LT3763_技术文档

LT3763

60V High Current

Step-Down LED Driver Controller

FeaTures

DescripTion

TheLT^®3763isafixedfrequency,synchronous,step-down

DC/DC controller designed to accurately regulate output

currents up to 20A. The average current mode control-

ler will maintain inductor current regulation over a wide

output voltage range from 0V to 55V. Output current is

set by analog voltages on the CTRL pins and an external

sense resistor. Voltage regulation and overvoltage protec-

tion are set with a voltage divider from the output to the

FB pin. The switching frequency is programmable from

200kHz to 1MHz through an external resistor on the RT

pin or with the SYNC pin and an external clock signal.

Input and output current sensing provides input current

limiting and an accurate measurement of these currents.

The FBIN pin is provided for applications requiring a peak

power tracking function.

n

Accurately Control Input and Output Current

n

3000:1 True Color PWM™ Dimming

n

±1ꢀ.5 ꢁoltage Regulation Accuracy

n

±±5 Current Regulation Accuracy

n

6V to 60V Input Voltage Range

n

Wide Output Range Up to 55V

n

<2µA Shutdown Current

n

Control Pin for Thermal Control of Load Current

n

Input and Output Current Monitor and Limit

n

Open, Short, and C/10 Fault Detection

n

PWM Driver Output for LED Applications

n

Thermally Enhanced 28-Lead FE Package

applicaTions

n

High Power Architectural Lighting

n

Automotive Lighting

Additional features include an accurate external reference

voltage for use with the CTRL pins, an accurate UVLO/

EN pin that allows for programmable UVLO hysteresis,

n

Aviation and Marine Strobe Lights

Solar-Powered Chargers, Laser Diodes

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and True

Color PWM is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents including 7199560, 7321203 and

others pending.

a PWM driver for LED applications, output voltage fault

detection, and thermal shutdown.

Typical applicaTion

20A, Pulse Width Modulated, Single LED Driver

2.5mΩ

V

IN

10V TO 30V

100µF

84.5k

15.4k

1µF

1k

4.7µF

PWM Dimming

V

IVINP

EN/UVLO

IVINN

IN

TG

220nF

V

REF

V

PWM

OUT

6V, 20A MAXIMUM

2.2µF

BOOST

SW

45.3k

1.5µH

2.5mΩ

10Ω

10V/DIV

LT3763

CTRL2

CTRL1

220µF

×2

V

SW

50V/DIV

INTV

CC

470k

47.5kΩ

22µF

33nF

10Ω

I

L

BG

50k

5A/DIV

GND

FBIN

+

SENSE

50Ω

3763 TA01b

5µs/DIV

IVINMON

1nF

–

SENSE

PWMOUT

ISMON

PWM

47.5k

FAULT

SYNC

RT

FB

SS

V

C

12.1k

82.5k

10nF

59k

4.7nF

3763 TA01

3763f

1

LT3763

absoluTe MaxiMuM raTings

pin conFiguraTion

(Note 1)

TOP VIEW

V , EN/UVLO, IVINP, and IVINN...............................60V

IN

1

2

GND

28

27

26

25

24

23

22

21

20

19

18

17

16

15

BG

INTV

+

–

SENSE and SENSE .................................................60V

CTRL1, CTRL2, FB, and FBIN ......................................3V

SYNC and PWM..........................................................6V

BOOST

SW

CC

3

V

IN

4

TG

EN/UVLO

INTV and FAULT.......................................................6V

CC

5

PWM_OUT

GND

V

REF

V , RT, and SS ............................................................3V

C

REF

6

IVINN

IVINP

IVINMON

FAULT

FBIN

V

, IVINMON, and ISMON........................................3V

7

PWM

SYNC

RT

29

GND

SW............................................................................60V

BOOST ......................................................................66V

BOOST-SW..................................................................6V

Operating Junction Temperature (Notes 2, 3)

LT3763E/LT3763I .............................. –40°C to 125°C

LT3763H ............................................ –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...................300°C

8

9

10

11

12

13

14

ISMON

V

C

FB

+

SENSE

GND

–

SENSE

CTRL2

CTRL1

SS

FE PACKAGE

28-LEAD PLASTIC TSSOP

θ

= 30°C/W

JA

EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH

LT3763EFE#PBF

LT3763IFE#PBF

LT3763HFE#PBF

TAPE AND REEL

PART MARKING*

LT3763FE

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LT3763EFE#TRPBF

LT3763IFE#TRPBF

LT3763HFE#TRPBF

28-Lead Plastic TSSOP

–40°C to 125°C

–40°C to 150°C

LT3763FE

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at T_A= 2.°Cꢀ ꢁ_IN= 12ꢁ, ꢁ_EN/UꢁLO= .ꢁ unless otherwise notedꢀ

PARAMETER

CONDITIONS

MIN

6

TYP

MAX

60

UNITS

Input Voltage Range

Supply Undervoltage Lockout

V

From Low to High

3.75

4.0

4.25

V

Pin Quiescent Current

Non-Switching Operation

Shutdown Mode

IN

V

= 1.4V, Not Switching

= 0V

1.7

0.2

3.5

2

mA

µA

EN/UVLO

EN/UVLO Pin Threshold (Falling Edge)

EN/UVLO Hysteresis

1.47

1.4

1.52

185

5

1.57

V

mV

µA

EN/UVLO Pin Current

EN/UVLO = 1.4V, V = 6V

IN

SYNC Pin Threshold (Falling Edge)

SYNC Pin Hysteresis

1.5

675

1.6

V

mV

3763f

2

LT3763

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at T_A= 2.°Cꢀ ꢁ_IN= 12ꢁ, ꢁ_EN/UꢁLO= .ꢁ unless otherwise notedꢀ

PARAMETER

CONDITIONS

MIN

TYP

1.5

675

20

MAX

UNITS

V

PWM Pin Threshold (Falling Edge)

PWM Pin Hysteresis

CTRL1 Pin Current

CTRL2 Pin Current

Reference

1.4

1.6

mV

nA

V

= 1.5V

CTRL1

= 1.5V, V

= 2V

FBIN

100

nA

CTRL1

CTRL2

l

Reference Voltage (V pin)

1.94

48

2

2.06

54

V

REF

Inductor Current Sensing

+

–

Full Range SENSE to SENSE

V

CTRL1

V

SENSE

V

SENSE

= 2V, V

> 2V, V = V

= 2V, V = 1.2V

51

mV

µA

CTRL2

–

SS

FBIN

C

+

SENSE Pin Current

= V

= 4V

–20

–40

SENSE

–

+

–

SENSE Pin Current

= 4V, V

= 1.5V

CTRL1

SENSE

Internal ꢁ Regulator (INTꢁ Pin)

CC

l

Regulation Voltage

I

= 10mA

4.8

5

5.2

V

LOAD

Current Limit

V

= 0V

60

mA

INTVCC

NMOS FET Driver

Non-Overlap Time TG to BG

Non-Overlap Time BG to TG

Minimum On-Time BG

Minimum On-Time TG

Minimum Off-Time BG

42

44

ns

(Note 4)

50

55

140

High Side Driver Switch On-Resistance

Gate Pull-Up

V

– V = 5V

CBOOST

SW

2.2

1.3

Ω

Gate Pull-Down

Low Side Driver Switch On-Resistance

Gate Pull-Up

V

= 5V

INTVCC

2.2

1

Ω

Gate Pull-Down

l

Switching Frequency

R = 40.2kΩ

T

930

180

1000

200

1070

220

kHz

T

R = 200kΩ

Soft-Start

Charging Current

ꢁoltage Regulation Amplifier

Input Bias Current

11

µA

V

= 1.3V

750

850

nA

µA/V

V

FB

g

m

+

–

l

Feedback Regulation Voltage

FAULT Comparator

= V

= V = 2V

CTRL1

1.188

1.137

0.24

1.206

1.224

1.183

0.26

SENSE

Upper FAULT Threshold (FB Rising)

Upper FAULT Threshold Hysteresis

Lower FAULT Threshold (FB Falling)

Lower FAULT Threshold Hysteresis

FAULT Pull-Down Current

Input ꢁoltage Regulation

FBIN Pin Current

1.16

40

V

mV

V

0.25

40

mV

mA

V

= 2V, V = 0V

8

FAULT

FB

= 1.5V

150

nA

FBIN

–

Sense Voltage

V

FBIN

V

FBIN

= 1.22V, V

= 1.26V, V

= 4V

10

45

mV

SENSE

+

–

(V

– V

)

SENSE

3763f

3

LT3763

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at T_A= 2.°Cꢀ ꢁ_IN= 12ꢁ, ꢁ_EN/UꢁLO= .ꢁ unless otherwise notedꢀ

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Output Current Monitor

Sense Voltage

–

V

Regulated to 1V, V

= 10V

45

5

50

10

55

15

mV

ISMON

SENSE

+

–

(V

– V

)

Regulated to 200mV, V

= 10V

SENSE

Input Current Monitor

+

Sense Voltage

V

Regulated to 1V, V

= 12V

46

6

50

10

54

14

mV

IVINMON

IVIN

+

–

+

(V

– V

)

Regulated to 200mV, V

= 12V

IVIN

l

Input Current Limit Sense Voltage

45

50

55

mV

+

–

(V

– V

)

IVIN

PWM Driver

PWM_OUT Driver On-Resistance

Gate Pull-Up

V

= 5V

INTVCC

2.2

0.9

Ω

Gate Pull-Down

PWM to PWM_OUT Propagation Delay

= 5V

INTVCC

Rising

Falling

11

38

ns

Current Control Loop g Amp

m

–

l

Offset Voltage

V

SENSE

= 4V, V

= 0V, V = 2V

CTRL2

–3

0

3

mV

CTRL1

Input Common Mode Range

V

(Note 5)

V

0

1.4

V

CM(LOW)

CM(HIGH)

+

–

Measured from V to V , V

= V

SENSE

CM(HIGH)

IN

CM SENSE

Output Impedance

3.5

475

1.7

MΩ

µA/V

V/mV

l

g

375

625

m

Differential Gain

Overvoltage

FB Overvoltage Protection (V Maximum)

1.515

85

V

FB

Overcurrent

–

Overcurrent Protection

V

SENSE

= 0V, R = 200kΩ, V = 1.2V

mV

T

VC

+

–

(V

– V

Maximum)

SENSE

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LT3763E is guaranteed to meet performance specifications

from 0°C to 125°C junction temperature. Specifications over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LT3763I is guaranteed to meet performance specifications over the

–40°C to 125°C operating junction temperature range. The LT3763H is

Note 3: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. The maximum

rated junction temperature will be exceeded when this protection is active.

Continuous operation above the specified absolute maximum operating

junction temperature may impair device reliability or permanently damage

the device.

Note 4: The minimum on- and off-times are guaranteed by design and are

not tested.

Note .: The minimum common mode voltage is guaranteed by design and

is not tested.

guaranteed over the –40°C to 150°C operating junction temperature range.

High junction temperatures degrade operating lifetimes; operating lifetime

is derated for junction temperatures greater than 125°C.

3763f

4

LT3763

Typical perForMance characTerisTics

EN/UꢁLO Threshold (Falling)

EN/UꢁLO Current

Quiescent Current (Shutdown)

6.0

5.5

5.0

4.5

4.0

10000

1000

100

10

1.70

1.64

1.58

1.52

1.46

1.40

6V

12V

60V

IN

1

0.1

0.01

0.001

6

24

42

60

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

6

24

42

60

V

(V)

V

(V)

IN

3763 G02

3763 G03

3763 G01

Quiescent Current (Non-Switching)

ꢁ_REFꢁoltage

ꢁ_REFCurrent Limit

1.5

1.4

1.3

1.2

1.1

1.0

0.9

3.0

2.5

2.0

1.5

2.03

2.02

2.01

2.00

1.99

6V

12V

60V

IN

T

= 150°C

= 25°C

= –50°C

T

= 150°C

= 25°C

= –50°C

A

6

24

42

60

6

24

42

60

–50 –25

0

25 50 75 100 125 150

V

IN

(V)

V

(V)

TEMPERATURE (°C)

IN

3763 G04

3763 G06

3763 G05

INTꢁ_CCCurrent Limit

RT Current Limit

SS Current

16

14

12

10

8

70

64

58

52

46

40

6

5

4

3

2

1

0

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

0

10

20

30

40

50

60

TEMPERATURE (°C)

I

(mA)

INTVCC

3763 G09

3763 G07

3763 G08

3763f

5

LT3763

Typical perForMance characTerisTics

ꢁ_INUꢁLO

ꢁ_BOOST– ꢁ_SWUꢁLO Thresholds

INTꢁ_CCUꢁLO

6.0

5.0

4.0

3.0

4.2

4.1

4.0

3.9

3.8

3.7

4.5

4.0

3.5

3.0

2.5

6V

12V

60V

IN

RISING

FALLING

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3763 G11

3763 G10

3763 G12

INTꢁ_CCLoad Regulation

Overvoltage Threshold

Overvoltage Timeout

14

13

12

11

10

1.55

1.53

1.51

1.49

1.47

1.45

5.10

5.05

5.00

4.95

4.90

–50 –25

0

25 50 75 100 125 150

0

10

20

30

40

50

60

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

I

(mA)

INTVCC

3763 G14

3763 G15

3763 G13

Overcurrent Threshold

Regulated Current vs ꢁ_FB

Maximum Output ꢁoltage

100

80

60

40

20

0

125

100

75

50

25

0

150

100

50

0

–50

–50 –25

0

25 50 75 100 125 150

0

0.5

1.0

– V

1.5

(V)

2.0

2.5

1.16

1.17

1.18

V

1.19

(V)

1.20

1.21

TEMPERATURE (°C)

V

FB

IN

OUT

3763 G16

3763 G17

3763 G18

3763f

6

LT3763

Typical perForMance characTerisTics

TG Driver R_DS(ON)

BG Driver R_DS(ON)

Nonoverlap Time

4

3

2

1

0

4

3

2

1

0

80

60

40

20

0

PULL-UP

BG TO TG

TG TO BG

PULL-DOWN

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3763 G19

3763 G20

3763 G21

Minimum On-Time

Oscillator Frequency

Minimum Off-Time

200

160

120

80

60

40

20

0

1.2

0.9

0.6

0.3

0

1MHz

HG

LG

HG

500kHz

200kHz

40

0

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3763 G22

3763 G23

3763 G24

Current Regulation Accuracy

Regulated Sense ꢁoltage

60

50

1.0

0.5

1.0

0.5

V

= 1.5V

V

= 0.75V

CTRL1

IN

CTRL1

IN

= 12V

40

30

0

20

10

0

–0.5

–1.0

–0.5

–1.0

0

0.5

1.0

1.5

2.0

0

2

4

6

8

10

0

2

4

6

8

10

V

(V)

V

(V)

V

(V)

CTRL1

OUT

3763 G25

3763 G26

3763 G27

3763f

7

LT3763

Typical perForMance characTerisTics

PWM Driver R_DS(ON)

PWM Driver Delay

C/10 Threshold

4

3

2

1

0

50

40

30

20

10

0

20

15

10

5

FALLING

PULL-UP

RISING

FALLING

RISING

PULL-DOWN

0

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3763 G28

3763 G29

3763 G30

FAULT Threshold

FAULT Hysteresis

Output Current Sense

1.6

1.2

0.8

0.4

0

75

50

25

0

2.0

1.5

1.0

0.5

0

UPPER

LOWER

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

0

25

V

50

– V

75

(mV)

100

+

–

TEMPERATURE (°C)

SENSE

3763 G33

3763 G31

3763 G32

Input Current Sense

Input Current Limit

Output ꢁoltage Load Regulation

2.0

1.5

1.0

0.5

0

55

53

51

49

47

45

8

6

4

2

0

V

= 12V

IN

= 5V

OUT

LIMIT

I

= 20A

0

25

50

– V

75

100

–50 –25

0

25 50 75 100 125 150

0

6

12

18

24

V

(mV)

I

(A)

TEMPERATURE (°C)

IVINP

IVINN

LOAD

3763 G34

3763 G36

3763 G35

3763f

8

LT3763

Typical perForMance characTerisTics

Output ꢁoltage Load Regulation

Efficiency vs Load Current

32

24

16

8

100

95

90

85

80

100

95

90

85

80

V

LIMIT

= 48V

IN

= 24V

= 10A

OUT

I

V

= 48V

OUT

V

= 12V

= 5V

IN

OUT

= 24V

0

3

6

9

12

0

6

12

18

24

0

3

6

9

12

I

(A)

I

(A)

I

(A)

LOAD

3763 G38

3763 G39

3763 G37

Shutdown and Recovery

1.A Load Step

V

OUT

V

OUT

5V/DIV

20mV/DIV

SS

AC-COUPLED

2V/DIV

EN/UVLO

5V/DIV

I

L

10A/DIV

I

L

5A/DIV

3763 G40

3763 G41

1ms/DIV

500µs/DIV

Solar Powered SLA Battery

Charging

PWM Dimming

FAULT

10V/DIV

I

L

V

IN

500mA/DIV

500mV/DIV

AC-COUPLED

V

SW

50V/DIV

I

L

2A/DIV

PWM

10V/DIV

V

OUT

50mV/DIV

AC-COUPLED

3763 G42

3763 G43

10µs/DIV

50s/DIV

3763f

9

LT3763

pin FuncTions

BG (Pin 1): BG is the bottom FET gate drive signal that

controls the state of the external low side power FET. The

driver pull-up impedance is 2.2Ω, and pull-down imped-

ance is 1Ω. Do not force any voltage on this pin.

IꢁINP (Pin 7): IVINP is the noninverting input of the input

current sense amplifier. This pin connects to the input

supply V and the input current sense resistor.

IN

IꢁINMON (Pin 8): IVINMON is the buffered output of the

input current sense amplifier. This pin enables monitoring

of the averaged supply current with an output voltage of

INTꢁ (Pin 2): The INTV pin provides a regulated 5V

CC

outputforchargingtheBOOSTcapacitor. INTV alsopro-

CC

vides the power for the digital and switching subcircuits.

20 • (V

– V

). The capacitive loading to this pin

IVINP

IVINN

Do not force any voltage on this pin. Bypass with at least

should be less than 1nF.

a 22µF capacitor to ground. INTV is current-limited to

CC

FAULT (Pin 9): Output Voltage Fault Detection Pin for

Shorted or Open LEDs. Internal comparators pull down

this pin when the FB pin voltage is lower than 0.25V or

higher than 1.16V and when the inductor current is less

than ten percent of the maximum value. This pin should

50mA. Shutdown operation disables the output voltage

drive.

ꢁ

(Pin 3): Input Supply Pin. Must be locally bypassed

IN

with at least a 4.7µF low ESR capacitor to ground as close

as possible to the exposed pad of the package.

be pulled up to INTV with a resistance higher than 10k.

CC

EN/UꢁLO (Pin 4): Enable Pin. The EN/UVLO pin acts as

an enable pin and turns on the internal current bias core

and sub-regulators at 1.705V and turns off at 1.52V. The

pin does not have any pull-up or pull-down, requiring a

voltage bias for normal operation. Full shutdown occurs

at approximately 0.5V. If unused, the Enable pin may be

FBIN (Pin 10): The FBIN pin enables peak power tracking

for solar powered chargers and other similar applications

by controlling the output current of the system based on

the input voltage. This pin should be tied to V

feature is not used.

if this

REF

FB (Pin 11): The feedback pin is used for voltage regula-

tion and overvoltage protection. The feedback voltage is

regulated to 1.206V. When the feedback voltage exceeds

1.515V, the overvoltage lockout prevents switching.

tied to V .

IN

ꢁ

(Pin .): Buffered 2V Reference Capable of 0.5mA

REF

Drive. Bypass with at least 1µF capacitor to ground.

IꢁINN (Pin ±): IVINN is the inverting input of the input

current sense amplifier. This pin connects to the drain of

the high side N-channel power FET and the input current

sense resistor.

3763f

10

LT3763

pin FuncTions

GND (Pin 12, Pin 23, Pin 28, Exposed Pad Pin 29):

Ground. The exposed pad must be soldered to the PCB.

RT (Pin 20): A resistor from the RT pin to ground sets the

switching frequency between 200kHz and 1MHz. When

using the SYNC function, set the frequency to be at least

20% lower than the SYNC pulse frequency. This pin is

current-limited to 55µA. Do not leave this pin open.

CTRL2 (Pin 13): Thermal Control Input to Reduce the

Regulated Output Current.

CTRL1 (Pin 14): The CTRL1 pin sets the regulated output

current. Themaximumcontrolvoltageis1.5V. Above1.5V,

there is no change in the regulated current.

SYNC (Pin 21): Frequency Synchronization Pin. This pin

allows the switching frequency to be synchronized to an

external clock. The RT resistor should be chosen to oper-

ate the internal clock at 20% slower than the SYNC pulse

frequency. This pin should be grounded when not in use.

SS(Pin1.):TheSoft-StartPin.Placeanexternalcapacitor

to ground to limit the regulated current during start-up

conditions. The soft-start pin has an 11µA charging cur-

rent. When the voltage at this pin is lower than voltages at

CTRL1andCTRL2,itoverridesbothsignalsanddetermines

the regulated current.

PWM (Pin 22): The input pin for PWM dimming of LEDs.

When low, all switching is terminated and the PWM_OUT

pin is low. This pin should be connected to INTV when

CC

not in use.

–

SENSE (Pin 1±): SENSE is the noninverting input of the

erroramplifierforthecurrentregulationloop.Thereference

current, based on CTRL1, CTRL2, SS or FBIN determines

PWM_OUT (Pin 24): This pin can drive an external FET

for PWM dimming of LEDs. The pull-up and pull-down

impedances of the driver are 2.2Ω and 0.9Ω, respectively.

Do not force any voltage on this pin.

+

–

the regulated voltage between SENSE and SENSE .

+

SENSE (Pin 17): SENSE is the inverting input of the

error amplifier for the current regulation loop. This pin

is connected to an external current sense resistor. The

TG (Pin 2.): TG is the top FET gate drive pin that controls

the state of the external high side power FET. The driver

pull-up impedance is 2.2Ω, and pull-down impedance is

1.3Ω. Do not force any voltage on this pin.

+

–

voltage drop between SENSE and SENSE is measured

against the voltage drop across an internal resistor at the

input to the current regulation loop.

SW (Pin 2±): The SW pin is used internally as the lower

railforthefloatingtopFETgatedriver. Externally, thisnode

connects the two power FETs and the inductor.

ꢁ (Pin 18): A resistor and capacitor connected in series

C

to the V pin provide the necessary compensation for the

C

stability of the average current loop. Typical values are 5k

BOOST (Pin 27): The BOOST pin provides a floating 5V

to 60k for the resistor and 2.2nF to 10nF for the capacitor.

regulated supply for the top FET gate driver. An external

schottky diode is required from the INTV pin to the

CC

ISMON (Pin 19): ISMON is the buffered output of the

outputcurrentsenseamplifier.Thisvoltageoutputenables

monitoring the averaged output current of the LED driver

BOOST pin to charge the BOOST capacitor when the SW

pin is near ground.

+

–

with a voltage of 20 • (V

– V

). The capacitive

SENSE

loading to this pin should be less than 1nF.

3763f

11

LT3763

block DiagraM

R

SENSE_IN

2.5mΩ

V

IN

C

IN2

47µF

R

FILTA

1k

FILTB

1k

C

FILT

1µF

C

IN1

4.7µF

C

VCC

22µF

7

6

3

2

27

BOOST

C

BOOST

200nF

IVINP

IVINN

V

INTV

CC

IN

HIGH SIDE

DRIVER

TG

SW

BG

25

26

1

SYNCHRONOUS

CONTROLLER

R

Q

LOW SIDE

DRIVER

S

INTERNAL

EN/UVLO

4

REGULATOR

AND UVLO

INPUT

CURRENT

MONITORING

+

–

SYNC

RT

21

20

V

REF

g

= 400µA/V

5

8

m

2V REFERENCE

C

REF

2.2µF

OSCILLATOR

1.5V

R

T

IVINMON

82.5k

CURRENT

MIRROR

R

C

47.5k

V

C

1.5V

+

18

24

22

CTRL1

CONTROL

BUFFER

C

4.7nF

L1

1µH

14

PWM_OUT

PWM

–

+

–

90k

–

0.1V

1.5V

ISMON

19

g

= 475µA/V

= 3.5M

CM(HIGH)

g

m

AMP

m

O

C/10

COMPARATOR

R

V

= V – 1.4V

IN

OUTPUT

MONITORING

+

SENSE

17

16

3k

R

S

2.5mΩ

–

SENSE

V

OUT

C

OUT

200µF

50k

11µA

×2

–

+

R

FB1

47.5k

SS

15

FB

C

SS

11

10nF

R

FB2

12.1k

1.206V

VOLTAGE

REGULATOR AMP

= 850µA/V

CTRL2

FBIN

13

10

g

m

1.16V

0.25V

+

–

INTV

CC

FAULT

1.206V

DETECTION

COMPARATORS

R

FAULT

47.5k

FAULT

9

GND (12, 23, 28, 29)

3763 BD

Figure 1ꢀ Block Diagram

3763f

12

LT3763

operaTion

TheLT3763utilizesfixedfrequency, averagecurrentmode

control to accurately regulate the inductor current inde-

pendentlyfromtheoutputvoltage. Thisisanidealsolution

for applications requiring a regulated current source. The

control loop will regulate the current in the inductor at

an accuracy of 6%. If the output reaches the regulation

voltage determined by the resistor divider from the output

to the FB pin, the inductor current will be reduced by the

voltage regulation loop. In voltage regulation, the output

voltage has an accuracy of 1.5%. For additional opera-

tion information, refer to the Block Diagram in Figure 1.

TheLT3763preventsexcessiveinductorcurrentbytrigger-

ing overcurrent limit when the inductor current produces

+

a voltage greater than 85mV across the SENSE and

–

SENSE pins. The current is limited on a cycle-by-cycle

basis; switching shuts down as soon as the overcurrent

level is reached. Overcurrent is not soft-started.

The regulated output voltage is set with a resistor divider

from the output to the FB pin. The reference for the FB

pin is 1.206V. If the output voltage level is high enough

to engage the voltage loop, the regulated inductor cur-

rent will be reduced. If the voltage at the FB pin reaches

1.515V, an internal overvoltage flag is set, shutting down

switching for 12μs.

The current control loop has two main inputs, determined

by the voltages at the analog control pins, CTRL1 and

CTRL2. The lower voltage between CTRL1 and CTRL2

determines the regulated output current. The voltages at

CTRL1 and CTRL2 are buffered to produce a reference

current set by the voltage across an internal 90k resistor.

This reference current produces a reference voltage that

the average current mode control loop uses to regulate

the inductor current as a voltage drop across the external

The EN/UVLO pin functions as a precision shutdown

pin. When the voltage at the EN/UVLO pin is lower than

1.52V, the internal reset flag is asserted and switching is

terminated. Full shutdown is guaranteed below 0.5V with

aquiescentcurrentoflessthan2µA. TheEN/UVLOpinhas

185mV of hysteresis built in, and a 5µA current source is

connected to this pin that allows any amount of hysteresis

to be added with a series resistor or resistor divider from

sense resistor, R . The outputs of the internal buffers are

S

clamped at 1.5V, limiting the control range of the CTRL1

V . Alternatively, this pin can be tied directly to V to

IN

and CTRL2 pins from 0V to 1.5V—corresponding to a

reduce the number of off-chip components.

0mV to 51mV range on R .

S

During start-up, the SS pin is held low until the internal

reset goes low and PWM goes high the first time after

a reset event. Once the reset is cleared, the capacitor

connected to the soft-start pin is charged with an 11μA

currentsource. Initially, theinternalbuffersfortheCTRL1,

CTRL2, and FBIN voltages are limited by the voltage at the

soft-start pin, and the inductor current reference slowly

increases to the level determined by the lowest voltage

of those three pins.

The FBIN pin provides a third input to the current control

loop. This input is dedicated to regulating the input volt-

age by controlling the inductor current. Inductor current

regulation commences when the voltage at the FBIN pin

riseshigherthan1.206V.Above1.206V,theinductorcurrent

is linearly increased, providing the maximum current, as

determined by the voltages at the CTRL pins, when FBIN

is at and above 1.26V. When input voltage regulation is

not needed, FBIN should be tied to V to allow the CTRL

REF

The rising threshold for thermal shutdown is set at 165°C

with–5°Chysteresis.Duringthermalshutdown,allswitch-

ing is terminated, and the part is in reset mode (forcing

the SS pin low).

pins to control the inductor current.

The 2V reference provided on the V

pin allows the

REF

use of a resistor voltage divider to the CTRL1 and CTRL2

pins. The current supplied by the V pin should be less

REF

The switching frequency is determined by a resistor at

the RT pin. This pin is limited to 55µA, which limits the

switching frequency to approximately 2MHz when the

RT pin is shorted to ground. The LT3763 may also be

synchronized to an external clock through the use of the

than 0.5mA.

The error amplifier for the average current mode control

loophasacommonmodelockoutthatregulatestheinduc-

tor current so that the error amplifier is never operated out

of the common mode range. The common mode range is

from ground to 1.4V below the V supply rail.

IN

3763f

13

LT3763

operaTion

SYNC pin which has precise thresholds at 2.175V and

1.5V for rising and falling edges, respectively.

informationsuchastheinputpowerandoutputpower.The

outputs of the current monitors, IVINMON and ISMON,

range from 0V to 1V when the inputs vary from 0V to

50mV. When using 2.5mΩ sense resistors, for example,

these current monitoring amplifiers sense from 0A to

20A. To filter out the switching portion of the currents

and measure the average current information, the input

pins of the input current monitor, IVINP and IVINN, should

connect to the sense resistor through two 1k resistors

and a capacitor directly between the IVINP and IVINN

pins. The capacitance value can be adjusted according to

the switching frequency and the ripple magnitude. The

outputcurrentmonitoremploysaninternalfiltertoreduce

ripple, and it does not require an external filter, but if one

is added, the corner frequency should be higher than the

switching frequency.

LT3763 also features a PWM driver for LED dimming.

PWM_OUTishighwhenthePWMpinvoltageishigherthan

2.175V, and low when PWM is lower than 1.5V. Switching

is terminated when PWM is lower than 1.5V. PWM should

be tied to INTV when the PWM function is not needed.

CC

The FAULT pin is pulled down to ground when the voltage

at FB becomes less than 0.25V which indicates a short-

circuit condition. It is also pulled down to indicate an

open-circuit condition when the voltage becomes greater

than1.16Vandtheinductorcurrentislessthantenpercent

of the maximum (C/10), or equivalently, when the volt-

age between SENSE and SENSE is less than 5mV. To

avoid jitter when recovering from a fault condition, 50mV

hysteresis is employed in the comparators. Additionally,

when the inductor current is lower than C/10, the C/10

comparator disables the low side MOSFET regardless of

the voltage at FB.

+

–

The LT3763 also includes an input current limiting func-

tion to regulate the input current to a value determined by

the R

SENSE_IN

resistor. When the voltage drop across the

SENSE_IN

R

resistor approaches 50mV, the inductor current

The integrated input current and output current monitor-

ing functions of the LT3763 allow users to acquire system

isreducedandregulatedsothat50mVismaintainedacross

the IVINP and IVINN pins.

applicaTions inForMaTion

Programming Inductor Current

30

25

The analog voltage at the CTRL1 pin is buffered and pro-

ducesareferencevoltage,V

,acrossaninternalresistor.

CTRL

20

15

The regulated average inductor current is determined by:

V_CTRL

I_O=

30•R_S

10

5

where R is the external sense resistor and I is the aver-

S

O

age inductor current, which is equal to the output current.

0

2

4

6

8

10 12 14 16 18 20

Figure 2 shows the maximum output current versus R .

S

R

S

(mΩ)

The maximum power dissipation in the resistor will be:

3763 F02

2

Figure 2ꢀ R_Sꢁalue Selection for Regulated Output Current

0.05V

R_S

(

)

P_RS=

maximum inductor current and sense-resistor power dis-

sipation. Susumu, Panasonic and Vishay offer accurate

sense resistors.

Figure 3 plots the power dissipation in R , and Table 1

lists several resistance values and the corresponding

S

3763f

14

LT3763

applicaTions inForMaTion

1.4

Table 2ꢀ Recommended Inductor Manufacturers

1.2

ꢁENDOR

WEBSITE

www.coilcraft.com

Coilcraft

1.0

Sumida

www.sumida.com

www.vishay.com

0.8

0.6

0.4

0.2

Vishay

Würth Electronics

NEC-Tokin

www.we-online.com

www.nec-tokin.com

Switching MOSFET Selection

0

2

4

8

10 12 14 16 18 20

0

6

The following parameters are critical in determining the

best switching MOSFETs for a given application: total gate

R

(mΩ)

S

3763 F03

charge(Q ), on-resistance(R

), gatetodraincharge

Figure 3ꢀ Power Dissipation in R_S

Table 1ꢀ Sense Resistor ꢁalues

G

DS(ON)

(Q ), gate-to-source charge (Q ), gate resistance (R ),

GD

GS

G

breakdown voltages (maximum V and V ) and drain

GS

DS

current (maximum I ). The following guidelines provide

D

MAXIMUM OUTPUT

CURRENT (A)

RESISTOR, R (mΩ) POWER DISSIPATION (W)

information to make the selection process easier, and

S

1

5

50

10

5

0.05

0.25

0.50

1.25

Table3listssomerecommendedpartsandmanufacturers.

ForbothswitchingMOSFETstherateddraincurrentshould

be greater than the maximum inductor current. Use the

following equation to calculate the peak inductor current:

10

25

2





V • V – V

Inductor Selection

IN

O

I

= I +

O

MAX





2 • f •L • V





IN

SW

Size the inductor so that the peak-to-peak ripple current

is approximately 30% of the output current.

The rated drain current is temperature dependent, and

most data sheets include a table or graph of the rated

drain current versus temperature.

The following equation sizes the inductor for best per-

formance:

2





The rated V should be higher than the maximum input

V • V – V

DS

IN

O

L =





voltage(includingtransients)forbothMOSFETs.Asforthe

0.3 • f •I • V





IN

SW

O

rated V , the signals driving the gates of the switching

GS

MOSFETshaveamaximumvoltageof5Vwithrespecttothe

source.However,duringstart-upandrecoveryconditions,

the gate-drive signals may be as low as 3V. Therefore, to

ensure that the LT3763 recovers properly, the maximum

threshold voltage should be less than 2V, and for a robust

where V is the output voltage, V is the input voltage,

O

IN

I is the maximum regulated current in the inductor and

O

SW

f

is the switching frequency.

The overcurrent comparator terminates switching when

+

–

thevoltagebetweentheSENSE andSENSE pinsexceeds

85mV. The saturation current for the inductor should be

at least 20% higher than the maximum regulated current.

RecommendedinductormanufacturersarelistedinTable2.

design, ensure that the rated V is greater than 7V.

GS

Power losses in the switching MOSFETs are related to the

on-resistance, R

; gate resistance, R ; gate-to-drain

DS(ON)

G

charge,Q andgate-to-sourcecharge,Q .Powerlostto

GD

GS

2

the on-resistance is an Ohmic loss, I R

, and usually

DS(ON)

dominates for input voltages less than 15V. Power lost

whilechargingthegatecapacitancedominatesforvoltages

3763f

15

LT3763

applicaTions inForMaTion

greater than 15V. When operating at higher input voltages,

efficiencycanbeoptimizedbyselectingahighsideMOSFET

7

6

5

with higher R

and lower Q . The total power loss in

G

DS(ON)

the high side MOSFET can be approximated by:

TOTAL

4

3

2

1

0

P

LOSS

= ohmic loss + transition loss

TRANSITIONAL









V_O

2

P

≈

•I_OR_DS(ON)•ρ_T+

LOSS





V

IN

OHMIC













Q

_GD+Q_GS•

(

)

V •I



_OUT

IN

10

20

INPUT VOLTAGE (V)

40

0

30

•

•f

















^SW

5V

2•R +R_PU+R_PD

)







G

3763 F04a

Figure 4aꢀ Power Loss Example for M1

where r is a dimensionless temperature dependent

T

factor in the MOSFET’s on-resistance. Using 70°C as the

maximum ambient operating temperature, r is roughly

2.5

2.0

T

equal to 1.3. R and R are the LT3763 high side gate

PD

PU

driver output impedances: 1.3Ω and 2.2Ω, respectively.

A good approach to MOSFET sizing is to select a high side

MOSFET, then select the low side MOSFET. The trade-off

1.5

TOTAL

between R

, Q , and Q for the high side MOSFET

DS(ON)

G GS

1.0

TRANSITIONAL

is evident in the following example. V is equal to 4V.

O

These two N-channel MOSFETs are rated for a V of 40V

0.5

0

OHMIC

DS

and mounted in the same package, but with 8× different

R

and 4.5× different Q and Q :

G GD

DS(ON)

0

10

20

30

40

INPUT VOLTAGE (V)

M1: R

= 2.3mΩ, Q = 45.5nC,

G

DS(ON)

3763 F04b

Q

GS

= 13.8nC, Q = 14.4nC, R = 1Ω

GD G

Figure 4bꢀ Power Loss Example for M2

M2: R

= 18mΩ, Q = 10nC,

G

DS(ON)

Q ,mustbechargedanddischargedeachswitchingcycle,

G

Q

GS

= 4.5nC, Q = 3.1nC, R = 3.5Ω

GD G

so the power lost to the charging of the gates is:

PowerlossforbothMOSFETsisshowninFigure4.Observe

that whereas the R of M1 is eight times lower, the

P

= V • (Q

+ Q ) • f

GATE

IN

GLG GHG SW

DS(ON)

where Q

high side gate charge.

is the low side gate charge and Q

is the

GLG

GHG

power loss at low input voltages is about equal to that of

M2, and at high voltages, it is four times higher.

The majority of this loss occurs in the internal LDO within

the LT3763:

Power loss within the low side MOSFET is almost entirely

from the R

of the FET. Select the low side FET with

DS(ON)

the lowest R

while keeping the total gate charge Q

P

≈ (V – 5V) • (Q

+ Q ) • f

GLG GHG SW

DS(ON)

G

LOSS_LDO

IN

to 30nC or less.

Whenever possible, utilize a switching MOSFET that

minimizes the total gate charge to limit the internal power

dissipation of the LT3763. Some recommended MOSFETs

are listed in Table 3.

AnotherpowerlossrelatedtoswitchingMOSFETselection

is the power lost driving the gates. The total gate charge,

3763f

16

LT3763

applicaTions inForMaTion

Table 3ꢀ Recommended Switching FETs

endofeverypulseasthedecreasinginductorcurrentflows

into the output capacitor. Use of a small output capacitor

may trigger overvoltage protection through the FB pin.

ꢁ

I

OUT

IN

OUT

(ꢁ) (ꢁ)

(A)

20 RJK0853DPB RJK0853DPB Renesas

www.renesas.com

TOP FET

BOTTOM FET MANUFACTURER

60

24

4

C

BOOT

Capacitor Selection

5

RJK0368DPA RJK0332DPB

48 10 to 35 10 RJK0851DPB RJK0851DPB

The C

capacitor must be sized no bigger than 220nF

BOOT

12 2 to 4 10

FDMS8680

FDMS8672AS Fairchild

www.fairchildsemi.com

and more than 50nF to ensure proper operation of the

LT3763. Use 220nF for high current switching MOSFETs

with high gate charge.

26

24

36

4

20

Si7884BDP

SiR470DP Vishay

www.vishay.com

40 PSMN4R0-30YL RJK0346DPA NXP/Philips

www.nxp.com

INTꢁ Capacitor Selection

CC

12

10 BSC100N06LS3 BSC100N06LS3 www.infineon.com

The bypass capacitor for the INTV pin should be larger

CC

than 22µF to ensure stability, and it should be connected

as close as possible to the exposed pad underneath

the package. It is recommended that the ESR be lower

than 50mΩ to reduce noise within the LT3763. For driv-

ing MOSFETs with gate charges larger than 44nC, use

0.5µF/nC of total gate charge.

Input Capacitor Selection

The input capacitor should be sized at least 2µF for every

1A of output current and placed very close to the high side

MOSFET. The loop created by the input capacitor, high side

MOSFET, lowsideMOSFETshouldbeminimized. Itshould

have a ripple current rating equal to half of the maximum

outputcurrent. Additionally, asmall4.7µFceramiccapaci-

Soft-Start

tor should be placed between V and ground as close as

Unlikeconventionalvoltageregulators,theLT3763utilizes

the soft-start function to control the regulated inductor

currentinsteadoftheoutputvoltage.Thechargingcurrent

is 11µA and reduces the set current as long as the SS pin

voltage is lower than CTRL1 and CTRL2.

IN

possible to the V pin and the exposed pad of the package

IN

for optimal noise immunity.

It is recommended that several low ESR (equivalent se-

ries resistance) ceramic capacitors be used as the input

capacitance,althoughothercapacitorswithhigherdensity

may be required to reduce board area. Only X5R or X7R

capacitors maintain their capacitance over a wide range

of operating voltages and temperatures.

Output Current Regulation

To adjust the regulated load current, an analog voltage is

applied to the CTRL1 pin. Figure 5 shows the regulated

voltage across the sense resistor for control voltages up to

Output Capacitor Selection

60

TheoutputcapacitorsneedtohaveverylowESRtoreduce

outputripple. Aminimumof20µF/Aofloadcurrentshould

be used in most designs. The capacitors also need to be

surge rated to the maximum output current. To achieve

the lowest possible ESR, several low ESR ceramic capaci-

tors should be used in parallel. Many lower output voltage

applications benefit from the use of high density POSCAP

capacitors, which are easily destroyed when exposed to

overvoltage conditions. To prevent this, select POSCAP

capacitors that have a voltage rating that is at least 50%

higher than the regulated voltage.

50

40

30

20

10

0

0.5

1.0

1.5

2.0

V

(V)

CTRL1

3763 F05

Figure .ꢀ Sense ꢁoltage vs CTRL ꢁoltage

Notethatwhendimming,theoutputvoltageincreasesatthe

3763f

17

LT3763

applicaTions inForMaTion

output current monitoring, the LT3763 enables users to

calculate the overall efficiency of the circuit including the

losses in the external components.

2V. Figure 6 shows the CTRL1 voltage created by a voltage

dividerfromV toground.Whensizingtheresistordivider,

REF

please be aware that the V pin should have a total load

REF

current less than 0.5mA, and that above 1.5V, the control

voltage has no effect on the regulated inductor current.

Setting CTRL1 to 0V does not automatically stop switch-

ing. To disable switching, set PWM pin voltage below 1.5V.

Output Current Monitoring

The LT3763 provides users the capability to monitor the

output current as a voltage provided at the ISMON pin.

The voltage will linearly increase from 0V to 1V as the

+

–

Input Current Monitoring

voltagebetweenSENSE andSENSE increasesfrom0mV

to 50mV as shown in Figure 8. If, for example, a 2.5mΩ

Users can monitor the input current at the IVINMON pin,

whichproduces0Vto1VasthevoltagebetweenIVINPand

IVINNvariesfrom0mVto50mV, asshowninFigure7. Due

to the switching of the high side FET, the input current is

noisyandmonitoringtheaverageinputcurrentrequiresan

externalfilterwith1kresistorsconnectingIVINPandIVINN

resistor is chosen for R , then a 1V output at ISMON will

S

indicate a 20A output current. A resistor and capacitor

may be connected to ISMON to filter noise.

ꢁoltage Regulation and Overvoltage Protection

to the input current sense resistor R

. Choose the

SENSE_IN

The LT3763 uses the FB pin to regulate the output volt-

age and to provide an overvoltage lockout to avoid high

voltage conditions. The regulated output voltage is pro-

grammed using a resistor divider from the output to the

FB pin (Figure 9). When the output voltage approaches

capacitorforthisfilteraccordingtotheswitchingfrequency

so that the noise is reduced by at least a factor of 100. If

the frequency is 500kHz, for example, 1µF is sufficient,

and higher switching frequencies will require a smaller

capacitor. A resistor and capacitor may be connected to

IVINMON to further filter the noise. With both input and

2.0

1.5

1.0

0.5

0

V

REF

LT3763

R2

R1

CTRL1

3763 F06

Figure ±ꢀ Analog Control of Inductor Current

2.0

0

25

50

– V

75

(mV)

100

+

–

V

SENSE

3763 F08

1.5

1.0

0.5

0

Figure 8ꢀ Output Current Monitoring ꢁoltage

vs Output Current Sense ꢁoltage

V

OUT

LT3763

R2

FB

R1

0

25

V

50

– V

75

100

(mV)

IVINP

IVINN

3763 F09

3763 F07

Figure 9ꢀ Output ꢁoltage Regulation and Overvoltage

Protection Feedback Connections

Figure 7ꢀ Input Current Monitoring ꢁoltage

vs Input Current Sense ꢁoltage

3763f

18

LT3763

applicaTions inForMaTion

the programmed level (1.206V at the FB pin), the voltage

Programming Switching Frequency

error amplifier overrides CTRL1 to set the inductor cur-

The LT3763 has an operational switching frequency range

between200kHzand1MHz.Thisfrequencyisprogrammed

with an external resistor from the RT pin to ground. Do not

leave this pin open under any condition. The RT pin is also

current-limitedto55µA.SeeTable4andFigure10forresis-

tor values and the corresponding switching frequencies.

rent and regulate V . When the output voltage exceeds

OUT

125% of the regulated voltage level (1.515V at the FB pin),

the internal overvoltage flag is set, terminating switching.

The regulated output voltage must be greater than 1.5V

and is set by the equation:

R2

R1





Table 4ꢀ Switching Frequency

SWITCHING FREQUENCY (MHz)

V_OUT=1.206V 1+









R (kΩ)

T

1.00

0.75

0.50

0.30

0.20

40.2

53.6

82.5

143

Fault Detection

The LT3763 detects that the load has had an open-circuit

or short-circuit event indicated by pulling the FAULT pin to

ground. These conditions are detected by comparing the

voltage at the FB pin to two internal reference voltages.

200

Switching Frequency Synchronization

A short-circuit is defined as V lower than 0.25V. In an

FB

open-circuit condition, the regulated inductor current will

charge the output capacitor, the voltage at FB will begin

to increase, and the voltage error amplifier will begin to

reducetheinductorcurrent.Theopen-circuitconditionwill

be indicated at FAULT when FB is higher than 1.16V and

the inductor current is less than ten percent (C/10) of the

The nominal switching frequency of the LT3763 is deter-

mined by the resistor from the RT pin to ground and may

be set from 200kHz to 1MHz. The internal oscillator may

alsobesynchronizedtoanexternalclockthroughtheSYNC

pin. The external clock applied to the SYNC pin must have

a logic low below 1.5V and a logic high above 2.175V. The

input frequency must be 20% higher than the frequency

that would otherwise be determined by the resistor at the

RT pin. Input signals outside of these specified parameters

will cause erratic switching behavior and subharmonic

oscillations. Synchronization is tested at 500kHz with

maximum value set by the sense resistor R . The output

S

voltage will be regulated as determined by the resistor

divider to the FB pin.

Low Current Detection

When the inductor current decreases to ten percent of the

maximum current, the C/10 comparator will also disable

the low side gate driver, so the converter will become

non-synchronous and automatically transition into dis-

continuous conduction mode when the inductor current

is low enough relative to the ripple.

a 200k R resistor. Operation under other conditions is

T

guaranteed by design. When synchronizing to an external

1.2

1.0

0.8

0.6

The low current condition is an essential part of battery

charging applications. The LT3763 works well in this ap-

plication delivering a constant current to the battery as it

charges and then automatically reducing the current to a

trickle charge as the battery voltage approaches its fully

charged value. In this application, the signal at FAULT

triggered by the low current detection comparator serves

as an indicator that the trickle charge phase of charging

the battery has begun.

0.4

0.2

0

50 100 150 200 250 300 350 400 450 500

(kΩ)

R

T

3763 F10

Figure 10ꢀ Frequency vs R_TResistance

3763f

19

LT3763

applicaTions inForMaTion

clock, please be aware that there will be a fixed delay from

the input clock edge to the edge of the signal at the SW pin.

The SYNC pin must be grounded if the synchronization to

an external clock is not required. When SYNC is grounded,

should be tied to INTV so as not to disable switching.

CC

PWM MOSFET Selection

The rated V for the PWM MOSFET need only be higher

DS

the switching frequency is determined by the resistor R .

T

than the maximum output voltage. Although this permits a

MOSFET choice with a smaller Q specification than that of

G

PWM Driver

theswitchingMOSFETs,itwillhavelittleeffectonefficiency,

because the PWM switching frequency will be much lower

thanthatoftheswitchingMOSFETs.Powerlostchargingthe

gate of the PWM MOSFET will naturally be much lower than

The LT3763 includes a PWM driver for users who want to

control the dimming of LEDs connected to the output. The

driverwillpullupthegateofanexternalN-channelMOSFET

connected to the PWM_OUT pin when the voltage at the

PWM pin rises above 2.175V and pull down the gate when

the power lost charging the switching MOSFETs. R

DS(ON)

conduction losses in the PWM MOSFET will also be much

thevoltagefallsbelow1.5V. WhenV

islowerthan1.5V,

smaller if the duty cycle of the PWM signal is very low.

PWM

switching is terminated and V is disconnected from the

C

Like the drivers for the switching MOSFETs, the PWM

current regulation amplifier. When V

is above 2.175V,

PWM

driver draws power from the INTV pin, and the choice

CC

theinductorcurrentisregulatedtothecurrentprogrammed

by the voltage at the CTRL1, CTRL2, or FBIN pins.

of MOSFET should follow the same recommendations for

thresholdvoltage(lessthan2V)andratedV (atleast7V).

GS

The pull-up driver impedance is 2.2Ω, and the pull-down

driverimpedanceis0.9Ω.ThePWMdimmingpulse-width

should be longer than two switching cycles.

Thermal Shutdown

The internal thermal shutdown within the LT3763 engages

at 165°C and terminates switching and discharges the

soft-start capacitor. When the part has cooled to 160°C,

the internal reset is cleared and the soft-start capacitor is

allowed to charge.

V

OUT

LOAD

PWM

1.5V

+

–

PWM_OUT

Shutdown and UꢁLO

3763 F11

The LT3763 has an internal UVLO that terminates switch-

ing, resets all synchronous logic, and discharges the soft-

start capacitor for input voltages below 4V. The LT3763

also has a precision shutdown at 1.52V on the EN/UVLO

pin. Partial shutdown occurs at 1.52V and full shutdown

Figure 11ꢀ PWM Driver Operation

PWM Operation

When the voltage at PWM is low, all switching of the high

and low side MOSFETS is terminated, and the inductor

current will decrease to zero. After PWM increases above

the logic threshold, the inductor current ramps up to the

is guaranteed below 0.5V with less than 2µA I in the full

Q

shutdown state. Below 1.52V, an internal current source

provides 5µA of pull-down current to allow for program-

mableUVLOhysteresis.Thefollowingequationsdetermine

the voltage-divider resistors for programming the UVLO

voltage and hysteresis as configured in Figure 12.

regulatedvalue. Theramptime, t , canbeestimatedusing

D

the following equation:

L•I_O

t_D=

V_HYST

R2=

V – V

IN

O

5µA

whichassumesthattheoutputcapacitordoesnotdischarge

significantly in the time that PWM is low.





1.52V •R2

R1=





V

–1.52V





UVLO

When the PWM functionality is not desired, the PWM pin

3763f

20

LT3763

applicaTions inForMaTion

V

• 11µA/V

CTRL

3k

V

IN

V

IN

LT3763

EN/UVLO

R2

L

R

S

MODULATOR

R1

LOAD

3763 F12

+

g

m

ERROR AMP

Figure 12ꢀ UꢁLO Configuration

3763 F14

R

C

–

Load Current Derating Using the CTRL2 Pin

C

The LT3763 is designed specifically for driving high power

loads. In high current applications, derating the maxi-

mum current based on operating temperature prevents

damage to the load. In addition, many applications have

thermal limitations that will require the regulated current

to be reduced based on load temperature and/or board

temperature. To achieve this, the LT3763 uses the CTRL2

pin to reduce the effective regulated current in the load,

which is otherwise programmed by the analog voltage at

the CTRL1 pin. The load/board temperature derating is

programmed using a resistor divider with a temperature

dependant resistance (Figure 13). When the load/board

temperature rises, the CTRL2 voltage will decrease. When

the CTRL2 voltage is lower than voltage at the CTRL1 pin,

the regulated current is reduced.

Figure 14ꢀ LT37±3 Average Current Mode Control Scheme

to the slope compensation ramp determines the stability

of the current regulation loop above 50% duty cycle. In

the same way, average current mode controllers require

the slope of the error voltage to not exceed the PWM ramp

slope during the switch off time.

Since the closed loop gain at the switching frequency

produces the error signal slope, the output impedance of

the error amplifier will be the compensation resistor, R .

C

Use the following equation as a good starting point for

compensation component sizing:

1kΩ•1V •L

V_O•R_S•T_SW

2nF

µs

R_C=

, C_C=

•T_SW

R

V

where T is the switching period, L is the inductance

V

SW

REF

value, V is the output voltage and R is the sense resistor.

O

S

R

X

LT3763

NTC

X

NTC

R2

For most applications, a 4.7nF compensation capacitor

is adequate and provides excellent phase margin with

optimized bandwidth. Please refer to Table 6 for recom-

mended compensation values.

CTRL2

3763 F13

R1

(OPTION A TO D)

A

B

C

D

Figure 13ꢀ Load Current Derating vs Temperature

Using NTC Resistor

Board Layout Considerations

Average current mode control is relatively immune to the

switching noise associated with other types of control

schemes.Nevertheless,thehighdi/dtloopformedbyinput

capacitors and switching MOSFETS should be minimized.

Average Current Mode Control Compensation

The use of average current mode control allows for pre-

cise regulation of the inductor current and load current.

Figure 14 shows the average current mode control loop

used in the LT3763, where the regulation current is pro-

grammed by a current source and a 3k resistor.

+

PlacingthesenseresistorascloseaspossibletotheSENSE

–

andSENSE pinsalsohelpsavoidnoiseissues.Duetosense

resistorESL(equivalentseriesinductance),10Ωresistors

+

–

inserieswiththeSENSE andSENSE pinswitha33nFca-

pacitorplacedbetweentheSENSEpinsarerecommended.

Utilizing a good ground plane underneath the switching

3763f

To design the compensation network, the maximum com-

pensation resistor needstobe calculated. In currentmode

controllers, the ratio of the sensed inductor current ramp

21

LT3763

applicaTions inForMaTion

components will minimize interplane noise coupling. To

dissipate the heat from the switching components, use a

large area for the switching node while keeping in mind

that this negatively affects the radiated noise.

Table ±ꢀ Recommended Compensation Component ꢁalues (ꢁ_CTRL2= 2ꢁ)

ꢁ

(ꢁ)

ꢁ (ꢁ)

ꢁ

(ꢁ)

I (A)

f

(kHz)

L (µH)

2.2

R (mΩ)

R (kΩ)

C (nF)

IN

O

CTRL1

L

SW

S

C

12

4

0.75

5

10

20

1

500

5

54.9

44.2

15.4

4.7

8.2

4.7

12

60

1.50

0.15

1.20

500

250

500

2.2

5

2.2

2.5

5

30

10

8

10

5

Typical applicaTions

20A, Pulse Width Modulated, Single LED Driver

R

SENSE_IN

2.5mΩ

V

IN

10V TO 30V

C

IN2

R

C

EN1

FILT

R

FILTA

1k

R

100µF

FILTB

84.5k

C

IN1

4.7µF

1µF

1k

R

EN2

15.4k

V

IVINP

EN/UVLO

IVINN

IN

M1

TG

C

BOOST

V

REF

220nF

C

L1

1.5µH

V

REF

R

S

OUT

R

HOT

BOOST

SW

2.2µF

6V, 20A MAXIMUM

2.5mΩ

45.3k

LT3763

C

OUT

CTRL2

CTRL1

220µF

R

470k

×2

NTC

INTV

CC

D1

R

SB

C

R

VCC

FAULT

R

22µF

47.5kΩ

SA

10Ω

BG

M2

10Ω

50k

GND

FBIN

+

SENSE

50Ω

C

S

IVINMON

33nF

1nF

–

SENSE

PWMOUT

M3

ISMON

R

FB1

1nF

FAULT

PWM

SYNC

RT

47.5k

FB

R

FB2

SS

V

C

L1: COILCRAFT XAL1010-152

M1: RENESAS RJK0365

M2: RENESAS RJK0453

M3: IR IRFH6200

12.1k

C

R

T

R

C

59k

C

3763 TA02

10nF

82.5k

C

4.7nF

R : VISHAY WSL25122L500FEA

S

PWM Dimming

PWM

10V/DIV

V

SW

50V/DIV

I

L

5A/DIV

3763 TA02b

5µs/DIV

3763f

22

LT3763

Typical applicaTions

1A, Five LED Driver

R

SENSE_IN

50mΩ

V

IN

32V TO 60V

C

IN2

C

FILT

R

FILTA

1k

R

4.7µF

FILTB

C

1µF

IN1

1k

1µF

V

IN

IVINP

IVINN

M1

ENABLE

EN/UVLO

TG

C

BOOST

V

50nF

L1

100µH

REF

V

R

OUT

S

C

REF

BOOST

SW

R

30V, 1A MAXIMUM

HOT

50mΩ

2.2µF

LT3763

45.3k

C

OUT

CTRL2

CTRL1

10µF

D1

×2

INTV

CC

R

NTC

470k

C

R

VCC

FAULT

D2

D3

D4

D5

R

SB

10Ω

22µF

47.5kΩ

SA

BG

M2

10Ω

50k

GND

+

SENSE

C

S

FBIN

33nF

–

SENSE

IVINMON

PWMOUT

ISMON

PWM

R

FB1

INTV

FAULT

CC

287k

SYNC

RT

FB

R

FB2

SS

V

C

L1: COILCRAFT MSS1278-104

M1, M2: RENESAS RJK1054

S

12.1k

C

R

T

R

C

59k

3763 TA03

R : VISHAY WSL2512R0500FEA

10nF

82.5k

C

4.7nF

3763f

23

LT3763

Typical applicaTions

3ꢀ3A, Six-Cell (3±ꢁ) SLA Battery Charger

R

SENSE_IN

15mΩ

V

IN

48V

C

IN2

C

FILT

R

FILTA

1k

R

47µF

FILTB

C

1µF

IN1

1k

1µF

V

IN

IVINP

IVINN

M1

ENABLE

EN/UVLO

TG

C

BOOST

V

220nF

L1

12µH

REF

V

R

OUT

S

C

REF

BOOST

SW

45V, 3.3A MAXIMUM

15mΩ

2.2µF

LT3763

CTRL2

CTRL1

+

12V

INTV

CC

C

R

+

VCC

FAULT

R

22µF

47.5kΩ

SA

SB

12V

BG

M2

10Ω

+

GND

12V

+

SENSE

C

S

FBIN

33nF

–

SENSE

IVINMON

PWMOUT

ISMON

PWM

R

FB1

INTV

FAULT

CC

402k

SYNC

RT

FB

R

FB2

R

SS

V

C

L1: WÜRTH 74471112

FB3

12.1k

178k

M1, M2: INFINEON BSC100N06LS3

M3: VISHAY VN2222LL

C

R

C

8.06k

C

4.7nF

T

10nF

82.5k

M3

R : VISHAY WSL2512R0150

S

C

3763 TA04

3±ꢁ SLA Battery Charging

FAULT

10V/DIV

I

L

2A/DIV

V

OUT

50mV/DIV

AC-COUPLED

3763 TA04b

50s/DIV

3763f

24

LT3763

Typical applicaTions

20A, Synchronized, .ꢁ Regulator

R

SENSE_IN

2.5mΩ

V

IN

7V TO 30V

C

IN2

R

C

EN1

FILT

R

FILTA

1k

R

100µF

FILTB

44.2k

C

1µF

IN1

1k

4.7µF

R

EN2

15.4k

IVINP

IVINN

V

IN

M1

EN/UVLO

TG

C

BOOST

V

220nF

L1

1.5µH

REF

V

R

OUT

S

C

REF

BOOST

SW

R

5V, 20A MAXIMUM

HOT

2.5mΩ

2.2µF

LT3763

45.3k

C

OUT

CTRL2

220µF

×2

INTV

CC

R

NTC

470k

C

R

VCC

FAULT

R

22µF

47.5kΩ

SA

SB

BG

M2

10Ω

CTRL1

FBIN

GND

+

SENSE

C

S

33nF

–

SENSE

IVINMON

ISMON

PWM

PWMOUT

R

FB1

INTV

FAULT

CC

38.3k

3V

0V

SYNC

RT

FB

R

FB2

SS

V

C

500kHz

L1: COILCRAFT XAL1010-152

M1: RENESAS RJK0365

M2: RENESAS RJK0453

12.1k

C

R

T

R

C

59k

C

3763 TA05

10nF

121k

R : VISHAY WSL25122L500FEA

S

C

4.7nF

Output ꢁoltage Load Regulation

Efficiency vs Load Current

8

6

4

2

0

100

95

90

85

80

V

= 12V

IN

= 5V

OUT

LIMIT

I

= 20A

V

= 12V

OUT

IN

= 5V

0

6

12

18

24

0

6

12

18

24

I

(A)

I

(A)

LOAD

3763 TA05b

3763 TA05c

3763f

25

LT3763

Typical applicaTions

350W White LED Driver

V

IN

48V

C

IN2

R

EN1

100µF

374k

C

IN1

4.7µF

R

EN2

124k

IVINP

IVINN

V

IN

M1

EN/UVLO

TG

×2

C

BOOST

V

220nF

L1

6µH

REF

V

R

OUT

S

C

REF

BOOST

SW

37V, 10A MAXIMUM

5mΩ

2.2µF

LT3763

C

OUT

CTRL2

10µF

×6

INTV

CC

C

R

VCC

FAULT

22µF

100k

M2

×2

BG

LUMINUS

PT-121

CTRL1

FBIN

GND

+

SENSE

C

S

1nF

–

SENSE

IVINMON

ISMON

PWM

PWMOUT

R

FB1

INTV

FAULT

CC

931k

3V

0V

SYNC

RT

FB

R

FB2

SS

V

C

400kHz

L1: COILTRONICS HC2-6R0

M1, M2: RENESAS RJK0851

S

30.9k

C

R

T

R

C

5k

3763 TA06

10nF

200k

R : VISHAY WSL25125L000

C

5nF

Maximum Output oltage

Efficiency vs LED Current

40

30

20

10

0

100

95

90

85

80

V

I

= 48V

= 10A

V

= 48V

IN

OUT

= 35V

LIMIT

0

3

6

9

12

0

3

6

9

12

I

(A)

I

(A)

LED

3763 TA06b

3763 TA06c

3763f

26

LT3763

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package

28-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663 Rev I)

Exposed Pad Variation EB

9.60 – 9.80*

(.378 – .386)

4.75

(.187)

4.75

(.187)

28 27 26 2524 23 22 21 20 1918 17 16 15

2.74

(.108)

EXPOSED

PAD HEAT SINK

ON BOTTOM OF

PACKAGE

6.60 ±0.10

4.50 ±0.10

SEE NOTE 4

6.40

2.74

(.252)

(.108)

BSC

0.45 ±0.05

1.05 ±0.10

0.65 BSC

RECOMMENDED SOLDER PAD LAYOUT

5

7

1

2

3

4

6

8

9 10 12 13 14

11

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

FE28 (EB) TSSOP REV I 0211

0.195 – 0.30

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

2. DIMENSIONS ARE IN

FOR EXPOSED PAD ATTACHMENT

MILLIMETERS

(INCHES)

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3. DRAWING NOT TO SCALE

3763f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LT3763

Typical applicaTion

70W, Solar Energy Harvester with Maximum Power Point Regulation

R

SENSE_IN

10mΩ

PANEL VOLTAGE

UP TO 60V

IN

C

IN2

37V V REG POINT

C

FILT

1µF

D1

D2

R

FILTA

1k

R

100µF

FILTB

C

IN1

1k

4.7µF

IVINP

IVINN

V

IN

M1

ENABLE

EN/UVLO

TG

Dn

C

BOOST

100nF

V

REF

L1

12µH

V

R

OUT

S

C

REF

BOOST

SW

R

14V MAXIMUM

HOT

10mΩ

2.2µF

LT3763

45.3k

CTRL2

CTRL1

+

3.6V

INTV

CC

R

NTC

470k

C

R

VCC

FAULT

R

22µF

47.5kΩ

SA

SB

BG

M2

10Ω

V

REF

GND

R

FBIN1

+

SENSE

348k

C

S

FBIN

33nF

–

SENSE

R

FBIN2

IVINMON

12.1k

PWMOUT

ISMON

PWM

R

FB1

INTV

FAULT

CC

121k

SYNC

RT

FB

R

FB2

R

SS

V

C

FB3

L1: COILCRAFT MSS1278-123

M1, M2: INFINEON BSC100N06LS3

M3: VISHAY VN2222LL

12.1k

182k

C

R

T

R

C

26.1k

C

4.7nF

10nF

82.5k

M3

R : VISHAY WSL2512R0100FEA

S

C

3763 TA07

Solar Powered SLA Battery

Charging

FAULT

10V/DIV

V

IN

500mV/DIV

AC-COUPLED

I

L

2A/DIV

V

OUT

50mV/DIV

3763 TA07b

50s/DIV

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

LT3743

LT3741

LT3791

Synchronous Step-Down LED Driver Controller

Synchronous Buck-Boost LED Driver Controller

92% Efficiency, I

to 20A, V : 5.5V to 36V, I = 2mA, I < 1µA, 4mm × 5mm

IN Q SD

OUT

QFN-28, TSSOP-28E

94% Efficiency, I

to 20A, V : 6V to 36V, I = 1.8mA, I < 1µA, 4mm × 4mm

IN Q SD

OUT

QFN-20, TSSOP-20E

98.5% Efficiency, I

to 25A, V : 4.7V to 60V, TSSOP-38E

OUT

IN

3763f

LT 1012 • PRINTED IN USA

28 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

 LINEAR TECHNOLOGY CORPORATION 2012

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3763
厂家：	Linear
描述：	60V High Current Step-Down LED Driver Controller Accurately Control Input and Output Current 60V高电流降压型LED驱动器控制器精确控制输入和输出电流驱动器控制器
文件：	总28页 (文件大小：374K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3763 [Linear]

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