LT3782AEFE [Linear]
2-Phase Step-Up DC/DC Controller; 两相升压型DC / DC控制器
| 型号： | LT3782AEFE |
| 厂家： | 
Linear |
| 描述： | 2-Phase Step-Up DC/DC Controller |
| 文件： | 总20页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3782A
2-Phase Step-Up
DC/DC Controller
FEATURES
DESCRIPTION
The LT®3782A is a current mode 2-phase step-up DC/DC
converter controller. Its high switching frequency (up to
500kHz) and 2-phase operation reduce system filtering
capacitance and inductance requirements.
n
2-Phase Operation Reduces Required Input and
Output Capacitance
n
Programmable Switching Frequency:
150kHz to 500kHz
6V to 40V Input Range
10V Gate Drive with V ≥13V
High Current Gate Drive (4A)
Programmable Soft-Start and Current Limit
Programmable Slope Compensation for
High Noise Immunity
MOSFET Gate Signals with Programmable
Falling Edge Delay for External Synchronous
Drivers
n
With 10V gate drive (V ≥13V) and 4A peak drive current,
CC
n
CC
the LT3782A can drive most industrial grade high power
MOSFETs with high efficiency. For synchronous applica-
tions, the LT3782A provides synchronous gate signals
with programmable falling edge delay to avoid cross
conduction when using external MOSFET drivers. Other
features include programmable undervoltage lockout,
soft-start, current limit, duty cycle clamp (50% or higher)
and slope compensation. The LT3782A is identical to the
LT3782exceptthattheLT3782Ahasatightercurrentsense
mismatch tolerance.
n
n
n
n
n
n
n
Programmable Undervoltage Lockout
Programmable Duty Cycle Clamp (50% or Higher)
Thermally Enhanced 28-Lead TSSOP and 4mm × 5mm
QFN Packages
The LT3782A is available in thermally enhanced 28-lead
TSSOP and 4mm × 5mm QFN packages.
APPLICATIONS
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6144194.
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Industrial Equipment
n
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Telecom Infrastructure
Interleaved Isolated Power Supply
TYPICAL APPLICATION
50V 4A Boost Converter
20μH
V
OUT
50V, 4A
V
IN
10V TO 36V
10μF
×2
D1
Efficiency and Power Loss
vs Load Current
V
GBIAS1
20μH
CC
1μF
GBIAS2
GBIAS
825k
274k
2μF
D2
+
97
95
93
91
89
87
85
18
15
12
9
10μF
×2
220μF
RUN
V
= 24V
IN
EFFICIENCY
BGATE1
V
= 12V
IN
LT3782A
0.004Ω
V
EE1
BGATE2
V
IN
= 12V
59k
SLOPE
DELAY
DCL
V
IN
= 24V
6
80k
POWER LOSS
0.004Ω
3
R
SET
V
EE2
+
10Ω
10nF
10Ω
10nF
0
SS
0
1
2
3
4
5
SENSE1
SENSE1
0.1μF
I
(A)
OUT
–
3782A TA01b
V
C
475k
+
–
13k
6.8nF
SENSE2
SENSE2
100pF
24.9k
FB
GND
3782A TA01
3782af
1
LT3782A
ABSOLUTE MAXIMUM RATINGS
(Note 1)
V
Supply Voltage ...................................................40V
SS........................................................... 300μA Max I
CC
SS
+
+
GBIAS, GBIAS1, GBIAS2 Pin
SENSE1 , SENSE2 ,
–
–
(Externally Forced)....................................................14V
SYNC, RUN Pin.........................................................30V
Operating Junction Temperature
SENSE1 , SENSE2 ..................................... –0.3V to 2V
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
Range (Notes 2, 3)................................. –40°C to 125°C
For FE Package...................................................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
1
2
GBIAS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SGATE2
SGATE1
NC
V
CC
3
NC
NC
28 27 26 25 24 23
4
GND
SYNC
DELAY
DCL
1
2
3
4
5
6
7
8
22 BGATE1
21
20
19
18
17
16
15
GBIAS1
NC
5
V
SYNC
DELAY
DCL
EE1
6
BGATE1
GBIAS1
GBIAS2
BGATE2
+
SENSE1
NC
7
29
29
–
SENSE1
+
GBIAS2
BGATE2
8
SENSE1
SLOPE
–
9
SENSE1
R
V
EE2
SET
10
11
12
13
14
V
SLOPE
EE2
–
SENSE2
NC
NC
R
SET
–
9
10 11 12 13 14
UFD PACKAGE
RUN
FB
SENSE2
SENSE2
+
V
C
SS
28-LEAD (4mm × 5mm) PLASTIC QFN
= 125°C, θ = 37°C/ W
FE PACKAGE
T
28-LEAD PLASTIC TSSOP
JMAX
JMAX
JA
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
T
= 125°C, θ = 25°C/ W
JA
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3782AEFE#PBF
LT3782AIFE#PBF
LT3782AEUFD#PBF
LT3782AIUFD#PBF
LEAD BASED FINISH
LT3782AEFE
TAPE AND REEL
PART MARKING*
LT3782AFE
LT3782AFE
3782A
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3782AEFE#TRPBF
LT3782AIFE#TRPBF
LT3782AEUFD#TRPBF
LT3782AIUFD#TRPBF
TAPE AND REEL
28-Lead Plastic TSSOP
–40°C to 85°C
28-Lead Plastic TSSOP
–40°C to 125°C
–40°C to 85°C
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
PACKAGE DESCRIPTION
3782A
–40°C to 125°C
TEMPERATURE RANGE
–40°C to 85°C
PART MARKING*
LT3782AFE
LT3782AFE
3782A
LT3782AEFE#TR
28-Lead Plastic SSOP
LT3782AIFE
LT3782AIFE#TR
28-Lead Plastic SSOP
–40°C to 125°C
–40°C to 85°C
LT3782AEUFD
LT3782AEUFD#TR
LT3782AIUFD#TR
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
LT3782AIUFD
3782A
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3782af
2
LT3782A
The ● denotes the specifications which apply over the full operating junction
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VCC = 13V, RSET = 80k, no load on any outputs, unless otherwise noted.
PARAMETER
Overall
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Supply Voltage (V
)
6
40
16
V
CC
Supply Current (I
Shutdown
)
V ≤ 0.5V (Switching Off), V ≤ 40V
11
mA
VCC
C
CC
RUN Threshold
2.3
2.45
80
2.6
V
RUN Threshold Hysteresis
Supply Current in Shutdown
mV
1V ≤ RUN ≤ V , V ≤ 30V
0.4
40
0.65
90
mA
μA
REF CC
RUN ≤ 0.3V, V ≤ 30V
CC
l
RUN Pin Input Current
V
RUN
= 2.3V
–0.5
–2
μA
Voltage Amplifier g
m
Reference Voltage (V
)
2.42
2.4
2.44
2.464
2.488
V
V
REF
l
l
l
Transconductance
V
= 1V, ΔI = 2μA
200
260
0.2
1.5
0.35
11
370
0.6
μmho
μA
V
VC
VC
Input Current I
V
= V
= 0
= 0
FB
FB
VC
VC
REF
V High
C
I
I
V Low
C
0.4
14
28
V
Source Current I
V
VC
= 0.7V – 1V, V = V – 100mV
8
13
0.3
6
μA
μA
V
VC
FB
REF
Sink Current I
V
VC
= 0.7V – 1V, V = V + 100mV
20
VC
FB
REF
l
V Threshold for Switching Off (BGATE1, BGATE2 Low)
C
Soft-Start Current I
V
= 0.1V – 2.8V
10
15
μA
SS
SS
Current Amplifier CA1, CA2
Voltage Gain ΔV /ΔV
4
C
SENSE
+
–
+
–
Current Limit (V
– V
) (V
– V
)
V
FB
= 2.3V
55
63
70
10
mV
mV
μA
SENSE1
SENSE1
SENSE2
SENSE2
Current Limit Mismatch
(ΔV
– ΔV
), V = 2.3V
–10
SENSE1
SENSE2
FB
+
–
+
–
Input Current (I
, I
, I
, I
)
ΔV
SENSE
= 0V
60
SENSE1 SENSE1 SENSE2 SENSE2
Oscillator
l
l
l
Switching Frequency
R
SET
R
SET
R
SET
= 130k
= 80k
= 40k
130
212
386
154
250
465
177
288
533
kHz
kHz
kHz
Synchronization Pulse Threshold on SYNC Pin
Rising Edge V
0.8
1.2
2
V
SYNC
Synchronization Frequency Range
(Note: Operation Switching Frequency Equals
Half of the Synchronization Frequency)
R
SET
R
SET
R
SET
= 130k
= 80k
= 40k
180
290
550
240
392
715
kHz
kHz
kHz
V
RSET
R
SET
= 80k
2.3
V
l
l
Maximum Duty Cycle
V
FB
= V – 25mV, R > 80k
90
83
94
90
%
%
REF
SET
SET
R
= 40k
Duty Cycle Limit
R
SET
= 80k, V
≤ 0.3V
= 1.2V
50
75
%
%
DCL
DCL
DCL
V
V
= V
Max Duty Cycle
RSET
l
DCL Pin Input Current
V
DCL
≤ 0.3V
–0.1
–0.3
μA
3782af
3
LT3782A
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = 25°C. VCC = 13V, RSET = 80k, no load on any outputs, unless otherwise noted.
PARAMETER
Gate Driver
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
I
< 70mA
GBIAS
10.2
11
11.7
10.5
V
GBIAS
l
l
BGATE1, BGATE2 High Voltage
13V ≤ V ≤ 24V, I
V
= –100mA
7.8
3.8
9.2
5
V
V
CC
BGATE
= 8V, I
= –100mA
CC
BGATE
BGATE1, BGATE2 Source Current (Peak)
Capacitive Load >22μF
Capacitive Load >50μF
3
4
A
A
l
l
BGATE1, BGATE2 Low Voltage
8V ≤ V ≤ 24V, I
= 100mA
0.5
0.7
V
CC
BGATE
BGATE1, BGATE2 Sink Current (Peak)
Capacitive Load >22μF
Capacitive Load >50μF
3
4
A
A
SGATE1, SGATE2 High Voltage
SGATE1, SGATE2 Low Voltage
SGATE1, SGATE2 Peak Current
Delay of BGATE High
8V ≤ V ≤ 24V, I
= –20mA
= 20mA
4.5
5.5
0.5
100
6.7
0.7
V
V
CC
SGATE
8V ≤ V ≤ 24V, I
CC
SGATE
500pF Load
mA
DELAY Pin and R Pin Shorted
100
150
250
500
ns
ns
ns
ns
SET
V
V
V
= 1V
= 0.5V
= 0.25V
DELAY
DELAY
DELAY
l
Delay Pin Input Current
V
DELAY
= 0.25V
–0.1
–0.3
μA
to meet performance specifications over the full –40°C to 125°C operating
junction temperature range.
Note 3: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3782AE is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LT3782AI is guaranteed
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
ΔVREF vs VCC, ΔFrequency vs VCC
(RSET = 80k)
VGBIAS vs IGBIAS
ICC vs VCC
11.0
10.9
10.8
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10.0
20
18
16
14
12
10
8
3
2
12
10
8
1
ΔV
REF
0
6
–1
–2
–3
–4
–5
4
2
ΔFREQUENCY
6
0
4
–2
–4
2
0
50
(mA)
0
100
6
8
10 12 14 16 18 20 22 24 26 28 30
(V)
6
9
12
15 18
(V)
21 24 27 30
I
V
CC
GBIAS
V
CC
3782A G01
3782A G02
3782A G03
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4
LT3782A
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Current Limit Threshold
vs Temperature
Reference Voltage
vs Temperature
Switching Frequency vs RFREQ
600
500
400
300
200
100
2.446
2.444
2.442
2.440
2.438
2.436
2.434
70
67
64
61
58
55
0
20 40 60 80 100 120 140 160 180 200
(kΩ)
30
55
–45 –20
5
80 105 130
0
25
75
100
125
150
50
R
JUNCTION TEMPERATURE (°C)
TEMPERATURE (°C)
FREQ
3782A G04
3782A G10
3782A G05
SGATE (Low) to BGATE (High)
Delay vs VDELAY (RSET = 80k)
VGBIAS vs IGBIAS at Start-Up
(Charging 2μF)
1000
900
800
700
600
500
400
300
200
100
0
14
800
700
600
500
400
300
200
100
0
12
10
8
V
GBIAS
6
4
I
GBIAS
2
0
–2
0
0.5
1.0
V
1.5
(V)
2.0
2.5
0
250μ
500μ
750μ
1m
TIME (s)
DELAY
3782A G07
3782A G06
Switching Frequency
vs Duty Cycle
Maximum Duty Cycle Limit
vs VDCL (RSET = 80k)
105
100
95
120
110
100
90
80
90
70
60
85
50
40
80
0.9 1.2
(V)
100
200
300
400
500
600
0
0.3 0.6
1.5 1.8 2.1 2.4
SWITCHING FREQUENCY (kHz)
V
DCL
3782A G08
3782A G09
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5
LT3782A
PIN FUNCTIONS (FE/UFD)
SGATE2(Pin1/Pin26):SecondPhaseSynchronousDrive V (Pin15/Pin12):Theoutputoftheg erroramplifierand
C
m
Signal. An external driver buffer is needed to drive the top the control signal of the current loop of the current-mode
synchronous power FET.
PWM. Switching starts at 0.7V, and higher V voltages
C
corresponds to higher inductor current.
SGATE1 (Pin 2/Pin 27): First Phase Synchronous Drive
Signal. An external driver buffer is needed to drive the top FB (Pin 16/Pin 13): Error Amplifier Inverting Input. A
synchronous power FET.
resistor divider to this pin sets the output voltage.
GND (Pin 4/Pin 28): Ground.
RUN (Pin 17/Pin 14): LT3782A goes into shutdown mode
when V
is below 2.2V and goes to low bias current
RUN
SYNC (Pin 5/Pin 1): Synchronization Input. The pulse
widthcanrangefrom10%to70%. Notethattheoperating
frequency is half of the sync frequency.
shutdown mode when V
is below 0.3V.
RUN
V
(Pin 19/Pin 16): Gate Driver BGATE2 Ground. This
EE2
pin should be connected to ground as close to the IC as
DELAY(Pin6/Pin2):Whensynchronousdriversareused,
the programmable delay that delays BGATE turns on after
SGATE turns off.
possible.
BGATE2 (Pin 20/Pin 17): Second Phase MOSFET Driver.
DCL (Pin 7/Pin 3): This pin programs the limit of the maxi- GBIAS2 (Pin 21/Pin 18): Bias for Gate Driver BGATE2.
mum duty cycle. When connected to V
, it operates at ShouldbeconnectedtoGBIASoranexternalpowersupply
RSET
natural maximum duty cycle, approximately 90%.
between 12V to 14V. A bypass low ESR capacitor of 2μF
or larger is needed and should be connected directly to
the pin to minimize parasitic impedance.
+
SENSE1 (Pin8/Pin4):FirstPhaseCurrentSenseAmplifier
Positive Input. An RC filter is required across the current
sense resistor. Current limit threshold is set at 63mV.
GBIAS1 (Pin 22/Pin 21): Bias for Gate Driver BGATE1.
Should be connected to GBIAS2.
–
SENSE1 (Pin9/Pin5):FirstPhaseCurrentSenseAmplifier
Negative Input. An RC filter is required across the current BGATE1 (Pin 23/Pin 22): First Phase MOSFET Driver.
sense resistor.
V
(Pin 24/Pin 23): Gate Driver BGATE1 Ground. This
EE1
SLOPE (Pin 10/Pin 6): A resistor from SLOPE to GND pin should be connected to ground as close to the IC as
increases the internal current mode PWM slope com- possible.
pensation.
V
(Pin 27/Pin 24): Chip Power Supply. Good supply
CC
R
(Pin 11/Pin 7): A resistor from R to GND sets the bypassing is required.
SET
SET
oscillator charging current and the operating frequency.
GBIAS (Pin 28/Pin 25): Internal 11V regulator output for
–
SENSE2 (Pin 12/Pin 8): Second Phase Current Sense biasing internal circuitry. Should be connected to GBIAS1
Amplifier Negative Input. An RC filter is required across and GBIAS2.
the current sense resistor.
Exposed Pad (Pin 29/Pin 29): The exposed package pad
SENSE2 (Pin 13/Pin 10): Second Phase Current Sense is fused to internal ground and is for heat sinking. Solder
+
Amplifier Positive Input. An RC filter is required across the bottom metal plate onto expanded ground plane for
the current sense resistor. Current limit threshold is set optimum thermal performance. This pad should be con-
at 63mV.
nected to ground as close to the IC as possible.
SS (Pin 14/Pin 11): Soft-Start. A capacitor on this pin sets NC(Pins3,18,25,26/Pins9,15,19,20):NotConnected.
the output ramp up rate. The typical time for SS to reach Can be connected to GND.
the programmed level is (C • 2.44V)/10μA.
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6
LT3782A
BLOCK DIAGRAM
V
V
OUT
IN
L1
D1
V
CC
15μH
V
GBIAS
= V – 1V AND CLAMPED AT 11V
CC
C
IN
20μF
27
REGULATOR
L2
D2
GBIAS1
+
15μH
C
LOW POWER
SHUTDOWN
OUT
100μF
22
21
28
+
–
+
–
+
R6
R8
GBIAS2
GBIAS
C3
2μF
A5
A11
A8
RUN
17
–
+
+
+
0.5V
7V
A6
V
– 2.5V
R
F1
CC
+
–
R
F2
A7
+
A20
2.44V
SGATE1
DELAY
2
6
A4
A1
ONE SHOT
GBIAS1
A9
R
SET
+
–
+
A12
2.5V
BGATE1
BGATE1
A13
23
8
M1
R
A14
R1
50k
SLOPE COMP
CH1
R7
+
–
SENSE1
SENSE1
S1
10Ω
C2
2nF
+
BLANKING
PWM1
R3
9
V
EE1
–
+
24
A3
BGATE1
CL1
–
+
SGATE1
SET
DELAY
60mV
SGATE2
1
A15
A17
+
–
+
A16
2.5V
DELAY
BGATE2
ONE SHOT
GBIAS2
BGATE2
A18
A2
20
13
M2
A19
R2
50k
SLOPE COMP
CH2
R9
+
–
R
S2
SENSE2
SENSE2
10Ω
SET
SLOPE
SYNC
C4
2nF
+
BLANKING
CH1
CH2
SLOPE
COMP
PWM2
10
5
R4
S
R
S
R
12
19
V
EE2
–
A10
R
SET
D6
D7
FB
11
OSC
CK
D
Q
Q
+
–
16
–
3782A BD
LOGIC
R
FREQ
+
GM
C5
20pF
NOTE:
CL2
PACKAGE BOTTOM METAL PLATE (PIN 29)
IS FUSED TO CHIP DIE AGND
V
REF
+
GND
I1
10μA
60mV
4
D4
4V
V
C
SS
14
7
15
R5
2k
C7
10nF
DCL
C1
2000pF
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7
LT3782A
APPLICATIONS INFORMATION
Operation
Soft-Start and Shutdown
The LT3782A is a two phase constant frequency current During soft-start, the voltage on the SS pin (V ) controls
SS
mode boost controller. Switching frequency can be pro- the output voltage. The output voltage thus ramps up fol-
grammed up to 500kHz. During normal switching cycles, lowing V . The effective range of V is from 0V to 2.44V.
SS
SS
the two channels are controlled by internal flip-flops and The typical time for the output to reach the programmed
are 180 degrees out-of-phase.
level is
Referring to the Block Diagram, the LT3782A’s basic func-
C •2.44V
10μA
t=
tionsincludeatransconductanceamplifier(g )toregulate
m
the output voltage and to control the current mode PWM
current loop. It also includes the necessary logic and flip- C is the capacitor connected from the SS pin to GND.
flop to control the PWM switching cycles, two high speed
Undervoltage Lockout and Shutdown
gate drivers to drive high power N-channel MOSFETs, and
2-phase control signals to drive external gate drivers for
optional synchronous operation.
Only when V is higher than 2.45V V
will be active
GBIAS
RUN
and the switching enabled. The LT3782A goes into low
current shutdown when V is below 0.3V. A resistor
In normal operation, each switching cycle starts with a
switch turn-on. The inductor current of each channel is
sampled through the current sense resistor and amplified
RUN
divider can be used on RUN pin to set the desired V
CC
undervoltage lockout voltage. 80mV of hysteresis is built
in on RUN pin thresholds.
then compared to the error amplifier output V to turn
C
the switch off. The phase delay of the second channel is
controlled by the divide-by-two D flip-flop and is exactly
180 degrees out-of-phase of the first channel. With a re-
sistor divider connected to the FB pin, the output voltage
is programmed to the desired value. The 10V gate drivers
aresufficienttodrivemosthighpowerN-channelMOSFET
in many industrial applications.
Oscillation Frequency Setting and Synchronization
The switching frequency of LT3782A can be set up to
500kHz by a resistor R
from pin R to ground.
FREQ
SET
For f = 250kHz, R
= 80k
FREQ
SET
Oncetheswitchingfrequencyf ischosen, R
canbe
SET
FREQ
foundfromtheSwitchingFrequencyvsR
graphfound
FREQ
Additional important features include shutdown, cur-
rent limit, soft-start, synchronization and programmable
maximum duty cycle. Additional slope compensation can
be added also.
under the Typical Performance Characteristics section.
Note that because of the 2-phase operation, the internal
oscillator is running at twice the switching frequency. To
synchronizetheLT3782Atothesystemfrequencyf
,
SYSTEM
Output Voltage Programming
the synchronizing frequency f
should be two times
SYNC
f
,andtheLT3782Aswitchingfrequencyf should
SYSTEM
SET
With a 2.44V feedback reference voltage V , the output
REF
be set below 80% of f
.
SYSTEM
V
is programmed by a resistor divider as shown in
OUT
the Block Diagram.
f
= 2f
and f < (f
• 0.8)
SYNC
SYSTEM
SET
SYSTEM
ꢀ
ꢃ
ꢅ
ꢄ
RF1
RF2
For example, to synchronize the LT3782A to 200kHz sys-
tem frequency f , f needs to be set at 400kHz
VOUT = 2.44 1+
ꢂ
SYSTEM SYNC
ꢁ
and f
needs to be set at 160kHz. From the Switching
SET
Frequency vs R
graph found under the Typical Per-
FREQ
formance Characteristics section, R
= 130k.
FREQ
3782af
8
LT3782A
APPLICATIONS INFORMATION
Witha200nsone-shottimeronchip,theLT3782Aprovides
flexibility on the external sync pulse width. The sync pulse
threshold is about 1.2V (Figure 1). This pin can be floated
when the sync function is not used.
Synchronous Rectifier Switches
For high output voltage applications, the power loss of the
catchdiodesarerelativelysmallbecauseofhighdutycycle.
If diodes power loss or heat is a concern, the LT3782A
provides PWM signals through SGATE1 and SGATE2 pins
to drive external MOSFET drivers for synchronous recti-
fier operation. Note that SGATE drives the top switch and
BGATEdrivesthebottomswitch.Toavoidcrossconduction
between top and bottom switches, the BGATE turn-on is
Current Limit
Current limit is set by the 63mV threshold across SEN1P,
SEN1N for channel one and SEN2P, SEN2N for channel
two. By connecting an external resistor R (see Block
S
Diagram), the current limit is set for 63mV/R . R should
S
S
delayed 100ns (when DELAY pin is tied to R pin) from
SET
be placed very close to the power switch with very short
traces. A low pass R filter is needed across R to filter out
SGATE turn-off (see Figure 2). If a longer delay is needed
C
S
to compensate for the propagation delay of external gate
the switching spikes. Good Kelvin sensing is required for
accurate current limit. The input bypass capacitor ground
should be at the same ground point of the current sense
resistor to minimize the ground current path.
driver,aresistordividercanbeusedfromR togroundto
SET
program V
for the longer delay needed. For example,
DELAY
for a switching frequency of 250kHz and delay of 150ns,
5V TO 20V
5k
LT3782A
SYNC
VN2222
3782A F01
PULSE WIDTH > 200ns
Figure 1. Synchronizing with External Clock
BGATE1
SGATE1
SET
DELAY
3782A F02
Figure 2. Delay Timing
3782af
9
LT3782A
APPLICATIONS INFORMATION
Layout Considerations
then R
+ R
RSET
should be 80k and V
should
FREQ1
be 1V, with V
FREQ2
= 2.3V then R
DELAY
= 47.5k and R
FREQ1 FREQ2
To prevent EMI, the power MOSFETs and input bypass
capacitor leads should be kept as short as possible. A
groundplaneshouldbeusedundertheswitchingcircuitry
to prevent interplane coupling and to act as a thermal
spreading path. Note that the bottom pad of the package
is the heat sink, as well as the IC signal ground, and must
be soldered to the ground plane.
= 32.5k (see Figure 3).
Duty Cycle Limit
When DCL pin is shorted to R
quency is less than 250kHz (R
pin and switching fre-
SET
> 80k), the maximum
FREQ
duty cycle of LT3782A will be at least 90%. The maximum
duty cycle can be clamped to 50% by grounding the DCL
Inaboostconverter, theconversiongain(assuming100%
efficiency) is calculated as (ignoring the forward voltage
drop of the boost diode):
pin or to 75% by forcing the V
voltage to 1.2V with a
DCL
resistor divider from R pin to ground. The typical DCL
SET
pin input current is 0.2μA.
VOUT
1
1−D
=
Slope Compensation
V
IN
The LT3782A is designed for high voltage and/or high
current applications, and very often these applications
generate noise spikes that can be picked up by the cur-
rent sensing amplifier and cause switching jitter. To avoid
switching jitter, careful layout is absolutely necessary to
minimize the current sensing noise pickup. Sometimes
increasing slope compensation to overcome the noise
can help to reduce jitter. The built-in slope compensa-
where D is the duty ratio of the main switch. D can then
be estimated from the input and output voltages:
V
V
VOUT
IN(MIN)
IN
D=1−
;DMAX =1−
VOUT
tion can be increased by adding a resistor R
from
SLOPE
SLOPE pin to ground. Note that smaller R
slope compensation and the minimum R
/2.
increases
SLOPE
SLOPE
allowed is
R
FREQ
DELAY
LT3782A
R
SET
R
FREQ1
47.5k
3782A F03
R
FREQ2
32.5k
Figure 3. Increase Delay Time
3782af
10
LT3782A
APPLICATIONS INFORMATION
The Peak and Average Input Currents
And the inductance is estimated to be:
The control circuit in the LT3782A measures the input cur-
rent by using a sense resistor in each MOSFET source, so
the output current needs to be reflected back to the input
in order to dimension the power MOSFET properly. Based
on the fact that, ideally, the output power is equal to the
input power, the maximum average input current is:
IO(MAX)
V •D
fs • ΔIL
IN
L=
where f is the switching frequency per phase.
s
The saturation current level of inductor is estimated to
be:
I
=
IN(MAX)
IOUT(MAX) • VOUT
ΔIL
2
I
IN
2
1–DMAX
The peak current is:
ISAT
≥
+
≅70%•
V
IN(MIN)
IO(MAX)
IIN(PEAK) =1.2•
Sense Resistor Selection
1–DMAX
During the switch on-time, the control circuit limits the
maximum voltage drop across the sense resistor to about
63mV. The peak inductor current is therefore limited to
63mV/R. The relationship between the maximum load
The maximum duty cycle, D
, should be calculated at
MAX
minimum V .
IN
Power Inductor Selection
current, duty cycle and the sense resistor R
is:
SENSE
In a boost circuit, a power inductor should be designed
to carry the maximum input DC current. The inductance
should be small enough to generate enough ripple current
to provide adequate signal to noise ratio to the LT3782A.
An empirical starting of the inductor ripple current (per
phase) is about 40% of maximum DC current, which is
half of the input DC current in a 2-phase circuit:
1–DMAX
R≤ VSENSE(MAX)
•
IO(MAX)
1.2•
2
Power MOSFET Selection
Important parameters for the power MOSFET include the
drain-to-sourcebreakdownvoltage(BV ),thethreshold
DSS
DS(ON)
IOUT(MAX) • VOUT
IOUT(MAX) • VOUT
ΔIL ≅40%•
=20%•
voltage(V
),theon-resistance(R
)versusgate-
GS(TH)
2V
V
IN
IN
to-source voltage, the gate-to-source and gate-to-drain
charges (Q and Q , respectively), the maximum drain
GS
D(MAX)
and R
GD
where V , V
and I
are the DC input voltage, output
IN OUT
OUT
current (I
) and the MOSFET’s thermal resistances
voltage and output current, respectively.
(R
).
TH(JC)
TH(JA)
3782af
11
LT3782A
APPLICATIONS INFORMATION
The gate drive voltage is set by the 10V GBIAS regulator.
Consequently, 10V rated MOSFETs are required in most
high voltage LT3782A applications.
voltage and temperature), and for the worst-case speci-
fications for V and the R of the MOSFET
SENSE(MAX)
listed in the manufacturer’s data sheet.
DS(ON)
Pay close attention to the BV
specifications for the
The power dissipated by the MOSFET in a 2-phase boost
converter is:
DSS
MOSFETs relative to the maximum actual switch voltage
in the application. The switch node can ring during the
turn-off of the MOSFET due to layout parasitics. Check the
switching waveforms of the MOSFET directly across the
drainandsourceterminalsusingtheactualPCboardlayout
(not just on a lab breadboard!) for excessive ringing.
ꢀ
ꢂ
ꢁ
ꢃ 2
ꢅ
IO(MAX)
2
ꢄ
PFET
=
•RDS(ON) •D •ꢆT
1–D
(
)
ꢀ
ꢂ
ꢁ
ꢃ
ꢅ
ꢄ
IO(MAX)
2
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
2
+k • VO •
•CRSS • f
1–D
2
In order to calculate the junction temperature of the power
MOSFET,thepowerdissipatedbythedevicemustbeknown.
This power dissipation is a function of the duty cycle, the
load current and the junction temperature itself (due to
The first term in the equation above represents the I R
losses in the device, and the second term, the switching
losses.Theconstant,k=1.7,isanempiricalfactorinversely
related to the gate drive current and has the dimension
the positive temperature coefficient of its R
). As a
DS(ON)
of 1/current. The ρ term accounts for the temperature
T
result, some iterative calculation is normally required to
determine a reasonably accurate value. Care should be
taken to ensure that the converter is capable of delivering
therequiredloadcurrentoveralloperatingconditions(line
coefficientoftheR
oftheMOSFET, whichistypically
DS(ON)
0.4%/°C. Figure 4 illustrates the variation of normalized
R
over temperature for a typical power MOSFET.
DS(ON)
2.0
1.5
1.0
0.5
0
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
3782A F04
Figure 4. Normalized RDS(ON) vs Temperature
3782af
12
LT3782A
APPLICATIONS INFORMATION
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
willfurtherreducetheinputcapacitorripplecurrentrating.
The ripple current is plotted in Figure 5. Please note that
the ripple current is normalized against:
T = T + P • R
V
L • fs
J
A
FET
TH(JA)
IN
Inorm
=
The R
to be used in this equation normally includes
TH(JA)
the R
for the device plus the thermal resistance from
TH(JC)
the case to the ambient temperature (R
). This value
TH(CA)
Output Capacitor Selection
of T can then be compared to the original, assumed value
J
The voltage rating of the output capacitor must be greater
than the maximum output voltage with sufficient derat-
ing. Because the ripple current in output capacitor is a
pulsating square wave in a boost circuit, it is important
that the ripple current rating of the output capacitor
be high enough to deal with this large ripple current.
Figure 6 shows the output ripple current in the 1- and 2-
phase designs. As shown, the output ripple current of a
2-phase boost circuit reaches almost zero when the duty
cycleequals50%ortheoutputvoltageistwiceasmuchas
theinputvoltage.Thusthe2-phasetechniquesignificantly
reduces the output capacitor size.
used in the iterative calculation process.
Input Capacitor Choice
The input capacitor must have high enough voltage and
ripplecurrentratingstohandlethemaximuminputvoltage
and RMS ripple current rating. The input ripple current in
a boost circuit is very small because the input current is
continuous.With2-phaseoperation,theripplecancellation
1.00
0.90
0.80
0.70
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0.60
1-PHASE
0.50
0.40
2-PHASE
0.30
0.20
0.10
0
1-PHASE
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE
2-PHASE
3782A F05
V
IN
L • fs
0.4 0.5
DUTY CYCLE OR (1-V /V
0.1 0.2 0.3
0.6 0.7 0.8 0.9
Inorm
=
)
IN OUT
3782A F06
The RMS Ripple Current is About 29% of
the Peak-to-Peak Ripple Current.
Figure 6. Normalized Output RMS Ripple Currents in Boost
Converter: 1-Phase and 2-Phase. IOUT Is the DC Output Current.
Figure 5. Normalized Input Peak-to-Peak Ripple Current
3782af
13
LT3782A
APPLICATIONS INFORMATION
For a given V and V , we can calculate the duty cycle D
improvement. Although all dissipative elements in the
circuit produce losses, four main sources usually account
for the majority of the losses in LT3782A application
circuits:
IN
OUT
and then derive the output RMS ripple current from Figure
6. After choosing output capacitors with sufficient RMS
ripple current rating, we also need to consider the ESR
requirement if electrolytic caps, tantulum caps, POSCAPs
or SP CAPs are selected. Given the required output ripple
1. The supply current into V . The V current is the sum
IN
IN
of the DC supply current I (given in the Electrical Char-
Q
voltagespecΔV (inRMSvalue)andthecalculatedRMS
OUT
acteristics)andtheMOSFETdriverandcontrolcurrents.
ripple current ΔI , one can estimate the ESR value of
OUT
The DC supply current into the V pin is typically about
IN
the output capacitor to be
7mA and represents a small power loss (much less
than 1%) that increases with V . The driver current
ΔVOUT
ESR≤
IN
resultsfromswitchingthegatecapacitanceofthepower
MOSFET; this current is typically much larger than the
DC current. Each time the MOSFET is switched on and
ΔIOUT
External Regulator to Bias Gate Drivers
then off, a packet of gate charge Q is transferred from
G
GBIAS to ground. The resulting dQ/dt is a current that
ForapplicationswithV higherthan24V,theICtemperature
IN
must be supplied to the GBIAS capacitor through the
may get too high. To reduce heat, an external regulator
V pin by an external supply. In normal operation:
between12Vto14Vshouldbeusedtooverridetheinternal
IN
V
regulatortosupplythecurrentneededforBGATE1
GBIAS
I
≈ I = f • Q
Q G
Q(TOT)
and BGATE2 (see Figure 7).
P = V • (I + f • Q )
IC
IN
Q
G
Efficiency Considerations
2. Power MOSFET switching and conduction losses:
ꢀ
ꢂ
ꢂ
ꢂ
ꢂ
ꢁ
ꢃ2
ꢅ
The efficiency of a switching regulator is equal to the out-
put power divided by the input power (¥100%). Percent
efficiency can be expressed as:
IO(MAX)
2
1–D
ꢅ
P
=
•RDS(ON) •DMAX •ꢆT
FET
MAX ꢅ
ꢅ
% Efficiency = 100% – (L1 + L2 + L3 + …),
ꢄ
where L1, L2, etc. are the individual loss components
as a percentage of the input power. It is often useful to
analyze individual losses to determine what is limiting
the efficiency and which change would produce the most
IO(MAX)
2
2
+ k • VO •
•CRSS • f
1–DMAX
LT3782A
GBIAS
+
12V
GBIAS1
GBIAS2
3782A F07
2μF
Figure 7
3782af
14
LT3782A
APPLICATIONS INFORMATION
3. The I R losses in the sense resistor can be calculated
2
PCB Layout Considerations
almost by inspection.
To achieve best performance from an LT3782A circuit, the
PC board layout must be carefully done. For lower power
applications, a two-layer PC board is sufficient. However,
at higher power levels, a multiplayer PC board is recom-
mended. Using a solid ground plane under the circuit is
the easiest way to ensure that switching noise does not
affect the operation.
ꢀ
ꢂ
ꢂ
ꢃ2
ꢅ
IO(MAX)
2
1–D
ꢅ
PR(SENSE)
=
•R •DMAX
ꢂ
ꢂ
ꢁ
MAX ꢅ
ꢅ
ꢄ
4. The losses in the inductor are simply the DC input cur-
rent squared times the winding resistance. Expressing
this loss as a function of the output current yields:
In order to help dissipate the power from MOSFETs and
diodes, keep the ground plane on the layers closest to the
layers where power components are mounted. Use power
planes for MOSFETs and diodes in order to improve the
spreading of the heat from these components into the
PCB.
ꢀ
ꢂ
ꢂ
ꢂ
ꢂ
ꢁ
ꢃ2
ꢅ
IO(MAX)
2
1–D
ꢅ
PR(WINDING)
=
•RW
MAX ꢅ
ꢅ
ꢄ
Forbestelectricalperformance,theLT3782Acircuitshould
be laid out as follows:
5. Losses in the boost diode. The power dissipation in the
boost diode is:
Place all power components in a tight area. This will
minimize the size of high current loops. Orient the input
andoutputcapacitorsandcurrentsenseresistorsinaway
that minimizes the distance between the pads connected
to ground plane.
IO(MAX)
PDIODE
=
• VD
2
The boost diode can be a major source of power loss
in a boost converter. For 13.2V input, 42V output at 3A,
a Schottky diode with a 0.4V forward voltage would
dissipate 600mW, which represents about 1% of the
input power. Diode losses can become significant at
low output voltages where the forward voltage is a
significant percentage of the output voltage.
Place the LT3782A and associated components tightly to-
gether and next to the section with power components.
Use a local via to ground plane for all pads that connect to
ground. Use multiple vias for power components.
Connect the current sense inputs of LT3782A directly
to the current sense resistor pads. Connect the current
sense traces on the opposite sides of pads from the traces
carrying the MOSFETs source currents to ground. This
technique is referred to as Kelvin sensing.
6. Other losses, including C and C ESR dissipation and
IN
O
inductor core losses, generally account for less than
2% of the total losses.
3782af
15
LT3782A
TYPICAL APPLICATIONS
10V to 24V Input to 24V, 8A Output Boost Converter
10V TO 24V INPUT
1
28
SGATE2
GBIAS
2R2
2
27
SGATE1
V
CC
L1
3
26
25
24
23
D1
PB2020-103
NC
NC
NC
UPS840
1μF
4
Q1
GND
PH3330
LT3782A
5
6
C
OUT2
SYNC
V
EE1
330μF, 35V, ×2
CS1
DELAY
BGATE1
GBIAS1
GBIAS2
0.004Ω
7
8
22
21
DCL
OUTPUT
24V
8A
10Ω
+
–
CS1
SENSE1
C
C
OUT1
22μF, 25V, ×4
IN
2.2μF
10nF
22μF
25V
9
20
19
SENSE1
SLOPE
BGATE2
0.004Ω
CS2
59k
82k
10
V
EE2
NC
825k
274k
11
12
18
17
R
SET
Q2
PH3330
–
+
SENSE2
RUN
FB
10nF
10Ω
24.9k
221k
13
14
16
15
L2
PB2020-103
CS2
SENSE2
SS
D2
UPS840
V
C
3782A TA02
4.7nF
L1, L2: PULSE PB2020-103
ALL CERAMIC CAPACITORS ARE X7R, TDK
C
C1
R
C1
C
C2
6.8nF
13.3k
*OUTPUT CURRENT WITH BOTH INPUTS PRESENT
100pF
Efficiency
100
98
96
94
92
90
88
86
15V
IN
12V
IN
0
1
2
3
4
5
6
7
8
I
(A)
OUT
3782A TA02b
3782af
16
LT3782A
TYPICAL APPLICATIONS
3782af
17
LT3782A
PACKAGE DESCRIPTION
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 2726 25 24 23 22 21 20 19 18 1716 15
6.60 ±0.10
2.74
(.108)
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
4.50 ±0.10
SEE NOTE 4
6.40
(.252)
BSC
2.74
(.108)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
5
7
1
2
3
4
6
8
9 10 12 13 14
11
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP 0204
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN
FOR EXPOSED PAD ATTACHMENT
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3. DRAWING NOT TO SCALE
3782af
18
LT3782A
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.50 REF
2.65 ± 0.05
3.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 ± 0.05
4.00 ± 0.10
(2 SIDES)
27
28
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ± 0.10
(2 SIDES)
3.50 REF
3.65 ± 0.10
2.65 ± 0.10
(UFD28) QFN 0506 REV B
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3782af
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT3782A
TYPICAL APPLICATION
28V Output Base Station Power Converter with Redundant Input
V
INA
0V TO 28V*
1
2
3
4
5
6
28
27
26
25
24
23
SGATE2
SGATE1
NC
GBIAS
2R2
L1
10μH
V
CC
D1
UPS840
BAS516
NC
NC
Q1
PH4840S
1μF
GND
C
INA
22μF
LT3782A
C
OUT2
330μF, 35V, ×2
CS1
0.004Ω
SYNC
DELAY
V
EE1
BGATE1
GBIAS1
GBIAS2
7
8
22
21
DCL
OUTPUT
28V
4A (8A**)
10Ω
+
–
CS1
SENSE1
C
OUT1
2.2μF
10nF
10μF, 50V, ×4
9
20
19
SENSE1
SLOPE
BGATE2
0.004Ω
CS2
59k
82k
10
V
EE2
NC
C
INB
22μF
825k
274k
11
12
18
17
R
SET
Q2
PH4840S
–
+
SENSE2
RUN
FB
10nF
10Ω
24.9k
261k
13
14
16
15
L2
10μH
BAS516
CS2
SENSE2
SS
D2
UPS840
V
C
3782A TA03
NOTE:
4.7nF
V
INB
0V TO 28V*
C
C1
4.7nF
*INPUT VOLTAGE RANGE FOR VINA AND VINB IS 0V TO 28V.
AT LEAST ONE OF THE INPUTS MUST BE 12V OR HIGHER.
R
C1
C
C2
100pF
15k
L1, L2: PULSE PB2020-103
ALL CERAMIC CAPACITORS ARE X7R, TDK
**OUTPUT CURRENT WITH BOTH INPUTS 12V OR HIGHER
RELATED PARTS
PART NUMBER
LT®1619
DESCRIPTION
COMMENTS
300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology
SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design; V Up to 36V
Current Mode PWM Controller
Current Mode DC/DC Controller
Overvoltage Protection Controller
LTC1624
IN
LTC1696
0.8V ≤ V ≤ 24V, 2% Overvoltage Threshold Accuracy, ThinSOT™ Package
IN
LTC1700
No R
™ Synchronous Step-Up Controller
SENSE
Up to 95% Efficiency, Operation as Low as 0.9V Input
LTC1871/LTC1871-7 Wide Input Range Controller
No R
, 7V Gate Drive, Current Mode Control
SENSE
LT1930
LT1952
LTC3425
1.2MHz, SOT-23 Boost Converter
Up to 34V Output, 2.6V ≤ V ≤ 16V, Miniature Design
IN
Single Switch Synchronous Forward Controller High Efficiency, 25W to 500W, Wide Input Range, Adaptive Duty Cycle Clamp
5A, 8MHz 4-Phase Monolithic Step-Up DC/DC
Converter
0.5V ≤ V ≤ 4.5V, 2.4V ≤ V
≤ 5.25V, Very Low Output Ripple
OUT
IN
LTC3703/LTC3703-5 100V and 60V, Step-Down and Step-Up DC/DC
Synchronous Controller
High Efficiency Synchronous Operation, High Voltage Operation,
No Transformer Required
LTC3729L-6
20A to 200A, 250kHz to 550kHz PolyPhase®
Synchronous Controller
Expandable from 2-Phase to 12-Phase, Uses All Surface Mount Components,
IN
V
Up to 30V
LTC3731
LT3782
3-Phase to 12-Phase Synchronous Controller
2-Phase Step-Up DC/DC Controller
SOT-23 Flyback Controller
60A to 240A Output Current, 0.6V ≤ V
≤ 6V, 4.5V ≤ V ≤ 32V
OUT IN
Pin Compatible with LT3782A
LTC3803
LTC3806
Adjustable Slope Compensation, Internal Soft-Start
Synchronous Flyback Controller
High Efficiency, Improves Cross Regulation in Multiple Output Designs,
Current Mode, 3mm × 4mm 12-Pin DFN Package
LTC3850
Dual, 250kHz to 750kHz, 2-Phase Synchronous V : 4V to 30V, 99% Duty Cycle, 4mm × 4mm QFN, 4mm × 5mm QFN and
IN
Step-Down Controller
SSOP-28 Packages
LTC3862/LTC3862-1 Multiphase High Power Current Mode Step-Up
Controller
4V ≤ V ≤ 36V Expandable from 2-Phase to 12-Phase
IN
PolyPhase is a registered trademark of Linear Technology Corporation. ThinSOT and No R
are trademarks of Linear Technology Corporation.
SENSE
3782af
LT 1208 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LT3782AEFE#PBF
LT3782A - 2-Phase Step-Up DC/DC Controller; Package: TSSOP; Pins: 28; Temperature Range: -40°C to 85°C
Linear
LT3782AEUFD#TR
IC 0.07 A SWITCHING CONTROLLER, 533 kHz SWITCHING FREQ-MAX, PQCC28, 4 X 5 MM, PLASTIC, MO-220WXXX-X, QFN-28, Switching Regulator or Controller
Linear
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