LT3745-1 [Linear]
16-Channel 50mA LED; 16通道LED 50毫安
| 型号： | LT3745-1 |
| 厂家： | 
Linear |
| 描述： | 16-Channel 50mA LED |
| 文件： | 总28页 (文件大小：376K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3745-1
16-Channel 50mA LED
Driver with Buck Controller
FEATURES
DESCRIPTION
The LT®3745-1 integrates a 16-channel LED driver with a
55Vbuckcontroller.TheLEDdriverlightsupto75mA/36V
of LEDs in series per channel, and the buck controller gen-
erates an adaptive bus voltage supplying the parallel LED
strings. Each channel has individual 6-bit dot correction
current adjustment and 12-bit grayscale PWM dimming.
Bothdotcorrectionandgrayscaleareaccessibleviaaserial
data interface in LVDS logic. A 4ꢀ LED current match-
ing and a 0.5µs minimum LED on-time can be achieved
at 50mA per channel.
n
6V to 55V Power Input Voltage Range
n
16 Independent LED Outputs Up to 75mA/36V
n
±±4 LED Current Matching at 50mA (Typ ±14%
6-Bit Dot Correction Current Adjustment
n
n
12-Bit Grayscale PWM Dimming
0.5µs Minimum LED On-Time
n
n
Adaptive LED Bus Voltage for High Efficiency
n
Cascadable 30MHz LVDS Serial Data Interface
n
Full Diagnostic and Protection: Individual Open/Short
LED and Overtemperature Fault
40-Lead 6mm × 6mm QFN Package
n
The LT3745-1 performs full diagnostic and protection
against open/short LED and overtemperature fault. The
fault status is sent back through the serial data interface.
The 30MHz fully-buffered, cascadable LVDS serial data
interfacemakesthechipextremelysuitableforlargescreen
LCD dynamic backlighting and mono-, multi-, full-color
LED displays. The LT3745 uses a TTL/CMOS serial data
interface instead of LVDS.
APPLICATIONS
n
Large Screen Display LED Backlighting
n
Mono-, Multi-, Full-Color LED Displays
n
LED Billboards and Signboards
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
True Color PWM is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 8058810
TYPICAL APPLICATION
16-Channel LED Driver, 1MHz Buck, 10 LEDs, 25mA to 75mA per Channel, 500Hz 12-Bit Dimming
V
IN
42V TO 55V
4.7µF
0.47µF
V
CAP
GATE
IN
EN
EN/UVLO
47µH
25mΩ
100k
10µF
V
CC
47µF
×2
V
CC
267k
3V TO 3.6V
GND
SYNC
10k
.
.
.
.
.
.
.
.
.
.
.
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.
.
.
ISP
ISN
FB
RT
SS
LT3745-1
46.4k
60.4k
10nF
LED00
LED01
I
SET
T
SET
LED02
.
.
.
32.4k
LED13
LED14
LED15
+
–
2.048MHz
LVDS CLOCK
PWMCK
PWMCK
+
+
SCKO
SCKI
–
–
SCKO
SCKI
LVDS
LVDS
+
+
SDO
SDI
–
–
SDO
SDI
LDI
37451 TA01
37451f
1
LT3745-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1%
TOP VIEW
V
.......................................................................... 57V
IN
CAP......................................................... V – 8V to V
IN
IN
40 39 38 37 36 35 34 33 32 31
GATE..............................................................CAP to V
IN
EN/UVLO
LED07
LED06
LED05
LED04
LED03
LED02
LED01
1
2
3
4
5
6
7
8
9
30
29
28
SYNC
LED08
LED09
LED00 to LED15, ISP, ISN .........................................40V
ISP.................................................ISN – 1V to ISN + 1V
FB, RT, T , I ....................................................... 2V
27 LED10
26 LED11
SET SET
41
GND
V ...............................................................–0.3V to 4V
CC
+
–
+
–
+
–
25
LED12
24 LED13
23
SCKI , SCKI , SCKO , SCKO , SDI , SDI ,
+
–
+
–
SDO , SDO , LDI, PWMCK , PWMCK , SYNC,
SS, EN/UVLO ............................................. –0.3V to V
Operating Junction Temperature Range
(Notes 2, 3)
LED14
CC
LED00
–
22 LED15
–
SCKI 10
21
SCKO
11 12 13 14 15 16 17 18 19 20
LT3745E-1.........................................–40°C to 125°C
LT3745I-1..........................................–40°C to 125°C
Storage Temperature Range ..................–65°C to 125°C
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
T
= 125°C, θ = 34°C/W, θ = 2.5°C/W
JA JC
JMAX
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3745EUJ-1#PBF
LT3745IUJ-1#PBF
TAPE AND REEL
PART MARKING*
LT3745UJ-1
PACKAGE DESCRIPTION
40-Lead (6mm × 6mm) Plastic QFN
40-Lead (6mm × 6mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
LT3745EUJ-1#TRPBF
LT3745IUJ-1#TRPBF
LT3745UJ-1
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3.3V, VEN/UVLO = 1.5V, VFB = 1.5V, VISP = VISN = 0V,
RT = 105k, RISET = 60.±k, CCAP = 0.±7µF to VIN, unless otherwise noted.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
V
V
Operating Voltage
Supply Current
6
55
V
IN
IN
I
V
= 0V
0.2
0.4
2
0.55
µA
mA
VIN
IN
EN/UVLO
No Switching
V
V
V
Operating Voltage
3
3.6
V
CC
CC
CC
I
Supply Current (Note 4)
V
= 0V
EN/UVLO
0.25
11
16
19
mA
mA
mA
mA
VCC
LED Channel Off, 30MHz Data Off
LED Channel On, 30MHz Data Off
LED Channel On, 30MHz Data On
37451f
2
LT3745-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3.3V, VEN/UVLO = 1.5V, VFB = 1.5V, VISP = VISN = 0V,
RT = 105k, RISET = 60.±k, CCAP = 0.±7µF to VIN, unless otherwise noted.
SYMBOL
Undervoltage Lockout (UVLO%
UVLO Threshold
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
Rising
Falling
2.76
2.58
2.86
2.68
2.96
2.78
V
V
CC
CC
CC
EN/UVLO Shutdown Threshold
UVLO Threshold
I
<1mA
0.35
1.26
1.18
V
V
V
VCC
V
V
Rising
1.30
1.22
1.34
1.26
EN/UVLO
EN/UVLO
Falling
I
EN/UVLO Bias Current
V
= V = 3.3V
0.1
1
µA
EN/UVLO
EN/UVLO
CC
(V – V ) UVLO Threshold
(V – V ) Rising
4.6
4.2
4.9
4.5
5.2
4.8
V
V
IN
CAP
IN
CAP
(V – V ) Falling
IN
CAP
Soft-Start (SS%
I
Soft-Start Charge Current
Soft-Start Discharge Current
Soft-Start Reset Threshold
V
V
= 1V
–16
–12
330
0.35
–8
µA
µA
V
SS
SS
= V , V
= 1V
SS
CC EN/UVLO
V
SS(TH)
Oscillator
V
RT Pin Voltage
1.186
1.205
–80
1.224
V
RT
I
f
RT Pin Current Limit
Oscillator Frequency
V
= 0V
µA
RT
RT
R = 280k
184
460
935
204
510
1035
224
560
1135
kHz
kHz
kHz
OSC
T
T
T
R = 105k
R = 46.4k
f
Sync Frequency Range (Note 5)
R = 348k
T
200
1000
kHz
SYNC
SYNC LOGIC
V
= 3V to 3.6V
= 5V
CC
High Level Voltage
Low Level Voltage
2.4
0
V
V
V
CC
0.6
1.234
0.8
Error Amplifiers and Loop Dynamics
l
V
FB Regulation Voltage
FB Input Bias Current
LED Regulation Voltage
Minimum GATE Off-Time
Minimum GATE On-Time
V
V
V
V
1.186
0.6
1.210
–120
0.7
V
nA
V
FB
ISN
ISN
ISN
ISP
I
FB
= 5V, V Regulated
FB
= 5V, V = 1V
FB
t
t
= V = 5V, V = 1V
120
ns
ns
OFF(MIN)
ISN
FB
(V – V ) = 60mV, V = 5V, V = 1V
200
ON(MIN)
ISP
ISN
ISN
FB
Current Sense Amplifier
ISP/ISN Pin Common Mode
to ISN Dropout Voltage (V – V
l
l
V
V
V
= V
0
36
2.1
58
V
V
ISP
ISN
V
)
ISN
= V , V = 1V
1.7
44
IN
IN
ISP
ISN FB
Current Limit Sense Threshold (V – V
)
ISN
= 1V
FB
30
mV
µA
µA
ISP
I
I
ISP Input Bias Current
ISN Input Bias Current
–24
–48
ISP
ISN
Gate Driver
V
CAP Bias Voltage (V – V
)
7V < V < 55V
6.4
6.8
22
7.1
V
mA
V
BIAS
CAP
IN
CAP
IN
I
CAP Bias Current Limit
(V – V ) = V
– 0.5V
IN
CAP
BIAS
GATE High Level (V – V
)
I
I
= –100mA
0.4
0.3
30
IN
GATE
GATE
GATE
GATE Low Level (V
GATE Rise Time
GATE Fall Time
– V
)
CAP
= 100mA
V
GATE
C
= 3.3nF to V
ns
ns
GATE
GATE
IN
IN
C
= 3.3nF to V
30
37451f
3
LT3745-1
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3.3V, VEN/UVLO = 1.5V, VFB = 1.5V, VISP = VISN = 0V,
RT = 105k, RISET = 60.±k, CCAP = 0.±7µF to VIN, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LED Driver
l
l
V
Trimmed I Pin Voltage
1.181
1.205
1.229
36
V
V
ISET
SET
LEDxx Operating Voltage
LEDxx Leakage Current
V = 48V, V = V = V
IN ISP ISN LEDxx
LED Channel Off, V = 48V,
0.2
µA
IN
LEDxx
V
ISP
= V = 36V, V
= 24V
ISN
I
LED Constant Sink Current
V
ISP
= V = 5V, V
= 1V
LED
ISN
LEDxx
l
l
l
REG = 0x00
23.3
47.5
70
25.3
50.5
74
27.3
53.5
78
mA
mA
mA
DC
REG = 0x20
DC
REG = 0x3F
DC
l
Current Mismatch Between Channels
Current Mismatch Between Devices
LED Current Line Regulation
V
= V = 5V, V
DC
= 1V,
= 1V,
= 1V,
1
4
ꢀ
∆I
∆I
∆I
∆I
ISP
ISN
LEDxx
LEDC
LEDD
LINE
REG = 0x20 (Note 6)
l
V
ISP
= V = 5V, V
ISN LEDxx
DC
1
3
ꢀ
REG = 0x20 (Note 7)
V
ISP
= V = 5V, V
LEDxx
0.1
0.1
0.2
0.2
ꢀ/V
ꢀ/V
ISN
REG = 0x20, V = 3V to 3.6V (Note 8)
DC
CC
LED Current Load Regulation
V
LEDxx
= V = 5V, REG = 0x20,
ISP ISN DC
LOAD
V
= 1V to 3V (Note 9)
V
V
Open LED Threshold
Short LED Threshold
Minimum LED On-Time
V
ISP
V
ISP
V
ISP
= V = 5V, V
Falling
Rising
0.35
3.9
V
V
OPEN
ISN
LEDxx
= V = 5V, V
3.7
4.1
SHT
ISN
LEDxx
t
= V = 5V, REG = 0x001
0.5
µs
LEDON
ISN
GS
Thermal Protection
l
I
T
T
Output Current
V
= 1V
19.0
19.8
510
20.6
µA
TSET
SET
SET
TSET
Over Temperature Threshold
T = 25°C
A
mV
Serial Data Interface
Single-Ended Input (Note 10)
High Level Voltage
Low Level Voltage
V
CC
= 3V to 3.6V
V
V
2.4
0
V
V
V
SIH
SIL
CC
0.6
I
Single-Ended Input Current
V
V
= 3V to 3.6V, SI = V or GND
–0.2
0.2
µA
SI
CC
CC
Differential Input (Note 11)
Common Mode
High Threshold
Low Threshold
= 3V to 3.6V
CC
V
V
V
V
V
V
= 200mV
CM
CM
0.1
2.3
100
V
mV
mV
CM
DTH
DTL
ID
= 1.2V
= 1.2V
50
–100
–0.2
230
–50
+
–
I
DI
Differential Input Current
V
CC
= 3.6V; DI , DI = 2.4V or 0V
0.2
430
10
µA
mV
mV
V
Differential Output Voltage (Note 11)
R = 100Ω
330
1
OD
L
V
Magnitude Change Between
R = 100Ω
∆V
OD
L
OD
Complementary Outputs
V
Differential Output Offset Voltage
R = 100Ω
1.1
1.2
1
1.3
10
V
OS
L
V
Magnitude Change Between
R = 100Ω
L
mV
∆V
OS
OS
Complementary Outputs
+
–
I
Differential Output Short-Circuit Current
DO = 0V or DO = 0V
–6
–8
mA
OSD
37451f
4
LT3745-1
The l denotes the specifications which apply over the full operating temperature
TIMING CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3V to 3.6V, VEN/UVLO = 1.5V, VFB = 1.5V, VISP = VISN = 5V,
VLEDxx = 1V, RT = 105k, RISET = 60.±k, CCAP = 0.±7µF to VIN, CSCKO /SCKO
+
– = CSDO /SDO
+
– = 15pF, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
30
UNITS
MHz
l
l
f
f
Data Shift Clock Frequency
PWMCK Clock Frequency
SCKI Pulse Duration
SCKI
25
MHz
PWMCK
l
l
t
t
SCKI = H (Figure 3)
SCKI = L (Figure 3)
16
16
ns
ns
WH-CKI
WL-CKI
l
l
t
t
PWMCK Pulse Duration
PWMCK = H (Figure 4)
PWMCK = L (Figure 4)
20
20
ns
ns
WH-PWM
WL-PWM
l
l
l
l
l
l
l
t
t
t
t
t
t
t
LDI Pulse Duration
LDI = H (Figure 3)
20
5
ns
ns
ns
ns
ns
ns
ns
ns
WH-LDI
SU-SDI
HD-SDI
SU-LDI
SDI-SCKI Setup Time
SDI – SCKI↑ (Figure 3)
SCKI↑ – SDI (Figure 3)
SCKI↓ – LDI↑ (Figure 3)
LDI↓ – SCKI↑ (Figure 3)
SCKI↑ – SCKO↑ (Figure 3)
SCKI↓ – SCKO↓ (Figure 3)
SCKI-SDI Hold Time
5
SCKI-LDI Setup Time
5
LDI-SCKI Hold Time
15
HD-LDI
PD-SCK↑
PD-SCK↓
SCKI-SCKO Propagation Delay (Rising)
SCKI-SCKO Propagation Delay (Falling)
SCK Duty Cycle Change
33
33
0
50
50
∆t
∆t
PD-SCK
= t
– t
PD-SCK
PD-SCK↑ PD-SCK↓
l
t
SCKO-SDO Propagation Delay
PWMCK-LED Propagation Delay
SCKO/SDO Rise Time
2
5
8
ns
ns
ns
ns
SCKO↑ – SDO (Figure 3)
PWMCK↑ – I (Figure 4)
PD-SD
t
t
t
55
2.6
2.6
PD-PWM
LED
C
LOAD
LOAD
= 15pF, 10ꢀ to 90ꢀ
= 15pF, 90ꢀ to 10ꢀ
R-SO
SCKO/SDO Fall Time
C
F-SO
Table 1. Test Parameter Equations
IOUTmax(0−15) –I
∆ILEDC(ꢀ) =
OUTmin(0−15) •100
V
= V(DI+ )– V(DI– )
(1)
(6)
(7)
(8)
(9)
2•IOUTavg(0−15)
ID
IOUTavg(0−15) –IOUTcal
∆ILEDD(ꢀ) =
• 100
(2)
(3)
V(DI+ )+ V(DI– )
IOUTcal
VCM
=
2
1.205V
RISET
IOUTcal = 2500 •
VOD = V(DO+ )– V(DO– )
I
V
= 3.6V – I
V
= 3V
OUTn
CC
OUTn
CC
100
∆I
(ꢀ / V) =
•
(4)
(5)
LINE
0.6V
I
V
= 3V
CC
OUTn
V(DO+ )+ V(DO– )
VOS
=
2
IOUTn VOUTn = 3V – IOUTn VOUTn = 1V
IOUTn VOUTn = 1V
100
2V
∆ILOAD(ꢀ / V) =
•
37451f
5
LT3745-1
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: The SYNC frequency must be higher than the RT programmed
oscillator frequency, and is suggested to be around 20ꢀ higher. Any SYNC
frequency higher than the suggested value may introduce sub-harmonic
oscillation in the converter due to insufficient slope compensation. See
Application Information section.
Note 6: The current mismatch between channels is calculated as
Equation 1 in Table 1.
Note 7: The current mismatch between devices is calculated as
Equations 2 and 3 in Table 1.
Note 8: The LED current line regulation is calculated as Equation 4 in
Note 2: The LT3745E-1 is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3745I-1 is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: This IC includes thermal shutdown protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when thermal shutdown protection is
active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Table 1.
Note 9: The LED current load regulation is calculated as Equation 5 in
Table 1.
Note 10: The specifications of single-ended input SI apply to the LDI pin.
+
–
+
Note 11: The specifications of differential inputs DI /DI apply to SCKI /
Note ±: The V supply current with LED channel on highly depends on
CC
–
+
–
+
–
SCKI , SDI /SDI and PWMCK /PWMCK ; the specifications of differential
the LED current setting and LEDxx pin voltage; its test condition is
+
–
+
–
+
–
outputs DO /DO apply to SCKO /SCKO and SDO /SDO . The parameters
V , V , V and V are defined in Equations 6 to 9 and measured in the
R
= 60.4k, REG = 0x3F, REG = 0xFFF, V = V = 5V,
ISET
DC GS ISP ISN
ID CM OD
OS
V
LEDxx
= 1V. The V supply current with serial data interface on highly
CC
Parameter Test Setup.
+
–
depends on V supply voltage, SCKI /SCKI clock frequency,
SCKO /SCKO , SDO /SDO loading capacitance, and PWMCK /PWMCK
clock frequency; its test condition is V = 3.3V, f – = 30MHz,
CC
+
–
+
–
+
–
+
SCKI /SCKI
CC
C
+
– = C
+
– = 15pF, f
+
– = 409.6KHz.
SCKO /SCKO
SDO /SDO
PWMCK /PWMCK
Parameter Test Setup
C
L
+
–
DO
R
D
L
DO
C
L
37451 PT
37451f
6
LT3745-1
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
100Hz 8:1 GS Dimming
100Hz ±096:1 GS Dimming
500Hz ±096:1 GS Dimming
I
I
LED15
50mA/DIV
LED15
I
LED15
50mA/DIV
50mA/DIV
V
V
V
OUT
OUT
OUT
2V/DIV
2V/DIV
2V/DIV
V
V
LED15
V
LED15
LED15
2V/DIV
2V/DIV
2V/DIV
V
V
V
PWMCK
PWMCK
PWMCK
0.5V/DIV
0.5V/DIV
0.5V/DIV
37451 G03
37451 G01
37451 G02
500ns/DIV
500ns/DIV
5ms/DIV
CIRCUIT OF FIGURE 7:
CIRCUIT OF FIGURE 7:
CIRCUIT OF FIGURE 7:
DC = 0×20
DC = 0×20
DC = 0×20
15
15
15
GS = 0×001
15
GS = 0×001
15
GS = 0×200
15
200Hz 2-Level DC Dimming
200Hz ±-Level DC Dimming
Adaptive LED Bus Voltage I
V
OUT
I
I
LED15
LED15
0.5V/DIV
50mA/DIV
50mA/DIV
V
OUT
V
OUT
2V/DIV
I
2V/DIV
L
0.5A/DIV
V
LED15
2V/DIV
V
LED15
2V/DIV
V
V
SCKI
SCKI
0.5V/DIV
0.5V/DIV
(a) (b) (c)
(a) (b) (c)
(a)
(b)
0.5ms/DIV
CIRCUIT OF FIGURE 7:
(c)
(d)
37451 G05
37451 G04
37451 G06
1ms/DIV
CIRCUIT OF FIGURE 7:
2ms/DIV
CIRCUIT OF FIGURE 7:
(a) EN = 0, GS = 0×FFF (c) EN = 1, DC = 0×00
(b) EN = 1, DC = 0×3F (d) EN = 1, DC = 0×20
(a) EN = 1, GS = 0×FFF (c) EN = 1, DC = 0×00
DC
= 0×3F, GS
= 0×FFF
15
15
15
15
15
15
00-15
00-15
(b) EN = 1, DC = 0×3F
15
Adaptive LED Bus Voltage II
Adaptive LED Bus Voltage III
Adaptive LED Bus Voltage IV
V
V
OUT
OUT
V
OUT
0.5V/DIV
0.5V/DIV
0.5V/DIV
I
L
0.5A/DIV
I
L
I
L
0.5A/DIV
0.5A/DIV
37451 G08
37451 G09
37451 G07
2ms/DIV
2ms/DIV
2ms/DIV
CIRCUIT OF FIGURE 7:
CIRCUIT OF FIGURE 7:
CIRCUIT OF FIGURE 7:
DC
00-03
GS
04-07
DC
12-15
= 0×3F, GS
= 0×3FF, DC
= 0×1F, GS
= 0×2F,
= 0×BFF,
DC
= 0×20, GS
= 0×800
DC
00-15
GS
04-05
GS
10-11
= 0×3F, GS
= 0×1FF, GS
= 0×7FF, GS
= 0×DFF, GS
= 0×3FF,
= 0×9FF,
08-09
14-15
00-03
08-11
12-15
04-07
08-11
00-15
00-15
00-01
06-07
12-13
02-03
= 0×7FF, DC
= 0×0F, GS
= 0×5FF, GS
= 0×BFF, GS
= 0×FFF
= 0×FFF
37451f
7
LT3745-1
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Buck Efficiency
Shutdown IVIN vs VIN
Quiescent IVIN vs VIN
100
95
90
85
80
75
70
5
4
3
2
1
0
0.43
24V , 12V
at 1MHz
OUT
IN
0.42
T = 125°C
T = 125°C
0.41
12V , 4V
at 500kHz
OUT
IN
T = 25°C
0.40
48V , 4V
at 200kHz
OUT
IN
T = –40°C
0.39
T = 25°C
30
65
60
T = –40°C
0.38
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0
10
20
40
50
60
0
10
20
30
(V)
40
50
60
LOAD CURRENT (A)
V
IN
(V)
V
IN
37451 G10
37451 G11
37451 G12
IVCC vs VCC – Channel Off,
Data Off
VCC UVLO Threshold
vs Temperature
IVCC vs VCC – Shutdown Mode
500
400
300
200
12.0
11.5
11.0
10.5
2.90
2.85
2.80
2.75
2.70
2.65
2.60
+
UVLO
T = 125°C
T = 125°C
T = 25°C
T = 25°C
T = –40°C
–
T = –40°C
UVLO
100
0
10.0
3.0
3.2
3.3
(V)
3.4
3.5
3.6
3.1
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
–50 –25
0
25
50
75 100 125
V
V
JUNCTION TEMPERATURE (°C)
CC
CC
37451 G15
37451 G13
37451 G14
EN/UVLO UVLO Threshold
vs Temperature
(VIN-VCAP% UVLO Threshold
vs Temperature
Oscillator Frequency fOSC vs RT
1.32
1.30
1.28
1.26
1.24
1.22
1.20
4.90
4.80
1000
800
+
+
UVLO
UVLO
4.70
4.60
4.50
4.40
600
400
200
0
–
UVLO
–
UVLO
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
20
60 100 140 180 220 260 300
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
R
(kΩ)
T
37451 G17
37451 G16
37451 G18
37451f
8
LT3745-1
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Oscillator Frequency fOSC
vs Temperature
LED Regulation Voltage
vs Load Current
FB Regulation Voltage
vs Load Current
520
510
500
490
480
1.216
1.214
1.212
1.210
1.208
1.206
1.204
0.72
0.70
0.68
0.66
0.64
0.62
0.60
–50 –25
0
25
50
75 100 125
0
400
600
800
1000 1200
200
0
400
600
800
1000 1200
200
JUNCTION TEMPERATURE (°C)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
37451 G20
37451 G21
37451 G19
Soft-Start Charge Current ISS
vs Temperature
CAP Bias Voltage (VIN-VCAP
vs VIN
%
Current Sense Threshold vs VISN
60
55
50
45
40
35
6.90
6.86
6.82
6.78
6.74
6.70
–10.0
–10.2
–10.4
T = 125°C
T = 25°C
T = 25°C
T = –40°C
–10.6
–10.8
–11.0
T = 125°C
T = –40°C
0
20
(V)
30
40
0
10
20
30
(V)
40
50
60
–50 –25
0
25
50
75 100 125
10
V
V
JUNCTION TEMPERATURE (°C)
ISN
IN
37451 G23
37451 G22
37451 G24
CAP Bias Voltage (VIN-VCAP
vs ICAP
%
VISET Pin Voltage vs Temperature
6.90
6.80
6.70
6.60
6.50
1.210
1.208
1.206
1.204
T = 25°C
T = –40°C
T = 125°C
6.40
6.30
6.20
1.202
1.200
0
4
8
12
(mA)
16
20
24
–50 –25
0
25
50
75
100 125
I
JUNCTION TEMPERATURE (°C)
CAP
37451 G25
37451 G26
37451f
9
LT3745-1
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
LED Current ILED
vs LED Voltage VLED
LED Current vs Dot Correction
Nominal LED Current vs RISET
80
70
60
50
40
30
20
10
0
50
40
30
20
80
70
60
50
40
30
20
10
0
DC = 0×3F
DC = 0×20
DC = 0×00
10
0
40
80
120 160 200 240 280 320
(kΩ)
1
8
24 32 40 48 56 64
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
R
DOT CORRECTION +1
V
ISET
LED
37451 G28
37451 G27
37451 G29
LED Current Variation ILED
vs Temperature
Short LED Threshold vs VISN
TSET Current vs ISET Current
51.0
50.5
50.0
49.5
49.0
20
16
12
8
30
24
18
12
6
4
0
0
–50 –25
0
25
50
75 100 125
0
4
8
12
(µA)
16
20
0
8
16
24
(V)
32
40
JUNCTION TEMPERATURE (°C)
I
V
ISET
ISN
37451 G32
37451 G31
37451 G30
LED Current Derating
vs Temperature
TSET Threshold vs Temperature
60
50
40
30
20
10
0
700
650
600
550
500
450
400
350
OT = 0
OT = 1
80 85 90 95 100 105 110 115 120
–50 –25
0
25
50
75
100 125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
37451 G34
37451 G33
37451f
10
LT3745-1
PIN FUNCTIONS
EN/UVLO (Pin 1%: Enable and Undervoltage Lockout
(UVLO) Pin. The pin can accept a digital input signal to
enable or disable the chip. Tie to 0.35V or lower to shut
down the chip or tie to 1.34V or higher for normal op-
SS (Pin 32%: Soft-Start Pin. Placing a capacitor here pro-
grams soft-start timing to limit inductor inrush current
during start-up. The soft-start cycle will not begin until
all the V , EN/UVLO, and (V -V ) voltages are higher
CC
IN CAP
than their respective UVLO thresholds.
eration. This pin can also be connected to V through a
IN
resistordividertoprogramapowerinputUVLOthreshold.
FB (Pin 33%: Feedback Pin. The pin is regulated to the
internal bang-gap reference 1.210V during start-up and
prechargingphases. Connecttoaresistordividerfromthe
buck converter output to program the maximum LED bus
voltage. See more details in the Applications Information
section.
If both the enable and UVLO functions are not used, tie
this pin to V pin.
CC
LED00 to LED15 (Pins 2 to 9, 22 to 29%: LED Driver Output
Pins. Connect the cathodes of LED strings to these pins.
−
+
SCKI , SCKI (Pins 10, 11%: Serial Interface LVDS Logic
ISN (Pin 3±%: Negative Inductor Current Sense Pin. The
pin is connected to one terminal of the external inductor
current sensing resistor and the buck converter output
supplying parallel LED channels.
Clock Input Pins.
−
+
SDI , SDI (Pins 12, 13%: Serial Interface LVDS Logic
Data Input Pins.
LDI(Pin1±%:SerialInterfaceTTL/CMOSLogicLatchInput
Pin. An asynchronous input signal at this pin latches the
serial data in the shift registers into the proper registers
and the status information is ready to shift out with the
coming clock pulses. See more details in the Operation
section.
ISP (Pin 35%: Positive Inductor Current Sense Pin. The pin
is connected to the inductor and the other terminal of the
external inductor current sensing resistor.
CAP (Pin 36%: V Referenced Regulator Supply Capacitor
IN
Pin. The pin holds the negative terminal of an internal V
IN
referenced6.8Vlinearregulatorusedtobiasthegatedriver
circuitry. Must be locally bypassed with a capacitor to V .
V
(Pin15%:LogicandControlSupplyPin.Thepinpowers
IN
CC
serial data interface and internal control circuitry. Must be
GATE (Pin 37%: Gate Driver Pin. The pin drives an external
P-channel power MOSFET with a typical peak current of
1A. Connect this pin to the gate of the power MOSFET with
a short and wide PCB trace to minimize trace inductance.
locally bypassed with a capacitor to ground.
+
−
PWMCK , PWMCK (Pins 16, 17%: Grayscale PWM
Dimming LVDS Logic Clock Input Pins. Individual PWM
dimming signal is generated by counting this clock pulse
from zero to the bits in its 12-bit grayscale PWM register.
V
IN
(Pin 38%: Power Input Supply Pin. Must be locally
bypassed with a capacitor to ground.
T (Pin 39%: Temperature Threshold Setting Pin. A
SET
+
−
SDO , SDO (Pins 18, 19%: Serial Interface LVDS Logic
resistor to ground programs overtemperature threshold.
See more details in the Applications Information section.
Data Output Pins.
+
−
SCKO , SCKO (Pins 20, 21%: Serial Interface LVDS Logic
I
(Pin ±0%: Nominal LED Current Setting Pin. A resistor
Clock Output Pins.
SET
to ground programs the nominal LED current for all the
channels. See more details in the Applications Informa-
tion section.
SYNC(Pin30%:SwitchingFrequencySynchronizationPin.
Synchronizes the internal oscillator frequency to an exter-
nal clock applied to the SYNC pin. The SYNC pin is TTL/
GND(ExposedPadPin±1%:GroundPin. Mustbesoldered
to a continuous copper ground plane to reduce die tem-
peratureandtoincreasethepowercapabilityofthedevice.
CMOS logic compatible. Tie to ground or V if not used.
CC
RT (Pin 31%: Timing Resistor Pin. Programs the switching
frequency from 200kHz to 1MHz. See Table 2 for the rec-
ommended R values for common switching frequencies.
T
37451f
11
LT3745-1
BLOCK DIAGRAM
37451f
12
LT3745-1
OPERATION
The LT3745-1 integrates a single constant-frequency
current-mode nonsynchronous buck controller with six-
teen linear current sinks. The buck controller generates
an adaptive output LED bus voltage to supply parallel
LED strings and the sixteen linear current sinks regulate
and modulate individual LED strings. Its operation is best
understood by referring to the Block Diagram.
LVDS Serial Data Interface
The LT3745-1 has a 30MHz, fully-buffered, cascadable
LVDS (low voltage differential signals) serial data in-
terface. Due to the differential signal transmission and
the low voltage swing, LVDS delivers the benefits of low
noise generation, high noise rejection, and low power
consumption for high data rate signals. Therefore, the
+
−
+
−
LT3745-1 uses LVDS logic for SCKI , SCKI , SDI , SDI ,
Start-Up
+
−
+
−
SCKO , SCKO , and SDO , SDO signals (high data rate
signals), and TTL/CMOS logic for LDI signal (low data rate
The LT3745-1 enters shutdown mode when the EN/UVLO
pin is lower than 0.35V. Once the EN/UVLO pin is above
0.35V, the part starts to wake up internal bias currents,
+
signal). In this data sheet, the differential signals SCKI ,
−
+
−
+
−
+
−
SCKI , SDI , SDI , SCKO , SCKO and SDO , SDO are
abbreviated to SCKI, SDI, SCKO and SDO, respectively.
generatevariousreferences,andchargethecapacitorC
CAP
towards6.8Vregulationvoltage.ThisV referencedvoltage
IN
The LT3745-1 can be connected to microcontrollers,
digital signal processors (DSPs), or field programmable
gate arrays (FPGAs) in two different topologies shown
in Figure 1. In topology #1, the LDI signal needs global
routing while the SCKI, and SDI signals only need local
routing between chips. Each chip provides the SCKO sig-
nal along with the SDO signal to drive the next chip. The
skew inside the chip between the SCKI and SDI signals
is balanced internally. The skew outside the chip between
the SCKO and SDO signals can be easily balanced by
parallel routing these two pairs of signals between chips.
The SDI signal is received with the SCKI signal, and the
SDO signal is sent with the SCKO signal. In a low data
rate application with a small number of cascaded chips,
the topology #1 can be simplified to the topology #2 by
ignoring the SCKO outputs.
regulator (V – V ) will supply the internal gate driver
IN
CAP
circuitry driving an external P-channel MOSFET in normal
operation. The LT3745-1 remains in undervoltage lockout
(UVLO)modeaslongasanyoneoftheEN/UVLO, V , and
CC
(V – V ) UVLO flags is high. Their UVLO thresholds
IN
CAP
are typically 1.30V, 2.86V, and 4.9V, respectively. After all
the UVLO flags are cleared, the buck controller starts to
switch, and the soft-start SS pin is released and charged
by a 12µA current source, thereby smoothly ramping up
the inductor current and the output LED bus voltage.
Power-on-Reset (POR%
During start-up, an internal power-on-reset (POR) high
signal blocks the input signals to the serial data interface
and resets all the internal registers except the 194-bit shift
register. The 1-bit frame select (FS) register, 1-bit enable
LEDchannel(EN)register,individual12-bitgrayscale(GS)
registers,andindividual6-bitdotcorrection(DC)registers
areallresettozero.ThusalltheLEDchannelsareturnedoff
initially with the default grayscale (0x000) and dot correc-
tion (0x00) setting. Once the part completes its soft-start
(i.e., the SS pin voltage is higher than 1V) and the output
LED bus voltage is power good (i.e., within 5ꢀ of its FB
programmed regulation level), the POR signal goes low
to allow the input signals to the serial data interface. Any
fault triggering the soft-start will generate another POR
high signal and reset internal registers again.
Figure2showstwoserialdatainputSDIframes(GSframe
andDCframe)andoneserialdataoutputSDOframe(status
frame). All the frames have the same 194-bit in length and
aretransmittedwiththeMSBfirstandtheLSBlast.TheSDI
frames are sent with the SCKI signal and the SDO frame is
received with the SCKO signal. The C0 bit (frame select)
determines any SDI frame to be either a GS frame (C0 = 0)
oraDCframe(C0=1), andtheC1bit(EN)enables(C1=1)
or disables (C1 = 0) all the LED channels. The status frame
reads back the T
pin resistor-programmable over-
SET
temperatureflagandindividualopen/shortLEDfaultflags,
as well as the individual 6-bit DC setting.
37451f
13
LT3745-1
OPERATION
LT3745-1 LVDS Topology #1
CONTROLLER
LDO
CHIP 1
+
CHIP 2
LDI
CHIP N
+
LDI
SCKI
LDI
SCKI
+
+
+
+
+
SCKO
SCKO
SCKI
SCKO
SCKO
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
–
–
–
+
–
–
+
–
–
+
SCKO
SCK-
SDI
SCKO
SDO
SCK-
SDI
SCKO
SDO
SCK-
SDI
SCKO
SDO
+
+
+
+
SDO
–
–
–
–
–
–
–
SDO
SDI
SDO
SDI
SDO
SDI
SDO
–
SDI
100Ω
100Ω
+
–
SDI
SCKI
+
SCKI
LDI
LT3745-1 LVDS Topology #2
CONTROLLER
LDO
CHIP 1
+
CHIP 2
LDI
CHIP N
+
LDI
SCKI
LDI
SCKI
+
+
+
+
+
SCKO
SCKO
SCKI
SCKO
SCKO
–
–
–
+
–
–
+
–
–
+
SCKO
SCK-
SDI
SCKO
SDO
SCK-
SDI
SCKO
SDO
SCK-
SDI
SCKO
SDO
+
+
+
+
SDO
100Ω
100Ω
100Ω
–
–
–
–
–
–
–
SDO
SDI
SDO
SDI
SDO
SDI
SDO
–
SDI
100Ω
100Ω
+
–
SDI
SCKI
+
SCKI
LDI
37451 F01
Figure 1. Two Topologies of the LT37±5-1 LVDS Serial Data Interface
Inside the part, there are one 194-bit shift register
SR[0:193], one 1-bit frame select (FS) register, one 1-bit
enable LED channel (EN) register, sixteen 12-bit grayscale
(GS) registers, sixteen 6-bit dot correction (DC) registers,
one 1-bit over temperature (OT) flag register, and sixteen
1-bit LED fault flag registers. The input of the 194-bit shift
register, i.e., the input of the first bit SR[0], is connected
to the SDI signal. The output of the 194-bit shift register,
i.e., the output of the last bit SR[193] is connected to the
SDOsignal.TheSCKIsignalshiftstheSDIframe(GSorDC
frame) in and the SCKO signal shift the SDO frame (status
frame) out of the 194-bit shift register with their rising
edges. The LDI high signal latches the SDI frame (GS or
DC frame) from the 194-bit shift register into correspond-
ing FS, EN, GS or DC registers, and loads the SDO frame
(status frame) from the OT and LED fault flag registers
to the 194-bit shift register at the same time. Therefore, a
daisy-chain type loop communication with simultaneous
writing and reading capability is implemented.
Figure 3 illustrates the timing relation among serial input
and serial output signals in more detail. One DC frame fol-
lowed by another GS frame is sent through the LDI, SCKI,
and SDI signals. At the same time, two status frames are
received through the SCKO and SDO signals. The rising
edges of the SCKI signal shift a frame of 194-bit data at
37451f
14
LT3745-1
OPERATION
194 BITS
GS
GS 15, 12 BITS
GS 0, 12 BITS
C1
C1
0
C0
C0
FRAME
DC
FRAME
DC 15, 6 BITS
DC 15, 6 BITS
x
x
x
x
x
x
DC 0, 6 BITS
DC 0, 6 BITS
x
x
x
x
x
x
STATUS
FRAME
0
0
0
0
0
S15
0
0
0
0
0
S0
F0
37451 F02
COMMAND REGISTER:
STATUS REGISTER:
C1: ENABLE LED CHANNELS - ENABLE = 1, DISABLE = 0
C0: FRAME SELECT - GS FRAME = 0, DC FRAME = 1
S0-S15: LED 0-15 FAULT - FAULT = 1, OK = 0
F0: OT - OVER TEMPERATURE = 1, OK = 0
Figure 2. Serial Data Frame Format
t
t
t
SU-LDI WH-LDI HD-LDI
LDI
SCKI
SDI
t
WH-CKI
1
186
193
194
1
192
193
194
1
t
SU-SDI
t
WL-CKI
t
HD-SDI
GS 15
MSB
DC 15
MSB
DC 0
LSB
GS 15
MSB
GS 0
LSB
C1
C0 = 1
C1
C0 = 0
DC 15
MSB
DC 0
LSB
GS 15
MSB
GS 0
LSB
GS 15
C1
C0 = 0
F0
SR[0]
SR[1]
C1
x
C0 = 1
C1
F0
0
MSB
DC 0
LSB + 1
GS 0
LSB + 1
GS 0
LSB
F0
C1
0
F0
t
PD-SCK↑
SCKO
1
186
193
194
1
192
193
194
t
t
PD-SCK↓
PD-SD
DC 15
MSB
DC 15
MSB
DC 15
MSB – 1
GS 15
MSB
DC 15
MSB
SDO/
SR[385]
0
F0
37451 F03
INPUT DATA
STATUS DATA
Figure 3. Serial Data Input and Output Timing Chart
37451f
15
LT3745-1
OPERATION
the SDI pins into the 194-bit shift register SR[0:193].
After 194 clock cycles, all the 194-bit data sit in the right
placewaitingfortheLDIsignal.AnasynchronousLDIhigh
signal latches the 1-bit FS register, 1-bit EN register, and
individual 12-bit GS registers (when FS = 0) or 6-bit DC
registers(whenFS=1)foreachchannel.Atthesametime,
a frame of status information, including over temperature
flag and individual open/short LED fault flags, is parallel
loaded into the 194-bit shift register and will be shifted
out with the coming clock cycles.
or disabled when its grayscale PWM dimming signal goes
high or low. This periodic grayscale PWM dimming signal
is generated by its own 12-bit grayscale register with a
duty cycle from 0/4096 to 4095/4096 and a period equal
to 4096 PWMCK clock cycles.
The generation of the grayscale PWM dimming signal is
bestunderstoodbyreferringtoFigure4. TheLVDSsignals
+
–
PWMCK , PWMCK areabbreviatedtothePWMCKsignal.
After EN = 1 is set, the first rising edge of the PWMCK
signal will increase the internal 12-bit grayscale counter
from zero to one and turn on all the LED channels with
grayscale value not zero. Each following rising edge of
the PWMCK signal increases the grayscale counter by
one. Any LED channel will be turned off when its 12-bit
grayscale register value is equal to the value in the gray-
scale counter. To generate a 100ꢀ duty cycle for all the
grayscale PWM dimming signals, the PWMCK signal can
be paused before counting to the value in any individual
12-bit grayscale registers. Setting EN = 0 will reset the
grayscale counter to zero and turn off all the LED chan-
nels immediately.
Constant Current Sink
Each LED channel has a local constant current sink regu-
lating its own LED current independent of the LED bus
voltage V . The recommended LED pin voltage ranges
OUT
from 0.8V to 3V. As shown in the Typical Performance
Characteristics I
vs V
curves, the LED current I
LED LED
LED
has the best load regulation when the LED pin voltage
sits above 0.5V. A lower LED bus voltage V may
V
LED
OUT
not regulate all the LED channels across temperature,
current, and manufacturing variation, while a higher LED
busvoltageV
willforceahigherLEDpinvoltageacross
OUT
the current sink, thereby dissipating more power inside
the part. See more details about the choice of the LED
bus voltage and the power dissipation calculation in the
Application Information section.
Dual-Loop Analog OR Control
Theswitchingfrequencycanbeprogrammedfrom200kHz
to 1MHz with the resistor connected to the RT pin and it
can be synchronized to an external clock using the SYNC
pin.Eachswitchingcyclestartswiththegatedriverturning
on the external P-channel MOSFET M1 and the inductor
Dot Correction and Grayscale Digital-to-Analog
Conversion
current is sampled through the sense resistor R between
S
The resistor on the I
pin programs the nominal LED
SET
the ISP and ISN pins. This current is amplified and added
to a slope compensation ramp signal, and the resulting
sum is fed into the positive terminal of the PWM compara-
tor. When this voltage exceeds the level at the negative
terminal of the PWM comparator, the gate driver turns
off M1. The level at the negative terminal of the PWM
current (10mA to 50mA) for all the channels. Individual
LED channel can be adjusted to a different current setting
by its own 6-bit dot correction register. The adjustable
LED current ranges from 0.5X to 1.5X of the nominal LED
current in 63 linear steps. See more details about setting
nominalLEDcurrentanddotcorrectionintheApplications
Information section.
comparator is set by either of two error amplifiers G
M1
and G . In this dual-loop analog OR control, the FB loop
M2
G
regulates the FB pin voltage to 1.205V and the LED
M1
In addition to the dot correction current adjustment,
individual LED channels can also be modulated by their
own grayscale PWM dimming signal. To achieve a better
performance, all the grayscale PWM dimming signals are
synchronized to the same frequency with no phase shift
betweenrisingedges.Eachconstantcurrentsinkisenabled
loop G regulates the minimum active LED pin voltage
M2
(LED00 to LED15) to 0.7V. In the start-up phase, the G
M2
is disabled and the output LED bus voltage is regulated
towards the feedback resistor programmed LED bus volt-
age. This FB programmed voltage defines the maximum
37451f
16
LT3745-1
OPERATION
LED bus voltage and should be programmed high enough
to supply the worst-case LED string across temperature,
current, and manufacturing variation.
all the LED channels being not active (i.e., either fault
or off) before the 3585th PWMCK clock, the PRECHG
signal will go high immediately.
Adaptive-Tracking-Plus-Precharging
To betterexplaintheoperationoftheadaptive-tracking-
plus-precharging technique, a simplified application
system with 3-channel LED array is presented in Fig-
ure 5. Each channel consists of a single LED with the
forward voltage drop equal to 3.1V, 3.5V, and 3.9V,
respectively. Three internal grayscale PWM dimming
signalsPWM1,PWM2,andPWM3areusedtomodulate
each LED channel.
Higher system efficiency and faster transient re-
sponse are two highly anticipated specifications in an
individually-modulated multi-channel LED driver chip.
TheLT3745-1usesapatentpendingadaptive-tracking-
plus-precharging technique to achieve both of them
simultaneously.
Besides 16 internal grayscale PWM dimming signals,
the part also generates another internal precharging
signal PRECHG. As shown in Figure 4, the PRECHG
signal divides any grayscale PWM dimming cycle
into two phases: tracking phase when PRECHG = 0
and precharging phase when PRECHG = 1. During
each grayscale PWM dimming cycle – 4096 PWMCK
clock cycles, the PRECHG signal stays low for the first
3584 clock cycles (7/8 of the grayscale PWM dimming
period) and goes high for the rest 512 clock cycles (1/8
of the grayscale PWM dimming period). In the event of
At the beginning of each grayscale PWM dimming
cycle, all three LED channels are turned on and the
tracking phase starts with PRECHG = 0. The amplifier
G
is enabled and takes the control from the amplifier
M2
G , regulating the minimum active LED pin voltage to
M1
0.7V. With the V
equal to 0.7V, the output LED bus
LED3
voltage is tracked to 4.6V. Subsequently, at a certain
time instant t when the third channel is turned off, the
1
minimum active LED pin voltage goes to V
, 1.1V.
LED2
ThentheamplifierG trackstheoutputLEDbusvoltage
M2
C1/EN
t
WH-PWM
PWMCK
I(LED00)
1
2
3
3584
3585
4095
4096
1
2
t
t
PD-PWM
WL-PWM
REG = 0x002
I(LED01)
I(LED15)
REG = 0xFFF
REG = 0x000
37451 F04
PRECHG
TRACKING PHASE
PRECHARGING PHASE
Figure ±. Grayscale PWM Dimming and Precharging Signal Timing Chart
37451f
17
LT3745-1
OPERATION
down to 4.2V to maintain the minimum active LED pin cycle. Without the precharging phase, the output LED
voltage equal to 0.7V again. Similarly, at the next time bus voltage will stay at 3.8V before the next grayscale
instant t , the output LED bus voltage is tracked down PWM dimmingcycle,whenallthe3LEDchannelswillbe
2
to3.8V.Inthismanner,theadaptive-trackingtechnique turned on again. At that time the 3.8V LED bus voltage
eliminates unnecessary power dissipation across the is too low to keep all the LED channels in regulation,
currentsinksandyieldssuperiorsystemefficiencywhen and the minimum LED on-time is greatly increased to
compared to a constant 4.6V output voltage.
accommodatetheslowtransientresponseoftheswitch-
ing buck converter charging the output capacitor from
3.8V to 4.6V. This adaptive-tracking-plus-precharging
LED bus voltage technique simultaneously lowers the
power dissipation in the LT3745-1 and maintains a
shorter minimum LED on-time.
At a later time instant t when the PRECHG signal goes
3
high, theamplifierG isdisabledandgivesthecontrol
M2
back to the amplifier G . The amplifier GM1 regulates
M1
theoutputLEDbusvoltagetowardstheFBprogrammed
maximum value 4.6V to guarantee shorter minimum
LED on-time for the next grayscale PWM dimming
4096*T
PWMCK
PWM
PWM
PWM
1
2
3
V
= 4.6V
(1)
(2)
(3)
OUT
+
+
+
3.1V
3.5V
3.9V
PRECHG
–
–
–
+
+
+
4.6V
4.6V
4.2V
4.2V
1.5V
1.1V
0.7V
IDEAL V
OUT
3.8V
3.8V
–
–
–
LT3745-1 V
OUT
4.6V
37451 F05
CONSTANT V
OUT
t
t
2
t t
3 4
1
Figure 5. Adaptive-Tracking-Plus-Precharging LED Bus Voltage Technique
37451f
18
LT3745-1
APPLICATIONS INFORMATION
Globally, theLT3745-1convertsahigherinputvoltagetoa
V Power Input Supply Range
IN
single lower LED bus voltage (V ) supplying 16 parallel
OUT
ThepowerinputsupplyfortheLT3745-1canrangefrom6V
to55V,coveringawidevarietyofindustrialpowersupplies.
LED strings with the adaptive-tracking-plus-precharging
technique. Locally, the part regulates and modulates the
current of each string to an independent dot correction
and grayscale PWM dimming setting sent by LVDS logic
serial data interface. This Application Information section
serves as a guideline of selecting external components
(refer to the Block Diagram) and avoiding common pitfalls
for the typical application.
AnotherrestrictionontheminimuminputvoltageV
IN(MIN)
IN
is the 2.1V minimum dropout voltage between the V and
ISN pins, and thus the V
is calculated as:
IN(MIN)
V
= V
+ 2.1V
IN(MIN)
OUT(MAX)
Choosing Switching Frequency
Selectionoftheswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency operation
improvesefficiencybyreducingMOSFETswitchinglosses
and gate charge losses. However, lower frequency opera-
tion requires larger inductor and capacitor values.
Programming Maximum V
OUT
The adaptive-tracking-plus-precharging technique regu-
lates V to its maximum value during the start-up and
OUT
precharging phases, and adaptively lowers the voltage to
keep the minimum active LED pin voltage around 0.7V
during the tracking phase. Therefore, the maximum V
Another restriction on the switching frequency comes
from the input and output voltage range caused by the
minimum switch on and switch off-time. The highest
OUT
should be programmed high enough to keep all the LED
pin voltages higher than 0.8V to maintain LED current
regulation across temperature, current, and manufactur-
ing variation. As a starting point, the maximum LED bus
switching frequency f
be calculated as:
for a given application can
SW(MAX)
voltage, V
, can be calculated as:
OUT(MAX)
DMIN 1–DMAX
,
fSW(MAX) = MIN
tON(MIN) tOFF(MIN)
V
= 0.8V + n • V
OUT(MAX)
F(MAX)
where n is the number of LED per string and V
the maximum LED forward voltage rated at the highest
operating current and the lowest operating temperature.
is
F(MAX)
where the minimum duty cycle D
and the maximum
MIN
duty cycle D
are determined by:
MAX
VOUT(MIN) + VD
VOUT(MAX) + VD
The V
is programmed with a resistor divider
DMIN
=
and DMAX
=
OUT(MAX)
VIN(MAX) + VD
VIN(MIN) + VD
between the output and the FB pin. The resistor values
are calculated as:
t
istheminimumswitchon-time(~200ns),t
OFF(MIN)
ON(MIN)
V
is the minimum switch off-time (~120ns), V
is the
RFB2 = RFB1 OUT(MAX) − 1
OUT(MIN)
isthemaximum
minimumadaptiveoutputvoltage,V
1.210V
IN(MAX)
input voltage, and V is the catch diode forward voltage
D
(~0.5V). The calculation of f
simplifies to:
Tolerance of the feedback resistors will add additional er-
rorstotheoutputvoltage, so1ꢀresistorvaluesshouldbe
used. The FB pin output bias current is typically 120nA, so
use of extremely high value feedback resistors could also
SW(MAX)
fSW(MAX)
=
OUT(MAX)
VIN(MIN) – V
VOUT(MIN) + V
MIN 5•
D,8.33•
MHz
cause bias current errors. A typical value for R is 10k.
FB1
VIN(MAX) + VD
VIN(MIN) + VD
37451f
19
LT3745-1
APPLICATIONS INFORMATION
Obviously,lowerfrequencyoperationaccommodatesboth
Inductor Current Sense Resistor R and Current Limit
S
extremely high and low V
to V ratios.
OUT
IN
The current sense resistor, R , monitors the inductor
S
Besides these common considerations, the specific appli-
cation also plays an important role in switching frequency
choice.Inanoise-sensitivesystem,theswitchingfrequency
is usually chosen to keep the switching noise out of a
sensitive frequency band.
current between the ISP and ISN pins, which are the in-
puts to the internal current sense amplifier. The common
mode input voltage of the current sense amplifier ranges
from 0V to (V – 2.1V) or 36V absolute maximum value,
IN
whichever is lower. The current sense amplifier not only
provides current information to form the current mode
control, but also a 44mV threshold. The 44mV threshold
Switching Frequency Setting and Synchronization
across the R resistor imposes an accurate current limit
The LT3745-1 uses a constant switching frequency that
can be programmed from 200kHz to 1MHz with a resistor
S
to protect both P-channel MOSFET M1 and catch diode
D1, and also to prevent inductor current saturation. Good
Kelvin sensing is required for accurate current limit. The
from the RT pin to ground. Table 2 shows R values for
T
common switching frequencies.
R resistor value can be determined by:
S
Table 2. Switching Frequency fSW vs RT Value
∆ IL
f
(kHz%
R * (kΩ%
SW
T
IOUT(MAX) = IL(MAX)
–
200
280
182
2
300
400
500
600
700
800
900
1000
where the maximum inductor current I
44mV
is set by:
L(MAX)
133
105
IL(MAX)
=
84.5
71.5
60.4
53.6
46.4
RS
I
is the maximum output load current, and ∆I
is the inductor peak-to-peak ripple current. Allowing ad-
equate margin for ripple current and external component
tolerances, R can be estimated as:
OUT(MAX)
L
* Recommend 1ꢀ Standard Values
S
Synchronizing the LT3745-1 oscillator to an external fre-
quency can be achieved using the SYNC pin. The square
wave amplitude, compatible to TTL/CMOS logic, should
have valleys that are below 0.6V and peaks that are above
2.4V. The synchronization frequency also ranges from
35mV
RS =
IOUT(MAX)
Inductor Selection
200kHz to 1MHz, in which the R resistor should be cho-
T
The critical parameters for selection of an inductor are
inductance value, DC or RMS current, saturation current,
and DCR resistance. For a given input and output voltage,
the inductor value and switching frequency will determine
sen to set the internal switching frequency around 20ꢀ
belowthesynchronizationfrequency.Inthecaseof200kHz
synchronization frequency, R = 348k is recommended.
T
It is also important to note that when the synchroniza-
the peak-to-peak ripple current, ∆I . The ∆I value usually
L
L
tion frequency is much higher than the R programmed
T
ranges from 20ꢀ to 50ꢀ of the maximum output load
internal frequency, the internal slope compensation will
be significantly reduced, which may trigger sub-harmonic
oscillation at duty cycles greater than 50ꢀ.
current, I
. Lower values of ∆I require larger and
OUT(MAX)
L
more costly inductors; higher values of ∆I increase the
L
peak currents and the inductor core loss. An inductor
37451f
20
LT3745-1
APPLICATIONS INFORMATION
current ripple of 30ꢀ to 40ꢀ offers a good compromise
22mA current capability of the internal regulator limits the
betweeninductorperformanceandinductorsizeandcost.
maximum Q
it can deliver to:
G(MAX)
However, for high duty cycle applications, a ∆I value of
L
22mA
fSW
QG(MAX)
=
~20ꢀ should be used to prevent sub-harmonic oscillation
due to insufficient slope compensation.
The largest inductor ripple current occurs at the highest
IN
specified maximum, the inductor value should be chosen
according to the following equation:
Therefore, the Q at V = 6.8V from the MOSFET data
G
GS
V . To guarantee that the ripple current stays below the
sheet should be less than Q
.
G(MAX)
For maximum efficiency, both R
and C
should
RSS
DS(ON)
be minimized. Lower R
means less conduction loss
DS(ON)
V
IN(MAX) – VOUT
while lower C
DS(ON)
reduces transition loss. Unfortunately,
VOUT + VD
IN(MAX) + VD
RSS
L ≥
•
R
is inversely related to C . Thus balancing the
RSS
V
fSW • ∆IL
conduction loss with the transition loss is a good criterion
in selecting a MOSFET. For applications with higher V
IN
The inductor DC or RMS current rating must be greater
than the maximum output load current I and its
voltages (≥24V) a lower C
is more important than a
RSS
OUT(MAX)
low R
.
DS(ON)
saturation current should be higher than the maximum
inductor current I . To achieve high efficiency, the
L(MAX)
Catch Diode Selection
DCR resistance should be less than 0.1Ω, and the core
materialshouldbeintendedforhighfrequencyapplications.
The catch diode D1 carries load current during the switch
off-time.Importantparametersforthecatchdiodeincludes
Power MOSFET Selection
peak repetitive reverse voltage (V
), forward voltage
RRM
(V ), and maximum average forward current (I
). The
F
F(AV)
Important parameters for the external P-channel MOSFET
diode V
specification should exceed the maximum
RRM
M1includedrain-to-sourcebreakdownvoltage(V
,
(BR)DSS)
), maximum
reverse voltage across it, i.e., V
. A fast switching
IN(MAX)
maximum continuous drain current (I
D(MAX)
), total gate charge (Q ),
SchottkydiodewithlowerV shouldbeusedtoyieldlower
F
gate-to-source voltage (V
GS(MAX)
G
power loss and higher efficiency.
drain-to-source on resistance (R
), reverse transfer
specification
(BR)DSS
DS(ON)
capacitance (C ). The MOSFET V
In continuous conduction mode, the average current
conducted by the catch diode is calculated as:
RSS
should exceed the maximum voltage across the source to
the drain of the MOSFET, which is V plus V . The
IN(MAX)
D
I
= I
• (1 – D)
D(AVG)
OUT
I
should exceed the peak inductor current, I
Since the gate driver circuit is supplied by the internal
.
D(MAX)
L(MAX)
The worst-case condition for the diode is when V
is
OUT
OUT
shorted to ground with maximum V and maximum I
6.8V V referenced regulator, the V
be at least 10V.
rating should
IN
IN
GS(MAX)
at present. In this case, the diode must safely conduct
the maximum load current almost 100ꢀ of the time. To
improve efficiency and to provide adequate margin for
short-circuit operation, a Schottky diode rated to at least
the maximum output current is recommended.
EachswitchingcycletheMOSFETisswitchedoffandon, a
packet of gate charge Q is transferred from the V pin to
G
IN
the GATE pin, and then from the GATE pin to the CAP pin.
The resulting dQ /dt is a current that must be supplied to
G
theC capacitorbytheinternalregulator.Themaximum
CAP
37451f
21
LT3745-1
APPLICATIONS INFORMATION
C , C , and C
Capacitor Selection
be paralleled to meet size or height requirements in the
design. Locate the capacitor very close to the MOSFET
switchandthecatchdiode,anduseshort,widePCBtraces
to minimize parasitic inductance.
IN VCC
CAP
A local input bypass capacitor C is required for buck
IN
converters because the input current is pulsed with fast
riseandfalltimes.Theinputcapacitorselectioncriteriaare
based on the voltage rating, bulk capacitance, and RMS
current capability. The capacitor voltage rating must be
The general discussion above also applies to the capacitor
C
at the V pin and the capacitor C between the V
VCC
CC CAP IN
greaterthanV .Thebulkcapacitancedeterminesthe
IN(MAX)
and CAP pins. Typically, a 10µF 10V-rated ceramic capaci-
input supply ripple voltage and the RMS current capability
is used to keep from overheating the capacitor.
tor for C
C
and a 0.47µF 16V-rated ceramic capacitor for
VCC
should be sufficient.
CAP
The bulk capacitance is calculated based on maximum
C
OUT
Capacitor Selection
input ripple, ∆V :
IN
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
the LT3745-1 to produce the DC output containing a con-
trolled voltage ripple. It also stores energy to satisfy load
transients and to stabilize the dual-loop operation. Thus
DMAX • IOUT(MAX)
CIN
=
∆VIN • fSW
∆V is typically chosen at a level acceptable to the user.
IN
100mV is a good starting point. For ceramic capacitors,
only X5R or X7R type should be used because they retain
their capacitance over wider voltage and temperature
ranges than other types such as Y5V or Z5U. Aluminum
electrolytic capacitors are a good choice for high voltage,
bulkcapacitanceduetotheirhighcapacitanceperunitarea.
the selection criteria for C
are based on the voltage
OUT
rating, the equivalent series resistance ESR, and the bulk
capacitance. As always, choose the C with a voltage
OUT
rating greater than V
.
OUT(MAX)
The LT3745-1 utilizes the output as the dominant pole
to stabilize the dual loop operation, so the C
value
OUT
The capacitor RMS current is:
determines the unity gain frequency f , which is set
UGF
around1/10oftheswitchingfrequency. To stabilizetheFB
loop during the start-up and precharging phases and the
LED loop during the tracking phase, a low ESR capacitor
VOUT • ( VIN – VOUT
)
ICIN(RMS) = IOUT
•
VI2N
(tens of mΩ) should be used and its minimum C
calculated as:
is
OUT
If applicable, calculate at the worst-case condition,
V = 2 • V . The capacitor RMS current rating specified
bythemanufacturershouldexceedthecalculatedI
DuetotheirlowESR,ceramiccapacitorsareagoodchoice
for high voltage, high RMS current handling. Note that the
ripplecurrentratingsfromaluminumelectrolyticcapacitor
manufacturersarebasedon2000hoursoflife.Thismakes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
IN
OUT
.
0.25
RS • fUGF
1.5
VOUT(MAX) • RS • fUGF
CIN(RMS)
COUT = MAX
,
Theadaptive-tracking-plus-prechargingtechniquemoves
the V with the grayscale PWM dimming frequency to
OUT
improve system efficiency, choosing a ceramic capacitor
as the C inevitably generates acoustic noise due to the
OUT
piezo effect of the ceramic material. In an acoustic noise
sensitive application, low ESR tantalum or aluminum
capacitors are preferred. When choosing a capacitor,
For a larger high voltage capacitor value, the combination
ofaluminumelectrolyticcapacitorsandceramiccapacitors
is an economical approach. Multiple capacitors may also
37451f
22
LT3745-1
APPLICATIONS INFORMATION
look carefully through the data sheet to find out what the
actual capacitance is under operating conditions (applied
voltage and temperature). A physically larger capacitor, or
one with a higher voltage rating, may be required.
Soft-Start
During soft-start, the SS pin voltage smoothly ramps up
inductor current and output voltage. The effective voltage
range of SS pin is from 0V to 1V. Therefore, the typical
soft-start period is:
Undervoltage Lockout (UVLO% and Shutdown
C
SS • 1V
12µA
LT3745-1 has three UVLO thresholds with hysteresis for
tSS
=
the EN/UVLO, V , and CAP pins. The part will remain in
CC
UVLO mode not switching until all the EN/UVLO, V , and
CC
where C is the capacitor connected at SS pin and
SS
(V – V ) voltages pass their respective typical thresh-
IN
CAP
12µA is the soft-start charge current. Whenever a UVLO
orthermalshutdownoccurs, theSSpinwillbedischarged
and the part will stop switching until the UVLO event has
disappeared and the SS pin has reached it reset threshold,
0.35V. The part then initiates a new soft-start cycle.
olds (1.30V, 2.86V, and 4.9V). As shown in Figure 6, the
EN/UVLO pin can be controlled in two different ways. The
EN/UVLO pin can accept a digital input signal to enable or
disable the chip. Tie to 0.35V or lower to shut down the
chip or tie to 1.34V or higher for normal operation. This
pincanalsobeconnectedtoaresistordividerbetweenV
IN
Setting Nominal LED Current
andgroundtoprogramapowerinputV UVLOthreshold.
IN
The nominal LED current is defined as the average LED
current across 16-channel when all the individual dot cor-
rection registers are set to 0x20. The nominal LED current
After R
is selected, R
can be calculated by:
UV1
UV2
V
IN(ON)
RUV2 = RUV1
•
– 1
1.3V
is programmed by a single resistor, R , between the
ISET
I
pin and ground. The voltage at the I
pin, V
,
SET
SET
ISET
where V
is the power input voltage above which the
IN(ON)
is trimmed to an accurate 1.205V, generating a current
inversely proportional to R . The nominal LED current,
part goes into normal operation. It is important to check
the EN/UVLO pin voltage not to exceed its 4V absolute
maximum rating:
ISET
I
, can be calculated as:
LED(NOM)
VISET
RISET
ILED(NOM)
=
• 2500
RUV1
RUV1 + RUV2
VIN(MAX)
•
< 4V
V
IN
V
V
V
V
IN
IN
R
R
CC
CC
UV2
FROM µCONTROLLER
EN/UVLO
EN/UVLO
UV1
37451 F06
(6a)
(6b)
Figure 6. Methods of Controlling the EN/UVLO Pin
37451f
23
LT3745-1
APPLICATIONS INFORMATION
I
must be set between 10mA and 50mA. Typical
control the amount of LED on-/off-time by pulse width
modulation (PWM).
LED(NOM)
R
ISET
resistor values for various nominal LED currents
are listed in Table 3.
The LT3745-1 can adjust the brightness for each channel
independently.The12-bitgrayscalePWM dimmingresults
in 4096 linear brightness steps from 0ꢀ to 99.98ꢀ. The
Table 3. Nominal LED Current ILED(NOM% vs. RISET Value
I
(mA%
R * (kΩ%
ISET
LED(NOM%
brightness level GS ꢀ for channel n can be calculated as:
10
301
n
20
30
40
50
150
100
75
GSn
4096
GSnꢀ =
• 100ꢀ
where GS is the nth programmed grayscale setting
(GS = 0 to 4095).
60.4
n
* Recommend 1ꢀ Standard Values
n
Setting Dot Correction
Open/Short LED Fault
The LT3745-1 can adjust the LED current for each channel
independently. This fine current adjustment, also called
dot correction, is mainly used to calibrate the brightness
deviation between LED channels. The 6-bit (64 steps) dot
correction setting adjusts each LED current from 0.5X to
1.5X of the nominal LED current according to:
The LT3745-1 has individual LED fault diagnostic circuitry
that detects both open and short LED faults for each chan-
nel. The open LED fault is defined as any LED string is
open or disconnected from the circuit; and the short LED
fault is defined as any LED string is shorted across itself.
The open LED flag is set if the LED pin voltage is lower
than 0.35V (typical) during on status with initial 500ns
blanking. The short LED flag is set if the LED pin voltage
DC + 32
n
ILEDn = ILED(NOM)
where I
•
64
is higher than 75ꢀ of the LED bus voltage V
any time.
OUT
IfoneLEDchannelisshortedacrossitself, thechannelwill
be turned off to eliminate unnecessary power dissipation.
The function can also be used to disable LED channels by
connecting their LED pins to the output directly. Both the
open and short LED flags are combined to set the LED
fault bits (S0 to S15) in the status frame to 1.
is the nth LED current and DC is the nth
LEDn
n
programmed dot correction setting (DC = 0 to 63). The
n
fine current step over the nominal LED current gives an
excellent resolution:
∆ILED
ILED(NON) 64
1
=
≈ 1.56ꢀ
Thermal Protection
which enhances the relative LED current match accuracy
if used as calibration.
The LT3745-1 has two overtemperature thresholds: one
is the fixed internal thermal shutdown and the other one
is programmed by a resistor, R
, between the T
TSET
SET
Setting Grayscale
pin and ground. When the junction temperature exceeds
165°C, the part will enter thermal shutdown mode, shut
downserialdatainterface, turnoffLEDchannels, andstop
switching. After the junction temperature drops below
155°C, the part will initiate a new soft-start.
Although adjusting the LED current changes its luminous
intensity, or brightness, it will also affect the color match-
ing between LED channels by shifting the chromaticity
coordinate. The best way to adjust the brightness is to
37451f
24
LT3745-1
APPLICATIONS INFORMATION
When the R
is placed at the T pin, a current equal
where N is the number of LT3745-1 chips and
LT3745-1
REFRESH
TSET
SET
to the current flowing through the R
passes the
f
is the refresh rate of the whole system.
ISET
R
, generating a voltage V
at the T
pin, which
TSET
TSET
SET
Calculating Power Dissipation
is calculated as:
The total power dissipation inside the chip can be calcu-
lated as:
RTSET
RISET
VTSET = 1.205V •
PTOTAL = VIN • (IVIN + fSW • QG) + VCC
Then the V
is compared to an internal proportional-
TSET
15
to-absolute-temperature voltage V
,
PTAT
• IVCC
+
GSnꢀ • ILEDn • VLEDn
∑
n=0
V
= 1.72mV • (T + 273.15)
J
PTAT
where T is the LT3745-1 junction temperature in °C.
where I is the power input V quiescent current, I
J
VIN
IN
VCC
When V
is higher than V
, an overtemperature flag
is the V supply current, and V
is the LED pin volt-
PTAT
TSET
CC
LEDn
OT = 1 is set. Once the R
exceeded, the part will also gradually derate the nominal
LED current I
without interrupting its normal operation.
programmed temperature is
age for channel n.
TSET
From the total power dissipation P
, the junction
TOTAL
to limit the total power dissipation
LED(NOM)
temperature T can be calculated as:
J
T = T + P
• θ
JA
J
A
TOTAL
Cascading Devices and Determining Serial Data
Interface Clock
Keep T below the maximum operating junction tempera-
J
ture 125°C.
InalargeLCDbacklightingorLEDdisplaysystem,multiple
LT3745-1 chipscanbe easilycascaded todriveall the LED
strings.Theminimumserialdatainterfaceclockfrequency
f
for a large display system can be calculated as:
SCKI
f
= N • 194 • f
LT3745-1 REFRESH
SCKI
37451f
25
LT3745-1
TYPICAL APPLICATION
V
IN
4.7µF
50V
10V TO 40V
0.47µF
16V
V
CAP
GATE
IN
EN/UVLO
L1
22µH
EN
M1
4V MAXIMUM OUTPUT VOLTAGE
25mΩ
100k
V
CC
3V TO 3.6V
C1
220µF
V
CC
D1
10µF
10V
SYNC
23.2k
10k
GND
RT
SS
ISP
ISN
LT3745-1
105k
10nF
FB
I
SET
LED00
LED01
LED02
LED03
LED04
60.4k
T
SET
32.4k
+
–
409.6kHz
LVDS CLOCK
PWMCK
PWMCK
LED05
.
.
.
LED10
LED11
LED12
LED13
LED14
LED15
37451 F07
+
SCKI
+
–
SCKO
SCKI
C1: SANYO 6TPE220MI
D1: DIODES DFLS160
LVDS
–
+
SCKO
SDI
LVDS
+
–
SDO
SDI
L1: WÜRTH ELECTRONIK 7447779122
M1: VISHAY Si9407BDY
–
SDO
LDI
Figure 7. 16-Channel LED Driver, 500kHz Buck, 1 LED 25mA to 75mA per Channel, 100Hz 12-Bit Dimming
37451f
26
LT3745-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UJ Package
±0-Lead Plastic QFN (6mm × 6mm%
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 0.05
6.50 0.05
5.10 0.05
4.42 0.05
4.50 0.05
(4 SIDES)
4.42 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.115
TYP
6.00 0.10
(4 SIDES)
R = 0.10
TYP
39 40
0.40 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.45 OR
0.35 ¥ 45
CHAMFER
4.42 0.10
4.50 REF
(4-SIDES)
4.42 0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
BOTTOM VIEW—EXPOSED PAD
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
37451f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3745-1
TYPICAL APPLICATION
V
IN
42V TO 55V
4.7µF
100V
0.47µF
16V
V
CAP
GATE
IN
L1
47µH
EN
EN/UVLO
M1
33.4V MAXIMUM OUTPUT VOLTAGE
25mΩ
100k
C1
47µF
×2
V
CC
V
CC
3V TO 3.6V
D1
10µF
10V
267k
10k
SYNC
GND
RT
SS
ISP
ISN
LT3745-1
46.4k
60.4k
10nF
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
FB
I
SET
LED00
LED01
T
SET
32.4k
LED02
.
.
.
+
–
2.048MHz
LVDS CLOCK
PWMCK
PWMCK
LED13
LED14
LED15
+
–
37451 F08
SCKI
+
SCKO
SCKI
C1: SANYO 35SVPD47M
D1: DIODES DFLS160
LVDS
–
+
–
SCKO
SDI
LVDS
+
SDO
SDI
L1: WÜRTH ELECTRONIK 744771147
M1: VISHAY Si9407BDY
–
SDO
LDI
Figure 8. 16-Channel LED Driver, 1MHz Buck, 10 LEDs, 25mA to 75mA per Channel, 500Hz 12-Bit Dimming
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
V : 6V to 55V, V
LT3745
LT3746
LT3476
LT3486
LT3496
LT3595
LT3598
LT3599
LT3754
LT3760
16-Channel 50mA LED Driver with Buck Controller
= 36V, 6-Bit Dot Correction Current
OUT(MAX)
IN
Adjustment, 12-Bit Grayscale Dimming, 6mm × 6mm QFN Package
32-Channel 20mA LED Driver with Buck Controller
V : 6V to 55V, V = 13V, 6-Bit Dot Correction Current
IN
OUT(MAX)
Adjustment, 12-Bit Grayscale Dimming, 5mm × 9mm QFN Package
Quad Output 1.5A, 2MHz High Current LED Driver with
1,000:1 Dimming
V : 2.8V to 16V, V
= 36V, True Color PWM™ Dimming = 1000:1,
IN
SD
OUT(MAX)
I
< 10µA, 5mm × 7mm QFN-10 Package
Dual 1.3A , 2MHz High Current LED Driver
V : 2.5V to 24V, V
= 36V, True Color PWM Dimming = 1000:1,
IN
SD
OUT(MAX)
I
< 1µA, 5mm × 3mm DFN-16 TSSOP-16E Package
Triple Output 750mA, 2.1 MHz High Current LED Driver with V : 3V to 30V, V
= 60V, True Color PWM Dimming = 3000:1,
IN
OUT(MAX)
3,000:1 Dimming
I
< 1µA, 4mm × 5mm QFN-28 Package
SD
45V, 2.5MHz 16-Channel Full Featured LED Driver
V : 4.5V to 45V, V
= 45V, True Color PWM Dimming = 5000:1,
IN
SD
OUT(MAX)
I
< 1µA, 5mm × 9mm QFN-56 Package
44V, 1.5A, 2.5MHz Boost 6-Channel 30mA LED Driver
44V, 2A, 2.5MHz Boost 4-Channel 120mA LED Driver
V : 3V to 40V, V
= 44V, True Color PWM Dimming = 1000:1,
IN
SD
OUT(MAX)
OUT(MAX)
I
< 1µA, 4mm × 4mm QFN-24 Package
V : 3V to 40V, V
= 44V, True Color PWM Dimming = 1000:1,
< 1µA, 4mm × 4mm QFN-24 Package
IN
SD
I
60V, 1MHz Boost 16-Channel 50mA LED Driver with True
Color 3,000:1 PWM Dimming and 2.8ꢀ Current Matching
V : 4.5V to 40V, V
= 60V, True Color PWM Dimming = 3000:1,
IN
SD
OUT(MAX)
I
< 1µA, 5mm × 5mm QFN-32 Package
60V, 1MHz Boost 8-Channel 100mA LED Driver with True
Color 3,000:1 PWM Dimming and 2.8ꢀ Current Matching
V : 4.5V to 40V, V
= 60V, True Color PWM Dimming = 3000:1,
IN
SD
OUT(MAX)
I
< 1µA, TSSOP-28E Package
37451f
LT 0512 • PRINTED IN USA
28 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2012
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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