IS61LV256-10T [ISSI]
Standard SRAM, 32KX8, 10ns, CMOS, PDSO28, 0.450 INCH, PLASTIC, TSOP1-28;型号: | IS61LV256-10T |
厂家: | INTEGRATED SILICON SOLUTION, INC |
描述: | Standard SRAM, 32KX8, 10ns, CMOS, PDSO28, 0.450 INCH, PLASTIC, TSOP1-28 静态存储器 光电二极管 内存集成电路 |
文件: | 总8页 (文件大小:53K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
IS61LV256
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
ISSI
OCTOBER 1999
DESCRIPTION
FEATURES
The ISSI IS61LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using
ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns maximum.
• High-speed access times:
-- 8, 10, 12, 15, 20 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
-- 345 mW (max.) operating
When CE is HIGH (deselected), the device assumes a
standbymodeatwhichthepowerdissipationisreducedto
50 µW (typical) with CMOS input levels.
-- 7 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
Easy memory expansion is provided by using an active
LOW Chip Enable (CE). The active LOW Write Enable
(WE) controls both writing and reading of the memory.
• Fully static operation: no clock or refresh
required
• Three-state outputs
TheIS61LV256isavailableintheJEDECstandard28-pin,
300-mil SOJ and the 450-mil TSOP (Type I) package.
FUNCTIONAL BLOCK DIAGRAM
256 X 1024
MEMORY ARRAY
A0-A14
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. I
1
11/09/99
®
IS61LV256
ISSI
PIN CONFIGURATION
28-Pin SOJ
PIN CONFIGURATION
28-Pin TSOP (Type I)
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
OE
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CE
2
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A6
4
A8
A5
5
A9
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A4
6
A11
OE
A3
7
A2
8
A10
CE
2
A1
9
3
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
4
I/O0
I/O1
I/O2
GND
5
6
A1
A2
7
8
TRUTH TABLE
PIN DESCRIPTIONS
Mode
WE
CE
OE
I/O Operation Vcc Current
A0-A14
CE
Address Inputs
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
Chip Enable Input
Output Enable Input
Write Enable Input
Input/Output
OE
Output Disabled
Read
H
H
L
L
L
L
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
WE
I/O0-I/O7
Vcc
Write
X
Power
GND
Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
VCC
Power Supply Voltage Relative to GND
Terminal Voltage with Respect to GND
Temperature Under Bias
–0.5 to +4.6
–0.5 to +4.6
VTERM
TBIAS
V
Com.
Ind.
–10 to +85
–45 to +90
°C
TSTG
PD
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150
°C
W
1
IOUT
±20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. I
11/09/99
®
IS61LV256
ISSI
OPERATING RANGE
Range
Ambient Temperature
Speed
VCC
Commercial
0°C to +70°C
8, 10, 12
15, 20
3.3V, +10%, –5%
3.3V ± 10%
Industrial
–40°C to +85°C
All
3.3V + 10%, –5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 4.0 mA
2.4
—
—
0.4
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
V
2.2
–0.3
VCC + 0.3
0.8
V
V
GND ≤ VIN ≤ VCC
Com.
Ind.
–1
–5
1
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled Com.
–1
–5
1
5
µA
Ind.
Notes:
1. VIL (min.) = –0.3V (DC); VIL (min.) = –2.0V (pulse width ≤ 2.0 ns).
VIH (max.) = VCC + 0.5V (DC); VIH (max.) = Vcc + 2.0V (pulse width ≤ 2.0 ns).
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
(2)
(2)
-10 ns
Min. Max.
-8 ns
Min. Max.
-12ns
Min. Max.
-15ns
Min. Max.
-20ns
Min. Max.
Sym. Parameter
TestConditions
CC =Max.,CE =VIL
OUT = 0 mA, f = fMAX
Unit
I
CC
VccDynamicOperating
SupplyCurrent
V
I
Com.
Ind.
—
—
120
—
—
—
110
120
—
—
100
110
—
—
90
100
—
—
80
90
mA
I
SB
1
TTLStandbyCurrent
(TTLInputs)
V
CC =Max.,
Com.
Ind.
—
—
15
—
—
—
10
20
—
—
10
20
—
—
10
20
—
—
10
20
mA
mA
VIN =VIH orVIL
CE ≥ VIH, f = 0
CC =Max.,
CE CC –0.2V,
IN >VCC –0.2V, or
0.2V, f = 0
ISB
2
CMOSStandby
Current(CMOSInputs)
V
Com.
Ind.
—
—
2
—
—
—
2
5
—
—
2
5
—
—
2
5
—
—
2
5
≤
V
V
V
IN
≤
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Shaded area = PREPRODUCTION AVAILABILITY.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
Output Capacitance
6
5
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. I
3
11/09/99
®
IS61LV256
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
(2)
(2)
-8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
-20 ns
Min. Max.
Symbol Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
8
—
2
—
8
10
—
2
—
10
—
10
5
12
—
2
—
12
—
12
6
15
—
2
—
15
—
15
7
20
—
2
—
20
—
20
8
tAA
Address Access Time
Output Hold Time
CE Access Time
tOHA
tACE
tDOE
tLZOE
—
8
—
—
0
—
—
0
—
—
0
—
—
0
—
—
0
OE Access Time
4
(3)
(3)
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE to Power-Up
—
4
—
5
—
5
—
6
—
6
tHZOE
—
3
—
3
—
3
—
3
—
3
(3)
tLZCE
tHZCE
—
4
—
5
—
6
—
7
—
7
(3)
—
0
—
0
—
0
—
0
—
0
(4)
tPU
—
8
—
10
—
12
—
15
—
20
(4)
tPD
CE to Power-Down
—
—
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. Shaded area = PREPRODUCTION AVAILABILITY.
3. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100%
tested.
4. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
319 Ω
319 Ω
3.3V
3.3V
OUTPUT
OUTPUT
353 Ω
353 Ω
5 pF
30 pF
Including
jig and
Including
jig and
scope
scope
Figure 1.
Figure 2.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. I
11/09/99
®
IS61LV256
AC WAVEFORMS
ISSI
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
HIGH-Z
DOUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. I
5
11/09/99
®
IS61LV256
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
(3)
(3)
-8 ns
Min. Max.
-10 ns
Min. Max.
-12ns
Min. Max.
-15ns
Min. Max.
-20ns
Min. Max.
Symbol Parameter
Unit
ns
tWC
tSCE
tAW
Write Cycle Time
8
—
—
—
10
8
—
—
—
12
8
—
—
—
15
10
10
—
—
—
20
12
12
—
—
—
CE to Write End
6.5
6.5
ns
Address Setup Time
to Write End
8
8
ns
tHA
Address Hold
from Write End
0
—
0
—
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
6.5
8
—
—
—
—
—
3.5
—
0
7
—
—
—
—
—
4
0
8
—
—
—
—
—
6
0
10
15
7
—
—
—
—
—
7
0
12
20
10
0
—
—
—
—
—
7
ns
ns
ns
ns
ns
ns
ns
tPWE1
tPWE2
tSD
WE Pulse Width (OE HIGH)
WE Pulse Width (OE LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
10
5
12
6
5
tHD
0
0
0
0
(4)
tHZWE
—
0
—
0
—
0
—
0
—
0
(4)
tLZWE
—
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing
are referenced to the rising or falling edge of the signal that terminates the Write.
3. Shaded area = PREPRODUCTION AVAILABILITY.
4. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
AC WAVEFORMS
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 )
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
t
PWE1
PWE2
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR1.eps
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. I
11/09/99
®
IS61LV256
ISSI
WRITE CYCLE NO. 2(WE Controlled, OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR2.eps
WRITE CYCLE NO. 3(WE Controlled, OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE • VIH.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. I
7
11/09/99
®
IS61LV256
ISSI
ORDERING INFORMATION
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
8
IS61LV256-8T
IS61LV256-8J
TSOP - Type I
300-mil Plastic SOJ
10
12
15
20
IS61LV256-10TI
IS61LV256-10JI
TSOP - Type I
300-mil Plastic SOJ
10
12
15
20
IS61LV256-10T
IS61LV256-10J
TSOP - Type I
300-mil Plastic SOJ
IS61LV256-12TI
IS61LV256-12JI
TSOP - Type I
300-mil Plastic SOJ
IS61LV256-12T
IS61LV256-12J
TSOP - Type I
300-mil Plastic SOJ
IS61LV256-15TI
IS61LV256-15JI
TSOP - Type I
300-mil Plastic SOJ
IS61LV256-15T
IS61LV256-15J
TSOP - Type I
300-mil Plastic SOJ
IS61LV256-20TI
IS61LV256-20JI
TSOP - Type I
300-mil Plastic SOJ
IS61LV256-15T
IS61LV256-20J
TSOP - Type I
300-mil Plastic SOJ
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. I
11/09/99
相关型号:
IS61LV256-12JL
Standard SRAM, 32KX8, 12ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, PLASTIC, SOJ-28
ISSI
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