IS61LV256-12J [ICSI]
32K X 8 LOW VOLTAGE CMOS STATIC RAM; 32K ×8低压CMOS静态RAM
| 型号： | IS61LV256-12J |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 32K X 8 LOW VOLTAGE CMOS STATIC RAM |
| 文件： | 总8页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61LV256
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
ꢀEATURES
DESCRIPTION
The ICSI IS61LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using ICSI's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 8 ns maximum.
High-speed access times:
-- 8, 10, 12, 15, 20 ns
Automatic power-down when chip is deselected
CMOS low power operation
-- 345 mW (max.) operating
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.
-- 7 mW (max.) CMOS standby
TTL compatible interface levels
Single 3.3V power supply
Easy memory expansion is provided by using an active LOW
Chip Enable (CE). The active LOW Write Enable (WE) controls
both writing and reading of the memory.
ꢀully static operation: no clock or refresh
required
Three-state outputs
The IS61LV256 is available in the JEDEC standard 28-pin,
300mil SOJ and the 8*13.4mm TSOP-1 package.
ꢀUNCTIONAL BLOCK DIAGRAM
256 X 1024
MEMORY ARRAY
A0-A14
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SR004-0D
1
IS61LV256
PIN CONꢀIGURATION
28-Pin SOJ
PIN CONꢀIGURATION
8x13.4mm TSOP-1
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
OE
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CE
2
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A6
4
A8
A5
5
A9
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A4
6
A11
OE
A3
7
A2
8
A10
CE
2
A1
9
3
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
4
I/O0
I/O1
I/O2
GND
5
6
A1
A2
7
8
TRUTH TABLE
PIN DESCRIPTIONS
Mode
WE CE
OE
I/O Operation Vcc Current
A0-A14
CE
Address Inputs
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
Chip Enable Input
Output Enable Input
Write Enable Input
Input/Output
OE
Output Disabled
Read
H
H
L
L
L
L
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
WE
I/O0-I/O7
Vcc
Write
X
Power
GND
Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
VCC
Power Supply Voltage Relative to GND
Terminal Voltage with Respect to GND
Temperature Under Bias
0.5 to +4.6
0.5 to +4.6
VTERM
TBIAS
V
Com.
Ind.
10 to +85
45 to +90
°C
TSTG
PD
Storage Temperature
Power Dissipation
DC Output Current
65 to +150
°C
W
1
IOUT
±20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2
Integrated Circuit Solution Inc.
SR004-0D
IS61LV256
OPERATING RANGE
Range
Ambient Temperature
Speed
VCC
Commercial
0°C to +70°C
8, 10, 12
15, 20
3.3V, +10%, 5%
3.3V ± 10%
Industrial
40°C to +85°C
All
3.3V + 10%, 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = 4.0 mA
VCC = Min., IOL = 8.0 mA
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
0.4
V
2.2
VCC + 0.3
0.8
V
0.3
V
GND ≤ VIN ≤ VCC
Com.
Ind.
1
5
1
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
Com.
Ind.
1
5
1
5
µA
Notes:
1. VIL (min.) = 0.3V (DC); VIL (min.) = 2.0V (pulse width ≤ 2.0 ns).
VIH (max.) = VCC + 0.5V (DC); VIH (max.) = Vcc + 2.0V (pulse width ≤ 2.0 ns).
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
-10 ns
-12 ns
-15 ns
-20 ns
Sym. Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
Vcc Dynamic Operating
Supply Current
V
CC = Max., CE = VIL
Com.
Ind.
120
130
110
120
100
110
90
80
90
mA
IOUT = 0 mA, f = fMAX
100
I
SB
1
TTL Standby Current
(TTL Inputs)
V
CC = Max.,
Com.
Ind.
25
30
25
30
25
30
25
30
25
30
mA
mA
VIN = VIH or VIL
CE
≥ VIH, f = 0
ISB
2
CMOS Standby
V
CC = Max.,
CE CC 0.2V,
IN > VCC 0.2V, or
0.2V, f = 0
Com.
Ind.
2
5
2
5
2
5
2
5
2
5
Current (CMOS Inputs)
≤ V
V
V
IN
≤
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pꢀ
Input Capacitance
Output Capacitance
6
5
COUT
VOUT = 0V
pꢀ
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Circuit Solution Inc.
SR004-0D
3
IS61LV256
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns
-10 ns
-12 ns
-15 ns
-20 ns
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
8
2
8
10
2
10
10
5
12
2
12
12
6
15
2
15
15
7
20
2
20
20
8
tAA
Address Access Time
Output Hold Time
CE Access Time
tOHA
tACE
tDOE
tLZOE
8
0
0
0
0
0
OE Access Time
4
(2)
(2)
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE to Power-Up
4
5
5
6
6
tHZOE
3
3
3
3
3
(2)
tLZCE
tHZCE
4
5
6
7
7
(2)
0
0
0
0
0
(3)
tPU
8
10
12
15
20
(4)
tPD
CE to Power-Down
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in ꢀigure 1.
2. Tested with the load in ꢀigure 2. Transition is measured ±200 mV from steady-state voltage. Not 100%
tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and ꢀall Times
Input and Output Timing
and Reference Levels
1.5V
Output Load
See ꢀigures 1 and 2
AC TEST LOADS
319 Ω
319 Ω
3.3V
3.3V
OUTPUT
OUTPUT
353 Ω
353 Ω
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
'igure 1.
'igure 2.
4
Integrated Circuit Solution Inc.
SR004-0D
IS61LV256
AC WAVEꢀORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Circuit Solution Inc.
SR004-0D
5
IS61LV256
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-8 ns
-10 ns
-12 ns
-15 ns
-20 ns
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
ns
tWC
tSCE
tAW
Write Cycle Time
8
7
7
10
8
12
8
15
10
10
20
12
12
CE to Write End
ns
Address Setup Time
to Write End
8
8
ns
tHA
Address Hold
0
0
0
0
0
ns
from Write End
tSA
Address Setup Time
0
7
3.5
0
10
7
4
0
12
8
6
0
15
10
7
7
0
20
12
10
0
7
ns
ns
ns
ns
ns
ns
ns
tPWE1
tPWE2
tSD
WE Pulse Width(OE High)
WE Pulse Width(OE Low)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
6.5
4.5
0
5
6
tHD
0
0
0
(3)
tHZWE
0
0
0
0
0
(3)
tLZWE
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in ꢀigure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
3. Tested with the load in ꢀigure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
AC WAVEꢀORMS
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 )
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
t
PWE1
PWE2
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
6
Integrated Circuit Solution Inc.
SR004-0D
IS61LV256
WRITE CYCLE NO. 2(WE Controlled, OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
WRITE CYCLE NO. 3(WE Controlled, OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
Integrated Circuit Solution Inc.
SR004-0D
7
IS61LV256
ORDERING INꢀORMATION
ORDERING INꢀORMATION
Commercial Range: 0°C to +70°C
Industrial Range: 40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns)
Order Part No.
Package
8
IS61LV256-8T
IS61LV256-8J
8*13.4mm TSOP-1
300mil SOJ
8
IS61LV256-8TI
IS61LV256-8JI
8*13.4mm TSOP-1
300mil SOJ
10
12
15
20
IS61LV256-10T
IS61LV256-10J
8*13.4mm TSOP-1
300mil SOJ
10
12
15
20
IS61LV256-10TI
IS61LV256-10JI
8*13.4mm TSOP-1
300mil SOJ
IS61LV256-12T
IS61LV256-12J
8*13.4mm TSOP-1
300mil SOJ
IS61LV256-12TI
IS61LV256-12JI
8*13.4mm TSOP-1
300mil SOJ
IS61LV256-15T
IS61LV256-15J
8*13.4mm TSOP-1
300mil SOJ
IS61LV256-15TI
IS61LV256-15JI
8*13.4mm TSOP-1
300mil SOJ
IS61LV256-15T
IS61LV256-20J
8*13.4mm TSOP-1
300mil SOJ
IS61LV256-20TI
IS61LV256-20JI
8*13.4mm TSOP-1
300mil SOJ
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
"ax: 886-3-5783000
BRANCH O""ICE:
7", NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
"AX: 886-2-26962252
http://www.icsi.com.tw
8
Integrated Circuit Solution Inc.
SR004-0D
相关型号：
IS61LV256-12JL
Standard SRAM, 32KX8, 12ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, PLASTIC, SOJ-28
ISSI
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