IS61LV256-12JL [ISSI]

Standard SRAM, 32KX8, 12ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, PLASTIC, SOJ-28;
IS61LV256-12JL
型号: IS61LV256-12JL
厂家: INTEGRATED SILICON SOLUTION, INC    INTEGRATED SILICON SOLUTION, INC
描述:

Standard SRAM, 32KX8, 12ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, PLASTIC, SOJ-28

静态存储器 光电二极管 内存集成电路
文件: 总11页 (文件大小:75K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
®
IS61LV256  
32K x 8 LOW VOLTAGE  
CMOS STATIC RAM  
ISSI  
June 2005  
DESCRIPTION  
FEATURES  
The ISSI IS61LV256 is a very high-speed, low power,  
32,768-word by 8-bit static RAM. It is fabricated using  
ISSI's high-performance CMOS technology. This highly  
reliable process coupled with innovative circuit design  
techniques, yields access times as fast as 8 ns maximum.  
• High-speed access times:  
-- 8, 10, 12, 15 ns  
• Automatic power-down when chip is deselected  
• CMOS low power operation  
-- 345 mW (max.) operating  
When CE is HIGH (deselected), the device assumes a  
standbymodeatwhichthepowerdissipationisreducedto  
50 µW (typical) with CMOS input levels.  
-- 7 mW (max.) CMOS standby  
• TTL compatible interface levels  
• Single 3.3V power supply  
Easy memory expansion is provided by using an active  
LOW Chip Enable (CE). The active LOW Write Enable  
(WE) controls both writing and reading of the memory.  
• Fully static operation: no clock or refresh  
required  
• Three-state outputs  
• Lead-free Available  
TheIS61LV256isavailableintheJEDECstandard28-pin,  
300-mil SOJ and the 450-mil TSOP (Type I) packages.  
FUNCTIONAL BLOCK DIAGRAM  
32K X 8  
MEMORY ARRAY  
A0-A14  
DECODER  
VDD  
GND  
I/O  
DATA  
COLUMN I/O  
I/O0-I/O7  
CIRCUIT  
CE  
CONTROL  
CIRCUIT  
OE  
WE  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying  
on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. K  
1
06/06/05  
®
IS61LV256  
ISSI  
PIN CONFIGURATION  
28-Pin SOJ  
PIN CONFIGURATION  
28-Pin TSOP (Type I)  
A14  
A12  
A7  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VDD  
WE  
A13  
A8  
OE  
A11  
A9  
22  
23  
24  
25  
26  
27  
28  
1
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
A10  
CE  
2
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
GND  
I/O2  
I/O1  
I/O0  
A0  
3
A8  
A6  
4
A13  
WE  
VDD  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A5  
5
A9  
A4  
6
A11  
OE  
A3  
7
A2  
8
A10  
CE  
2
A1  
9
3
A0  
10  
11  
12  
13  
14  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
4
I/O0  
I/O1  
I/O2  
GND  
5
6
A1  
A2  
7
8
TRUTH TABLE  
PIN DESCRIPTIONS  
Mode  
WE CE  
OE  
I/OOperation VDD Current  
A0-A14  
CE  
Address Inputs  
Chip Enable Input  
Not Selected  
(Power-down)  
X
H
X
High-Z  
ISB1, ISB2  
OE  
Output Enable Input  
Write Enable Input  
Input/Output  
Power  
OutputDisabled  
Read  
H
H
L
L
L
L
H
L
High-Z  
DOUT  
DIN  
ICC  
ICC  
ICC  
WE  
I/O0-I/O7  
VDD  
Write  
X
GND  
Ground  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol Parameter  
Value  
Unit  
V
VDD  
Power Supply Voltage Relative to GND  
Terminal Voltage with Respect to GND  
StorageTemperature  
–0.5 to +4.6  
–0.5 to +4.6  
–65 to +150  
1
VTERM  
TSTG  
PD  
V
°C  
W
PowerDissipation  
IOUT  
DCOutputCurrent  
±20  
mA  
Notes:  
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent  
damage to the device. This is a stress rating only and functional operation of the device at these or any  
other conditions above those indicated in the operational sections of this specification is not implied.  
Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
2
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. K  
06/06/05  
®
IS61LV256  
ISSI  
OPERATING RANGE  
Range  
AmbientTemperature  
Speed(ns)  
VDD  
Commercial  
0°C to +70°C  
8,10,12  
15  
3.3V, +10%, –5%  
3.3V ± 10%  
Industrial  
–40°Cto+85°C  
10,12  
3.3V + 10%, –5%  
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)  
Symbol Parameter  
TestConditions  
Min.  
Max.  
Unit  
V
VOH  
VOL  
VIH  
VIL  
ILI  
OutputHIGHVoltage  
VDD = Min., IOH = –2.0 mA  
VDD = Min., IOL = 4.0 mA  
2.4  
0.4  
OutputLOWVoltage  
Input HIGH Voltage  
Input LOW Voltage(1)  
InputLeakage  
V
2.2  
–0.3  
VDD + 0.3  
0.8  
V
V
GND VIN VDD  
Com.  
Ind.  
–1  
–5  
1
5
µA  
ILO  
OutputLeakage  
GND VOUT VDD, Outputs Disabled  
Com.  
Ind.  
–1  
–5  
1
5
µA  
Notes:  
1. VIL (min.) = –0.3V (DC); VIL (min.) = –2.0V (pulse width 2.0 ns).  
VIH (max.) = VDD + 0.5V (DC); VIH (max.) = VDD + 2.0V (pulse width 2.0 ns).  
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.  
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)  
-8 ns  
-10ns  
-12ns  
-15ns  
Sym. Parameter  
DD DynamicOperating  
TestConditions  
DD = Max., CE = VIL  
OUT = 0 mA, f = fMAX  
Min.Max.  
Min.Max.  
Min.Max.  
Min.Max.  
Unit  
ICC  
V
V
I
Com.  
Ind.  
120  
110  
120  
100  
110  
90  
100  
mA  
SupplyCurrent  
I
SB  
1
TTLStandbyCurrent  
(TTL Inputs)  
V
DD = Max.,  
Com.  
Ind.  
15  
10  
20  
10  
20  
10  
20  
mA  
mA  
VIN = VIH or VIL  
CE VIH, f = 0  
DD = Max.,  
CE DD – 0.2V,  
IN VDD – 0.2V, or  
0.2V, f = 0  
ISB  
2
CMOSStandby  
Current(CMOSInputs)  
V
Com.  
Ind.  
2
2
5
2
5
2
5
V
V
V
IN  
Notes:  
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.  
CAPACITANCE(1,2)  
Symbol  
CIN  
Parameter  
Conditions  
VIN = 0V  
Max.  
Unit  
pF  
InputCapacitance  
OutputCapacitance  
6
5
COUT  
VOUT = 0V  
pF  
Notes:  
1. Tested initially and after any design or process changes that may affect these parameters.  
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. K  
3
06/06/05  
®
IS61LV256  
ISSI  
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)  
-8 ns  
-10 ns  
-12 ns  
-15 ns  
Symbol Parameter  
Min. Max.  
Min. Max.  
Min. Max.  
Min. Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tRC  
Read Cycle Time  
8
2
8
10  
2
10  
10  
5
12  
2
12  
12  
6
15  
2
15  
15  
7
tAA  
Address Access Time  
Output Hold Time  
CE Access Time  
tOHA  
tACE  
tDOE  
tLZOE  
8
0
0
0
0
OE Access Time  
4
(2)  
(2)  
OE to Low-Z Output  
OE to High-Z Output  
CE to Low-Z Output  
CE to High-Z Output  
CE to Power-Up  
4
5
5
6
tHZOE  
3
3
3
3
(2)  
tLZCE  
tHZCE  
4
5
6
7
(2)  
0
0
0
0
(3)  
tPU  
8
10  
12  
15  
(3)  
tPD  
CE to Power-Down  
Notes:  
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse  
levels of 0 to 3.0V and output loading specified in Figure 1.  
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100%  
tested.  
3. Not 100% tested.  
AC TEST CONDITIONS  
Parameter  
Unit  
0V to 3.0V  
3 ns  
Input Pulse Level  
Input Rise and Fall Times  
Input and Output Timing  
and Reference Levels  
1.5V  
Output Load  
See Figures 1 and 2  
AC TEST LOADS  
319 Ω  
319 Ω  
3.3V  
3.3V  
OUTPUT  
OUTPUT  
353 Ω  
353 Ω  
5 pF  
30 pF  
Including  
jig and  
Including  
jig and  
scope  
scope  
Figure 1.  
Figure 2.  
4
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. K  
06/06/05  
®
IS61LV256  
ISSI  
AC WAVEFORMS  
READ CYCLE NO. 1(1,2)  
t
RC  
ADDRESS  
t
AA  
t
OHA  
t
OHA  
DATA VALID  
DOUT  
PREVIOUS DATA VALID  
READ1.eps  
READ CYCLE NO. 2(1,3)  
t
RC  
ADDRESS  
OE  
t
AA  
t
OHA  
t
HZOE  
t
DOE  
t
t
LZOE  
ACE  
CE  
t
HZCE  
t
LZCE  
HIGH-Z  
DOUT  
DATA VALID  
CE_RD2.eps  
Notes:  
1. WE is HIGH for a Read Cycle.  
2. The device is continuously selected. OE, CE = VIL.  
3. Address is valid prior to or coincident with CE LOW transitions.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. K  
5
06/06/05  
®
IS61LV256  
ISSI  
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)  
-8 ns  
-10 ns  
-12 ns  
-15 ns  
Symbol Parameter  
Min. Max.  
Min. Max.  
Min. Max.  
Min. Max.  
Unit  
ns  
tWC  
tSCE  
tAW  
Write Cycle Time  
8
10  
8
12  
8
15  
10  
10  
CE to Write End  
6.5  
6.5  
ns  
Address Setup Time  
to Write End  
8
8
ns  
tHA  
Address Hold  
from Write End  
0
0
0
0
0
ns  
tSA  
Address Setup Time  
3.5  
0
7
4
0
8
6
0
10  
15  
7
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPWE1  
tPWE2  
tSD  
WE Pulse Width (OE HIGH) 6.5  
WE Pulse Width (OE LOW)  
Data Setup to Write End  
Data Hold from Write End  
WE LOW to High-Z Output  
WE HIGH to Low-Z Output  
8
5
10  
5
12  
6
tHD  
0
0
0
0
(3)  
tHZWE  
0
0
0
0
(3)  
tLZWE  
Notes:  
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse  
levels of 0 to 3.0V and output loading specified in Figure 1.  
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states  
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing  
are referenced to the rising or falling edge of the signal that terminates the Write.  
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%  
tested.  
AC WAVEFORMS  
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 )  
t
WC  
VALID ADDRESS  
SCE  
ADDRESS  
t
SA  
t
t
HA  
CE  
t
AW  
t
tPPWWEE21  
WE  
t
HZWE  
t
LZWE  
HIGH-Z  
DATA UNDEFINED  
DOUT  
t
SD  
t
HD  
DATAIN VALID  
DIN  
CE_WR1.eps  
6
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. K  
06/06/05  
®
IS61LV256  
ISSI  
WRITE CYCLE NO. 2(WE Controlled, OE is HIGH During Write Cycle) (1,2)  
tWC  
ADDRESS  
VALID ADDRESS  
tHA  
OE  
LOW  
CE  
tAW  
tPWE1  
WE  
tSA  
tHZWE  
tLZWE  
HIGH-Z  
DATA UNDEFINED  
DOUT  
tSD  
tHD  
DATAIN VALID  
DIN  
CE_WR2.eps  
WRITE CYCLE NO. 3(WE Controlled, OE is LOW During Write Cycle) (1)  
t
WC  
ADDRESS  
VALID ADDRESS  
t
HA  
LOW  
LOW  
OE  
CE  
t
t
AW  
t
PWE2  
WE  
t
SA  
HZWE  
t
LZWE  
HIGH-Z  
DATA UNDEFINED  
DOUT  
t
SD  
t
HD  
DATAIN VALID  
DIN  
CE_WR3.eps  
Notes:  
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,  
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling  
edge of the signal that terminates the Write.  
2. I/O will assume the High-Z state if OE > VIH.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. K  
7
06/06/05  
®
IS61LV256  
ISSI  
ORDERING INFORMATION  
Commercial Range: 0°C to +70°C  
Speed (ns) Order Part No.  
Package  
8
IS61LV256-8T  
IS61LV256-8J  
IS61LV256-8JL  
TSOP - Type I  
300-mil Plastic SOJ  
300-mil Plastic SOJ, Lead-free  
10  
12  
15  
IS61LV256-10T  
IS61LV256-10TL TSOP - Type I, Lead-free  
IS61LV256-10J  
TSOP - Type I  
300-mil Plastic SOJ  
IS61LV256-12T  
IS61LV256-12J  
IS61LV256-12JL  
TSOP - Type I  
300-mil Plastic SOJ  
300-mil Plastic SOJ, Lead free  
IS61LV256-15T  
IS61LV256-15TL  
IS61LV256-15J  
IS61LV256-15JL  
TSOP - Type I  
TSOP - Type I, Lead free  
300-mil Plastic SOJ  
300-mil Plastic SOJ, Lead free  
ORDERING INFORMATION  
Industrial Range: –40°C to +85°C  
Speed (ns) Order Part No.  
Package  
10  
IS61LV256-10TI  
IS61LV256-10JI  
TSOP - Type I  
300-mil Plastic SOJ  
12  
IS61LV256-12TI  
TSOP - Type I  
IS61LV256-12TLI TSOP - Type I, Lead-free  
IS61LV256-12JI 300-mil Plastic SOJ  
IS61LV256-12JLI 300-mil Plastic SOJ, Lead-free  
8
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. K  
06/06/05  
®
PACKAGING INFORMATION  
300-mil Plastic SOJ  
Package Code: J  
ISSI  
N
E1  
E
1
SEATING PLANE  
D
A
A2  
B
C
e
b
A1  
E2  
Notes:  
1. Controlling dimension: inches, unless otherwise  
specified.  
2. BSC = Basic lead spacing between centers.  
3. Dimensions D and E1 do not include mold flash  
protrusionsandshouldbemeasuredfromthebottomof  
MILLIMETERS  
INCHES  
Min. Typ. Max.  
Sym. Min. Typ. Max.  
N0.  
thepackage  
.
4. Formed leads shall be planar with respect to one  
another within 0.004 inches at the seating plane.  
Leads  
24/26  
A
3.56  
0.140  
A1  
A2  
b
0.64  
2.41  
0.41  
0.66  
0.20  
17.02  
8.26  
7.49  
6.27  
0.025  
0.095  
0.016  
0.026  
0.008  
0.670  
0.325  
0.295  
0.247  
2.67  
0.51  
0.81  
0.25  
17.27  
8.76  
7.75  
7.29  
0.105  
0.020  
0.032  
0.010  
0.680  
0.345  
0.305  
0.287  
B
C
D
E
E1  
E2  
e
1.27 BSC  
0.050 BSC  
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev. D  
02/25/03  
®
PACKAGING INFORMATION  
300-mil Plastic SOJ  
Package Code: J  
ISSI  
MILLIMETERS  
INCHES  
MILLIMETERS  
INCHES  
Sym. Min. Typ. Max.  
Min. Typ. Max.  
Sym. Min. Typ. Max.  
Min. Typ. Max.  
N0.  
N0.  
Leads  
28  
Leads  
32  
A
3.56  
0.140  
A
3.56  
0.140  
A1  
A2  
b
0.64  
2.41  
0.41  
0.66  
0.20  
18.29  
8.26  
7.49  
6.27  
0.025  
0.095  
0.016  
0.026  
0.008  
0.720  
0.325  
0.295  
0.247  
A1  
A2  
b
0.64  
2.41  
0.41  
0.66  
0.20  
20.83  
8.26  
7.49  
6.27  
0.025  
0.095  
0.016  
0.026  
0.008  
0.820  
0.325  
0.295  
0.247  
2.67  
0.51  
0.81  
0.25  
18.54  
8.76  
7.75  
7.29  
0.105  
0.020  
0.032  
0.010  
0.730  
0.345  
0.305  
0.287  
2.67  
0.51  
0.81  
0.25  
21.08  
8.76  
7.75  
7.29  
0.105  
0.020  
0.032  
0.010  
0.830  
0.345  
0.305  
0.287  
B
B
C
C
D
D
E
E
E1  
E2  
e
E1  
E2  
e
1.27 BSC  
0.050 BSC  
1.27 BSC  
0.050 BSC  
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev.D  
02/25/03  
®
PACKAGINGINFORMATION  
ISSI  
Plastic TSOP - 28-pins  
Package Code: T (Type I)  
1
E
H
N
D
SEATING PLANE  
A
S
L
α
e
B
C
A1  
Plastic TSOP (T—Type I)  
Millimeters  
Inches  
Symbol  
Min  
Max  
Min  
Max  
Ref. Std.  
No. Leads  
Notes:  
28  
1. Controlling dimension: millimeters, unless otherwise specified.  
2. BSC = Basic lead spacing between centers.  
3. Dimensions D and E do not include mold flash protrusions and  
should be measured from the bottom of the package  
4. Formed leads shall be planar with respect to one another within  
0.004 inches at the seating plane.  
A
A1  
B
C
D
E
H
e
1.00  
0.05  
0.16  
1.20  
0.20  
0.27  
0.037  
0.002  
0.006  
0.004  
0.308  
0.456  
0.515  
0.047  
0.008  
0.011  
0.008  
0.316  
0.465  
0.531  
.
0.10  
0.20  
7.90  
11.70  
13.20  
8.10  
11.90  
13.60  
0.55 BSC  
0.022 BSC  
L
0.30  
0.70  
0.011  
0.027  
α
0°  
5°  
0°  
5°  
Integrated Silicon Solution, Inc.  
1
PK13197T28 Rev. B 01/31/97  

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ISSI

IS61LV256-15J

32K X 8 LOW VOLTAGE CMOS STATIC RAM
ICSI

IS61LV256-15JI

32K X 8 LOW VOLTAGE CMOS STATIC RAM
ICSI

IS61LV256-15JL

Standard SRAM, 32KX8, 15ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, PLASTIC, SOJ-28
ISSI

IS61LV256-15N

32K x 8 LOW VOLTAGE CMOS STATIC RAM
ISSI