IS61LV12816-8TI [ISSI]
128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY; 128K ×16高速CMOS静态RAM与3.3V电源
| 型号： | IS61LV12816-8TI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY |
| 文件： | 总11页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61LV12816
128K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
ISSI
NOVEMBER 2000
FEATURES
DESCRIPTION
The ISSI IS61LV12816 is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words bꢂ 16 bits. It is fabricated
ꢁsingISSI'shigh-performanceCMOStechnologꢂ. Thishighlꢂ
reliable process coꢁpled with innovative circꢁit design
techniqꢁes, ꢂields access times as fast as 8 ns with low power
consꢁmption.
• High-speed access time: 8, 10, 12, and 15 ns
• CMOS low power operation
• TTL and CMOS compatible interface levels
• Single 3.3V 10ꢀ power sꢁpplꢂ
• Fꢁllꢂ static operation: no clock or refresh
reqꢁired
When CE is HIGH (deselected), the device assꢁmes a
standbꢂ mode at which the power dissipation can be redꢁced
down with CMOS inpꢁt levels.
• Three state oꢁtpꢁts
• Data control for ꢁpper and lower bꢂtes
• Indꢁstrial temperatꢁre available
EasꢂmemorꢂexpansionisprovidedbꢂꢁsingChipEnableand
Oꢁtpꢁt Enable inpꢁts, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memorꢂ.
A data bꢂte allows Upper Bꢂte (UB) and Lower Bꢂte (LB)
access.
The IS61LV12816 is packaged in the JEDEC standard 44-pin
400-mil SOJ, 44-pin TSOP, 44-pin LQFP, and 48-pin mini
BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
128K x 16
MEMORY ARRAY
A0-A16
DECODER
VCC
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
ISSI reserves the right to make changes to its prodꢁcts at anꢂ time withoꢁt notice in order to improve design and sꢁpplꢂ the best possible prodꢁct. We assꢁme no responsibilitꢂ for anꢂ errors
which maꢂ appear in this pꢁblication. © Copꢂright 2000, Integrated Silicon Solꢁtion, Inc.
Integrated Silicon Solution, Inc. — 11--880000--337799--44777744
1
Rev. A
11/30/00
®
ISSI
IS61LV12816
PIN CONFIGURATIONS
44-Pin SOJ (K)
44-Pin TSOP (T)
A4
A3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
2
A6
A2
3
A7
A1
4
OE
A0
5
UB
CE
CE
6
LB
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
19
20
21
22
A8
A9
A10
A11
NC
48-Pin mini BGA (B)
44-Pin LQFP (LQ)
1
2
3
4
5
6
44 43 42 41 40 39 38 37 36 35 345
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
A0
A3
A1
A4
A2
LB
I/O
OE
UB
N/C
A
B
C
D
E
F
CE
I/O
0
8
I/O
I/O
A5
A6
I/O
1
I/O
2
9
10
TOP VIEW
GND
Vcc
NC
NC
A14
A12
A7
I/O
I/O
I/O
I/O
I/O
Vcc
11
3
4
5
GND
A16
A15
A13
A10
12
I/O
14
I/O
I/O
6
13
9
I/O
15
NC
A8
WE
I/O
7
10
11
G
H
I/O8
NC
NC
A9
A11
NC
12 13 14 15 16 17 18 19 20 21 22
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/30/00
®
ISSI
IS61LV12816
OPERATING RANGE
PIN DESCRIPTIONS
Range
Commercial
Industrial
Ambient Temperature
VCC
3.3V 10ꢀ
3.3V 10ꢀ
A0-A16
I/O0-I/O15
CE
Address Inputs
0°C to + 70°C
–40°C to + 85°C
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
OE
WE
LB
UB
NC
Vcc
Power
GND
Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCC
Parameter
Value
–0.5 to 5.0
–0.5 to Vcc + 0.5
–65 to + 150
Unit
V
V
Power Supply Voltage Relative to GND
Terminal Voltage with Respect to GND
Storage Temperature
VTERM
TSTG
°C
TBIAS
Temperature Under Bias:
Com.
Ind.
–10 to + 85
–45 to + 90
°C
°C
PT
Power Dissipation
DC Output Current
2.0
20
W
mA
IOUT
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
—
Max.
Unit
V
VOH
VOL
VIH
VIL
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
—
Output LOW Voltage
Input HIGH Voltage(1)
Input LOW Voltage(1)
Input Leakage
0.4
V
2
VCC + 0.3
V
–0.3
–1
0.8
1
V
ILI
GND - VIN - VCC
µA
µA
ILO
Output Leakage
GND - VOUT - VCC, Outputs Disabled
–1
1
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns).
VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width - 2.0 ns).
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. A
11/30/00
®
ISSI
IS61LV12816
TRUTH TABLE
Mode
I/O PIN
WE
CE
OE
LB
UB
I/O0-I/O7
I/O8-I/O15 Vcc Current
Not Selected
Output Disabled
X
H
X
H
L
L
X
H
X
X
X
H
X
X
H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
ISB1, ISB2
ICC
Read
Write
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
L
H
L
L
H
L
H
L
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
ICC
DIN
High-Z
DIN
High-Z
DIN
DIN
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
Symbol
Parameter
Test Conditions
Unit
ICC
Vcc Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = Max.
Com.
Ind.
—
—
150
160
—
—
125
135
—
—
110
120
—
—
90
100
mA
ISB1
ISB2
TTL Standby
Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE • VIH, f = max
Com.
Ind.
—
—
50
60
—
—
40
50
—
—
35
45
—
—
30
40
mA
CMOS Standby
Current
(CMOS Inputs)
VCC = Max.,
Com.
Ind.
—
—
10
20
—
—
10
20
—
—
10
20
—
—
10
20
mA
CE - VCC – 0.2V,
VIN > VCC – 0.2V, or
VIN - 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/30/00
®
ISSI
IS61LV12816
CAPACITANCE(1)
Symbol
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
CIN
Input Capacitance
6
8
COUT
Note:
Input/Output Capacitance
VOUT = 0V
pF
1. Tested initially and after any design or process changes that may affect these parameters.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Min.
-10 ns
Min.
-12 ns
Min.
-15 ns
Min.
Symbol Parameter
Max
—
8
Max.
—
10
—
10
4
Max.
—
12
—
12
5
Max.
—
15
—
15
6
Unit
tRC
Read Cycle Time
8
—
3
10
—
3
12
—
3
15
—
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
Output Hold Time
tOHA
tACE
tDOE
tHZOE
—
—
3
CE Access Time
8
—
—
—
0
—
—
—
0
—
—
0
OE Access Time
—
—
0
(2)
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
3
4
5
6
(2)
(2)
tLZOE
—
3
—
4
—
5
0
—
8
tHZCE
0
0
0
0
(2)
tLZCE
3
—
3
3
—
4
3
—
5
3
—
6
tBA
—
0
—
0
—
0
—
0
(2)
tHZB
3
4
5
6
(2)
tLZB
0
—
0
—
0
—
0
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels
of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100ꢀ tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
3 ns
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
319 Ω
319 Ω
3.3V
3.3V
OUTPUT
OUTPUT
353 Ω
353 Ω
5 pF
30 pF
Including
jig and
scope
Including
jig and
scope
Figure 1.
Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. A
11/30/00
®
ISSI
IS61LV12816
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
D
OUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
LB, UB
t
BA
t
HZB
t
LZB
HIGH-Z
D
OUT
DATA VALID
UB_CEDR2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/30/00
®
ISSI
IS61LV12816
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 ns
Min.
-10 ns
-12 ns
Min.
-15 ns
Min.
Symbol Parameter
Max
—
Min.
Max.
Max.
—
Max.
—
Unit
ns
tWC
tSCE
tAW
Write Cycle Time
8
10
8
—
12
8
15
10
10
CE to Write End
6.5
6.5
—
—
—
—
ns
Address Setup Time
to Write End
—
8
—
8
—
—
ns
tHA
Address Hold from Write End
Address Setup Time
0
0
—
—
—
—
—
—
—
3
0
0
—
—
—
—
—
—
—
4
0
0
—
—
—
—
—
—
—
5
0
0
—
—
—
—
—
—
—
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSA
tPWB
tPWE1
tPWE2
tSD
LB, UB Valid to End of Write
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
6.5
5
8
9
10
10
11
7
7
8
6.5
4
8
10
6
5
tHD
0
0
0
0
(3)
tHZWE
—
0
—
0
—
0
—
0
(3)
tLZWE
—
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V
to 3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing
are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100ꢀ tested.
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. A
11/30/00
®
ISSI
IS61LV12816
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
tPPWWEE21
WE
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
D
IN
UB_CEWR1.eps
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/30/00
®
ISSI
IS61LV12816
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
t
PBW
UB, LB
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR3.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. A
11/30/00
®
ISSI
IS61LV12816
WRITE CYCLE NO. 4(LB, UB Controlled, Back-to-Back Write) (1,3)
tWC
tWC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
tSA
LOW
tHA
tSA
tHA
WE
tPBW
tPBW
WORD 2
UB, LB
WORD 1
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
DOUT
tHD
tHD
tSD
tSD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/30/00
®
ISSI
IS61LV12816
IS61LV12816 STANDARD VERSION
ORDERING INFORMATION
IS61LV12816 STANDARD VERSION
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
8
IS61LV12816-8B
IS61LV12816-8K
IS61LV12816-8LQ
IS61LV12816-8T
mini BGA (6mm x 8mm)
400-mil Plastic SOJ
LQFP
8
IS61LV12816-8BI
IS61LV12816-8KI
IS61LV12816-8LQI
IS61LV12816-8TI
mini BGA (6mm x 8mm)
400-mil Plastic SOJ
LQFP
Plastic TSOP
Plastic TSOP
10
12
15
IS61LV12816-10B
IS61LV12816-10K
IS61LV12816-10LQ LQFP
mini BGA (6mm x 8mm)
400-mil Plastic SOJ
10
12
15
IS61LV12816-10BI
IS61LV12816-10KI
IS61LV12816-10LQI LQFP
mini BGA (6mm x 8mm)
400-mil Plastic SOJ
IS61LV12816-10T
Plastic TSOP
IS61LV12816-10TI
Plastic TSOP
IS61LV12816-12B
IS61LV12816-12K
IS61LV12816-12LQ LQFP
mini BGA (6mm x 8mm)
400-mil Plastic SOJ
IS61LV12816-12BI
IS61LV12816-12KI
IS61LV12816-12LQI LQFP
mini BGA (6mm x 8mm)
400-mil Plastic SOJ
IS61LV12816-12T
Plastic TSOP
IS61LV12816-12TI
Plastic TSOP
IS61LV12816-15B
IS61LV12816-15K
mini BGA (6mm x 8mm)
400-mil Plastic SOJ
IS61LV12816-15BI
IS61LV12816-15KI
mini BGA (6mm x 8mm)
400-mil Plastic SOJ
IS61LV12816-15LQ LQFP
IS61LV12816-15T Plastic TSOP
IS61LV12816-15LQI LQFP
IS61LV12816-15TI Plastic TSOP
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
Rev. A
11/30/00
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