IS61LV12816L-10BI [ISSI]
128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY; 128K ×16高速CMOS静态RAM与3.3V电源
| 型号： | IS61LV12816L-10BI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 128K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY |
| 文件： | 总16页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61LV12816L
ISSI
128K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
OCTOBER2005
FEATURES
DESCRIPTION
The ISSI IS61LV12816L is a high-speed, 2,097,152-bit
static RAM organized as 131,072 words by 16 bits. It is
fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times
as fast as 8 ns with low power consumption.
• High-speed access time: 8, 10 ns
• Operating Current: 50mA (typ.)
• Stand by Current: 700µA (typ.)
• TTL and CMOS compatible interface levels
• Single 3.3V power supply
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
• Fully static operation: no clock or refresh
required
• Three state outputs
EasymemoryexpansionisprovidedbyusingChipEnable
and Output Enable inputs, CE and OE. The active LOW
WriteEnable(WE)controlsbothwritingandreadingofthe
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
The IS61LV12816L is packaged in the JEDEC standard
44-pinTSOP(TypeII),44-pinLQFP,and48-pinminiBGA
(6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
128Kx16
MEMORY ARRAY
A0-A16
DECODER
VDD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
CIRCUIT
COLUMN I/O
I/O8-I/O15
Upper Byte
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
1
10/27/05
®
ISSI
IS61LV12816L
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LB
UB
I/O0-I/O7
I/O8-I/O15
VDD Current
Not Selected
X
H
X
X
X
High-Z
High-Z
ISB1, ISB2
ICC
OutputDisabled
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
Read
Write
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
ICC
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
PIN CONFIGURATION
44-Pin TSOP (Type II) (T)
PIN DESCRIPTIONS
A0-A16
I/O0-I/O15
CE
Address Inputs
DataInputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
A4
A3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
2
A6
A2
3
A7
OE
A1
4
OE
A0
5
UB
WE
CE
6
LB
LB
Lower-byteControl(I/O0-I/O7)
Upper-byteControl(I/O8-I/O15)
NoConnection
I/O0
I/O1
I/O2
I/O3
7
I/O15
I/O14
I/O13
I/O12
GND
8
UB
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
V
DD
VDD
Power
GND
I/O4
I/O5
I/O6
I/O7
WE
VDD
I/O11
I/O10
I/O9
I/O8
NC
GND
Ground
A16
A15
A14
A13
A12
A8
A9
A10
A11
NC
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/27/05
®
IS61LV12816L
ISSI
PIN CONFIGURATION
48-Pin mini BGA (B)
44-Pin LQFP (LQ)
1
2
3
4
5
6
44 43 42 41 40 39 38 37 36 35 345
1
33
32
31
30
29
28
27
26
25
24
23
CE
I/O0
I/O1
I/O2
I/O3
I/O15
I/O14
I/O13
I/O12
GND
2
A0
A3
A1
A4
A2
LB
OE
UB
NC
I/O
A
B
C
D
E
F
3
4
I/O
CE
8
0
5
I/O
I/O
I/O
A5
A6
I/O
I/O
I/O
2
9
10
1
TOP VIEW
6
V
DD
VDD
GND
NC
NC
A14
A12
A7
7
V
DD
GND
I/O4
I/O5
I/O6
I/O7
I/O11
I/O10
I/O9
I/O8
NC
11
3
4
5
8
I/O
I/O
GND
V
DD
I/O
I/O
A16
A15
A13
A10
12
9
I/O
I/O
I/O
6
14
13
10
11
NC
A8
WE
I/O
7
15
G
H
12 13 14 15 16 17 18 19 20 21 22
NC
A9
A11
NC
PIN DESCRIPTIONS
A0-A16
I/O0-I/O15
CE
Address Inputs
DataInputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
OE
WE
LB
Lower-byteControl(I/O0-I/O7)
Upper-byteControl(I/O8-I/O15)
NoConnection
UB
NC
VDD
Power
GND
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
3
10/27/05
®
ISSI
IS61LV12816L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VDD
Parameter
Value
–0.5 to 4.0V
–0.5 to VDD + 0.5
–65 to + 150
1.0
Unit
V
Power Supply Voltage Relative to GND
Terminal Voltage with Respect to GND
StorageTemperature
VTERM
TSTG
PT
V
°C
W
PowerDissipation
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
OPERATING RANGE
Range
AmbientTemperature
0°C to +70°C
VDD (8 nS)
VDD (10 nS)
3.3V + 10%
3.3V + 10%
Commercial
Industrial
3.3V + 10%, -5%
3.3V + 10%, -5%
–40°Cto+85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
TestConditions
Min.
2.4
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
—
OutputLOWVoltage
InputHIGHVoltage(1)
InputLOWVoltage(1)
InputLeakage
0.4
V
2
VDD + 0.3
V
–0.3
–1
0.8
1
V
GND ≤ VIN ≤ VDD
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
Note:
1.
VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/27/05
®
IS61LV12816L
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Min. Max.
-10 ns
Min. Max.
Symbol
Parameter
Test Conditions
Unit
ICC
VDD Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = Max.
Com.
Ind.
—
—
—
65
70
50
—
—
—
60
65
50
mA
typ.(2)
ISB1
TTL Standby
Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = max
Com.
Ind.
—
—
30
35
—
—
25
30
mA
ISB2
CMOS Standby
Current
(CMOS Inputs)
VDD = Max.,
CE ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
Com.
Ind.
—
—
—
3
4
700
—
—
—
3
4
700
mA
mA
µA
typ.(2)
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=3.3V, TA=25oC. Not 100% tested.
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
Input/OutputCapacitance
6
8
COUT
VOUT = 0V
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
5
10/27/05
®
ISSI
IS61LV12816L
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
1.5V
OutputLoad
See Figures 1 and 2
AC TEST LOADS
319 Ω
3.3V
ZO = 50Ω
50Ω
1.5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
Figure 1.
Figure 2.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns
-10 ns
Symbol
tRC
Parameter
Min.
Max
—
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
8
—
3
10
—
3
—
10
—
10
4
tAA
Address Access Time
Output Hold Time
8
tOHA
—
tACE
CE Access Time
—
—
—
0
8
—
—
—
0
tDOE
OE Access Time
3.5
3.5
—
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
4
(2)
tLZOE
—
4
(2)
tHZCE
0
3.5
—
0
(2)
tLZCE
3.5
—
0
3
—
4
tBA
3.5
3.5
—
—
0
(2)
tHZB
4
(2)
tLZB
0
0
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/27/05
®
IS61LV12816L
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
LB, UB
t
BA
t
HZB
t
LZB
HIGH-Z
DOUT
DATA VALID
UB_CEDR2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
7
10/27/05
®
ISSI
IS61LV12816L
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 ns
-10 ns
Symbol
tWC
Parameter
Min. Max
Min. Max.
Unit
ns
Write Cycle Time
CE to Write End
8
7
7
—
—
—
10
8
—
—
—
tSCE
ns
tAW
Address Setup Time
to Write End
8
ns
tHA
Address Hold from Write End
Address Setup Time
0
0
—
—
—
—
—
—
—
3
0
0
—
—
—
—
—
—
—
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSA
tPBW
tPWE1
tPWE2
tSD
LB, UB Valid to End of Write
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
6.5
6
8
7
6.5
4
8
5
tHD
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
0
0
(3)
tHZWE
—
0
—
0
(3)
tLZWE
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/27/05
®
IS61LV12816L
ISSI
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
t
SA
t
t
HA
CE
t
AW
t
PWE1
PWE2
t
WE
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR1.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
9
10/27/05
®
ISSI
IS61LV12816L
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
t
PBW
UB, LB
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR3.eps
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/27/05
®
IS61LV12816L
ISSI
WRITE CYCLE NO. 4(LB, UB Controlled, Back-to-Back Write) (1,3)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
t
SA
LOW
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
11
10/27/05
®
ISSI
IS61LV12816L
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Test Condition
Options
Min.
Typ.(1)
Max.
Unit
V
VDD for Data Retention
Data Retention Current
See Data Retention Waveform
VDD = 2.0V, CE ≥ VDD – 0.2V
2.0
—
3.6
IDR
Com.
Ind.
—
—
0.7
—
3
4
mA
tSDR
tRDR
Data Retention Setup Time See Data Retention Waveform
0
—
—
—
—
ns
ns
Recovery Time
See Data Retention Waveform
tRC
O
Note 1: Typical values are measured at VDD = 3.3V, T
A
= 25 C. Not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
VDR
CE ≥ VDD - 0.2V
CE
GND
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/27/05
®
IS61LV12816L
ISSI
ORDERING INFORMATION:
Commercial Range: 0°C to +70°C
Speed(ns)
Order Part No.
Package
8
IS61LV12816L-8T
IS61LV12816L-8TL
Plastic TSOP (Type II)
Plastic TSOP (Type II), Lead-free
10
IS61LV12816L-10T
IS61LV12816L-10TL
Plastic TSOP (Type II)
Plastic TSOP (Type II), Lead-free
Industrial Range: –40°C to +85°C
Speed(ns)
Order Part No.
Package
8
IS61LV12816L-8BI
IS61LV12816L-8TI
mini BGA (6mm x 8mm)
Plastic TSOP (Type II)
10
IS61LV12816L-10BI
IS61LV12816L-10BLI
IS61LV12816L-10LQI
IS61LV12816L-10LQLI
IS61LV12816L-10TI
IS61LV12816L-10TLI
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
LQFP
LQFP,Lead-free
Plastic TSOP (Type II)
Plastic TSOP (Type II), Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
13
10/27/05
®
PACKAGING INFORMATION
ISSI
LQFP (Low Profile Quad Flat Pack)
Package Code: LQ (44-pin)
D
D1
E
E1
L1
θ
L
e
b
SEATING
PLANE
A2
A
A1
Notes:
Low Profile Quad Flat Pack (LQ)
1. All dimensioning and tolerancing
conforms to ANSI Y14.5M-1982.
2. Dimensions D1 and E1 do not include
mold protrusions. Allowable protrusion is
0.25 mm per side. D1 and E1 include
mold mismatch.
Ref. Std.
No. Leads
MS-026
44
Millimeters
Min Max
Inches
Symbol
Min
Max
3. Controlling dimension: millimeters.
A
A1
A2
b
—
1.60
0.15
1.45
0.45
0.20
—
0.063
0.006
0.057
0.018
0.008
0.05
1.35
0.30
0.09
0.002
0.053
0.012
0.004
C
D
12.00 BSC
0.472 BSC
D1
E
E1
e
10.00 BSC
12.00 BSC
10.00 BSC
0.80 BSC
0.394 BSC
0.472 BSC
0.394 BSC
0.031 BSC
L
0.45
1.00 REF.
0o 7o
0.75
0.018
0.039 REF.
0o 7o
0.030
L1
θ
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
05/30/03
®
PACKAGING INFORMATION
Mini Ball Grid Array
ISSI
Package Code: B (48-pin)
Top View
Bottom View
φ b (48x)
1
2
3
4
5 6
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
e
D
D1
G
H
G
H
e
E
E1
Notes:
1. Controllingdimensionsareinmillimeters.
A2
A
A1
SEATING PLANE
mBGA - 6mm x 8mm
mBGA - 8mm x 10mm
MILLIMETERS
INCHES
MILLIMETER
INCHES
Sym. Min. Typ. Max.
Min. Typ. Max.
Sym. Min. Typ. Max.
Min. Typ. Max.
N0.
N0.
Leads
48
Leads
48
A
—
—
—
—
—
1.20
0.30
—
—
—
—
—
—
0.047
0.012
—
A
—
—
—
—
—
1.20
0.30
—
—
—
—
—
—
0.047
0.012
—
A1
A2
D
0.24
0.60
7.90
0.009
0.024
0.311
A1
A2
D
0.24
0.60
9.90
0.009
0.024
0.390
8.10
0.319
10.10
0.398
D1
E
5.25 BSC
—
0.207 BSC
D1
E
5.25 BSC
—
0.207 BSC
5.90
6.10
0.232
—
0.240
7.90
8.10
0.311
—
0.319
E1
e
3.75 BSC
0.75 BSC
0.148 BSC
E1
e
3.75 BSC
0.75 BSC
0.148 BSC
0.030 BSC
0.030 BSC
b
0.30 0.35 0.40
0.012 0.014 0.016
b
0.30 0.35 0.40
0.012 0.014 0.016
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
®
PACKAGING INFORMATION
ISSI
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
E
E1
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
.
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Millimeters Inches
Millimeters
Inches
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Ref. Std.
No. Leads (N)
32
44
50
A
A1
b
C
D
E1
E
e
—
1.20
—
0.047
—
1.20
0.15
0.45
0.21
—
0.047
—
1.20
—
0.047
0.05 0.15
0.30 0.52
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
1.27 BSC
0.002 0.006
0.012 0.020
0.005 0.008
0.820 0.830
0.391 0.400
0.451 0.466
0.050 BSC
0.05
0.30
0.12
18.31 18.52
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.721 0.729
0.395 0.405
0.455 0.471
0.032 BSC
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
L
ZD
α
0.40 0.60
0.95 REF
0.016 0.024
0.037 REF
0.41
0.81 REF
0°
0.60
0.016 0.024
0.032 REF
0.40 0.60
0.88 REF
0.016 0.024
0.035 REF
0°
5°
0°
5°
5°
0°
5°
0°
5°
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
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