IS61LV12816L-10LQ [ISSI]
Standard SRAM, 128KX16, 10ns, CMOS, PQFP44, MS-026, LQFP-44;
| 型号： | IS61LV12816L-10LQ |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 128KX16, 10ns, CMOS, PQFP44, MS-026, LQFP-44 静态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：58K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61LV12816L
IS61LV12816LL
ISSI
128K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
PRELIMINARYINFORMATION
JULY2002
FEATURES
DESCRIPTION
TheISSIIS61LV12816L/IS61LV12816LLisahigh-speed,
2,097,152-bit static RAM organized as 131,072 words by
16 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields access
times as fast as 8 ns with low power consumption.
• High-speed access time:
IS61LV12816L: 8, 10 ns
IS61LV12816LL: 12, 15 ns
• Operating Current:
IS61LV12816L: 50mA (typ.)
IS61LV12816LL: 25mA (typ.)
• Stand by Current:
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
IS61LV12816L: 500µA (typ.)
IS61LV12816LL: 250µA(typ.)
• TTL and CMOS compatible interface levels
• Single 3.3V power supply
EasymemoryexpansionisprovidedbyusingChipEnable
and Output Enable inputs, CE and OE. The active LOW
WriteEnable(WE)controlsbothwritingandreadingofthe
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
• Fully static operation: no clock or refresh
required
The IS61LV12816L/IS61LV12816LL is packaged in the
JEDEC standard 44-pin TSOP, 44-pin LQFP, and 48-pin
mini BGA (6mm x 8mm).
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
FUNCTIONAL BLOCK DIAGRAM
128Kx16
MEMORY ARRAY
A0-A16
DECODER
VCC
GND
I/O0-I/O7
Lower Byte
I/O
DATA
CIRCUIT
COLUMN I/O
I/O8-I/O15
Upper Byte
CS2
CS1
OE
WE
UB
CONTROL
CIRCUIT
LB
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00B
1
07/30/02
®
ISSI
IS61LV12816L, IS61LV12816LL
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LB
UB
I/O0-I/O7
I/O8-I/O15
VccCurrent
Not Selected
X
H
X
X
X
High-Z
High-Z
ISB1, ISB2
ICC
OutputDisabled
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
Read
Write
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
ICC
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
PIN CONFIGUREATION
44-Pin TSOP (T)
PIN DESCRIPTIONS
A0-A16
I/O0-I/O15
CE
Address Inputs
DataInputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
A4
A3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
2
A6
A2
3
A7
OE
A1
4
OE
A0
5
UB
WE
CE
6
LB
LB
Lower-byteControl(I/O0-I/O7)
Upper-byteControl(I/O8-I/O15)
NoConnection
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
8
UB
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
Vcc
Power
GND
Ground
A8
A9
A10
A11
NC
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev.00B
07/30/02
®
ISSI
IS61LV12816L, IS61LV12816LL
PIN CONFIGUREATION
48-Pin mini BGA (B)
44-Pin LQFP (LQ)
1
2
3
4
5
6
44 43 42 41 40 39 38 37 36 35 345
1
33
32
31
30
29
28
27
26
25
24
23
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
2
A0
A3
A1
A4
A2
LB
I/O
OE
UB
NC
I/O
A
B
C
D
E
F
3
4
CE
8
0
5
I/O
I/O
I/O
A5
A6
I/O
I/O
I/O
2
9
10
1
TOP VIEW
6
GND
Vcc
NC
NC
A14
A12
A7
Vcc
7
11
3
4
5
8
I/O
I/O
GND
I/O
I/O
A16
A15
A13
A10
12
9
I/O
14
I/O
6
13
10
11
I/O8
NC
I/O
15
NC
A8
WE
I/O
7
G
H
12 13 14 15 16 17 18 19 20 21 22
NC
A9
A11
NC
PIN DESCRIPTIONS
A0-A16
I/O0-I/O15
CE
Address Inputs
DataInputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
OE
WE
LB
Lower-byteControl(I/O0-I/O7)
Upper-byteControl(I/O8-I/O15)
NoConnection
UB
NC
Vcc
Power
GND
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev.00B
3
07/30/02
®
ISSI
IS61LV12816L, IS61LV12816LL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCC
Parameter
Value
–0.5 to 4.0V
–0.5 to Vcc + 0.5
–65 to + 150
1.0
Unit
V
Power Supply Voltage Relative to GND
Terminal Voltage with Respect to GND
StorageTemperature
VTERM
TSTG
PT
V
°C
W
PowerDissipation
IOUT
DCOutputCurrent
±20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
OPERATING RANGE
Range
AmbientTemperature
0°C to + 70°C
VCC
Commercial
Industrial
3.3V + 10%, -5%
3.3V + 10%, -5%
–40°C to + 85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
TestConditions
Min.
2.4
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
—
OutputLOWVoltage
InputHIGHVoltage(1)
InputLOWVoltage(1)
InputLeakage
0.4
V
2
VCC + 0.3
V
–0.3
–1
0.8
1
V
GND - VIN - VCC
µA
µA
ILO
OutputLeakage
GND - VOUT - VCC, Outputs Disabled
–1
1
Note:
1.
VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns).
VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width - 2.0 ns).
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev.00B
07/30/02
®
ISSI
IS61LV12816L, IS61LV12816LL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
IS61LV12816L
-8 ns
Min. Max.
-10 ns
Min. Max.
Symbol
Parameter
Test Conditions
Unit
ICC
Vcc Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = Max.
Com.
Ind.
—
—
65
70
—
—
60
65
mA
ISB1
ISB2
TTL Standby
Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE • VIH, f = max
Com.
Ind.
—
—
30
35
—
—
25
30
mA
CMOS Standby
Current
(CMOS Inputs)
VCC = Max.,
Com.
Ind.
—
—
3
4
—
—
3
4
mA
mA
CE - VCC – 0.2V,
VIN > VCC – 0.2V, or
VIN - 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
IS61LV12816LL
-12 ns
-15 ns
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Unit
ICC
Vcc Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = Max.
Com.
Ind.
—
—
50
60
—
—
45
50
mA
ISB1
TTL Standby
Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE • VIH, f = max
Com.
Ind.
—
—
15
20
—
—
15
20
mA
ISB2
CMOS Standby
Current
(CMOS Inputs)
VCC = Max.,
Com.
Ind.
—
—
200
300
—
—
200
300
µA
µA
CE - VCC – 0.2V,
VIN > VCC – 0.2V, or
VIN - 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
Input/OutputCapacitance
6
8
COUT
VOUT = 0V
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev.00B
5
07/30/02
®
ISSI
IS61LV12816L, IS61LV12816LL
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
1.5V
OutputLoad
See Figures 1 and 2
AC TEST LOADS
319 Ω
3.3V
ZO = 50Ω
50Ω
1.5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
Figure 1.
Figure 2.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
IS61LV12816L
-8 ns -10 ns
Min. Min.
IS61LV12816LL
-12 ns -15 ns
Min. Max.
Symbol Parameter
Max
—
Max.
—
10
—
10
4
Min.
12
—
3
Max.
—
12
—
12
5
Unit
tRC
Read Cycle Time
8
—
3
10
—
3
15
—
3
—
15
—
15
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
Output Hold Time
8
tOHA
tACE
tDOE
—
CE Access Time
8
—
—
—
—
0
—
—
—
0
—
—
0
OE Access Time
—
—
0
3.5
3.5
—
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
4
5
6
(2)
tLZOE
tHZCE
—
4
—
5
0
—
8
(2)
0
3.5
—
0
0
0
(2)
tLZCE
3.5
—
0
3
—
4
3
—
5
3
—
6
tBA
3.5
3.5
—
—
0
—
0
—
0
(2)
tHZB
4
5
6
(2)
tLZB
0
0
—
0
—
0
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev.00B
07/30/02
®
ISSI
IS61LV12816L, IS61LV12816LL
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
LB, UB
t
BA
t
HZB
t
LZB
HIGH-Z
DOUT
DATA VALID
UB_CEDR2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev.00B
7
07/30/02
®
ISSI
IS61LV12816L, IS61LV12816LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
IS61LV12816L
-8 ns -10 ns
Min. Max.
IS61LV12816LL
-12 ns
Min. Max.
-15 ns
Min. Max.
Symbol Parameter
Min.
Max
—
Unit
tWC
tSCE
tAW
Write Cycle Time
8
7
7
10
8
—
—
—
12
8
—
—
—
15
10
10
—
—
—
ns
ns
ns
CE to Write End
—
Address Setup Time
to Write End
—
8
8
tHA
Address Hold from Write End
Address Setup Time
0
0
—
—
—
—
—
—
—
3
0
0
—
—
—
—
—
—
—
4
0
0
—
—
—
—
—
—
—
5
0
0
—
—
—
—
—
—
—
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSA
tPWB
tPWE1
tPWE2
tSD
LB, UB Valid to End of Write
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
6.5
6
8
9
10
10
11
7
7
8
6.5
4
8
10
6
5
tHD
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
0
0
0
0
(3)
tHZWE
—
0
—
0
—
0
—
0
(3)
tLZWE
—
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev.00B
07/30/02
®
ISSI
IS61LV12816L, IS61LV12816LL
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
PWE1
PWE2
t
WE
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR1.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev.00B
9
07/30/02
®
ISSI
IS61LV12816L, IS61LV12816LL
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
t
PBW
UB, LB
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR3.eps
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev.00B
07/30/02
®
ISSI
IS61LV12816L, IS61LV12816LL
WRITE CYCLE NO. 4(LB, UB Controlled, Back-to-Back Write) (1,3)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
CE
t
SA
LOW
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is refer
enced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev.00B
11
07/30/02
®
ISSI
IS61LV12816L, IS61LV12816LL
IS61LV12816L
IS61LV12816L
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed(ns) OrderPartNo.
Package
Speed(ns) OrderPartNo.
Package
8
IS61LV12816L-8B
IS61LV12816L-8LQ
IS61LV12816L-8T
mini BGA (6mm x 8mm)
LQFP
PlasticTSOP
8
IS61LV12816L-8BI
IS61LV12816L-8LQI
IS61LV12816L-8TI
mini BGA (6mm x 8mm)
LQFP
PlasticTSOP
10
IS61LV12816L-10B
IS61LV12816L-10LQ
IS61LV12816L-10T
mini BGA (6mm x 8mm)
LQFP
PlasticTSOP
10
IS61LV12816L-10BI
IS61LV12816L-10LQI
IS61LV12816L-10TI
mini BGA (6mm x 8mm)
LQFP
PlasticTSOP
IS61LV12816LL
IS61LV12816LL
ORDERING INFORMATION
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Commercial Range: 0°C to +70°C
Speed(ns) OrderPartNo.
Package
Speed(ns) OrderPartNo.
Package
12
IS61LV12816LL-12BI
IS61LV12816LL-12LQI LQFP
IS61LV12816LL-12TI
mini BGA (6mm x 8mm)
12
IS61LV12816LL-12B
IS61LV12816LL-12LQ
IS61LV12816LL-12T
mini BGA (6mm x 8mm)
LQFP
PlasticTSOP
PlasticTSOP
15
IS61LV12816LL-15B
IS61LV12816LL-15LQ
IS61LV12816LL-15T
mini BGA (6mm x 8mm)
LQFP
PlasticTSOP
15
IS61LV12816LL-15BI
IS61LV12816LL-15LQI LQFP
IS61LV12816LL-15TI PlasticTSOP
mini BGA (6mm x 8mm)
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev.00B
07/30/02
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