IS61C64AL-10TLI [ISSI]
8K x 8 HIGH-SPEED CMOS STATIC RAM; 8K ×8高速CMOS静态RAM
| 型号： | IS61C64AL-10TLI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 8K x 8 HIGH-SPEED CMOS STATIC RAM |
| 文件： | 总13页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61C64AL
ISSI
MARCH2006
8K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
DESCRIPTION
The ISSI IS61C64AL is a very high-speed, low power,
8192-word by 8-bit static RAM. It is fabricated using ISSI's
high-performance CMOS technology. This highly reliable
processcoupledwithinnovativecircuitdesigntechniques,
yields access times as fast as 10 ns with low power
consumption.
• High-speed access time: 10 ns
• CMOS low power operation
— 1 mW (typical) CMOS standby
— 125 mW (typical) operating
• TTL compatible interface levels
• Single 5V power supply
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 150 µW (typical) with CMOS input levels.
• Fully static operation: no clock or refresh
required
• Lead-free available
Easy memory expansion is provided by using one Chip
Enable input, CE. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS61C64AL is packaged in the JEDEC standard 28-
pin, 300-mil SOJ, and TSOP.
FUNCTIONAL BLOCK DIAGRAM
8K x 8
MEMORY ARRAY
A0-A12
DECODER
VDD
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. A
03/16/06
®
IS61C64AL
ISSI
TRUTH TABLE
Mode
WE
CE
OE
I/O Operation VDD Current
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
Output Disabled
Read
Write
H
H
L
L
L
L
H
L
X
High-Z
DOUT
DIN
ICC
ICC
ICC
PIN CONFIGURATION
28-Pin SOJ
PIN CONFIGURATION
28-Pin TSOP (Type 1)
NC
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
WE
NC
OE
A11
A9
22
23
24
25
26
27
28
1
2
3
4
5
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CE
2
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A6
4
A8
A8
A5
5
A9
NC
WE
VDD
NC
A12
A7
A6
A5
A4
A3
A4
6
A11
OE
A3
7
A2
8
A10
CE
A1
9
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0
I/O1
I/O2
GND
6
7
A1
A2
8
PIN DESCRIPTIONS
A0-A12
CE
Address Inputs
Chip Enable 1 Input
Output Enable Input
Write Enable Input
Input/Output
OE
WE
I/O0-I/O7
NC
No Connect
VDD
Power
GND
Ground
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/16/06
®
IS61C64AL
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to +7.0
–65 to +150
1.5
Unit
V
°C
VTERM
TSTG
PT
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
1
W
IOUT
DC Output Current (LOW)
20
mA
2
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
3
4
OPERATING RANGE
(1)
Range
Commercial
Industrial
AmbientTemperature
0°C to +70°C
Speed
-10
-10
VDD
5V 5%
5V 5%
5
–40°Cto+85°C
Note:
1. If operated at 12ns, VDD range is 5V + 10%.
6
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
—
0.4
7
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
—
V
2.2
VDD + 0.5
0.8
V
–0.3
V
8
GND ≤ VIN ≤ VDD
Com.
Ind.
–1
–2
1
2
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD,
Com.
Ind.
–1
–2
1
2
µA
9
Outputs Disabled
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. A
03/16/06
®
IS61C64AL
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10
Min. Max.
-12
Min. Max.
Symbol
Parameter
DDOperating
SupplyCurrent
DD DynamicOperating
TestConditions
DD =Max.,CE=VIL
OUT =0mA,f=0
DD =Max.,CE=VIL
IOUT =0mA,f=fMAX
Unit
I
CC
1
V
V
I
Com.
Ind.
—
—
20
25
—
—
20
25
mA
I
CC
2
V
V
Com.
Ind.
—
—
45
50
—
—
35
45
mA
mA
µA
SupplyCurrent
typ.(2)
25
25
I
SB
1
TTLStandbyCurrent
(TTLInputs)
VDD=Max.,
Com.
Ind.
—
—
1
2
—
—
1
2
VIN =VIH orVIL
CE
≥ VIH,f=0
I
SB
2
CMOSStandby
Current(CMOSInputs)
VDD=Max.,
Com.
Ind.
—
—
200
350
450
—
—
350
450
CE
≥
≥
V
DD –0.2V,
VIN
VDD –0.2V,or
typ.(2)
200
VIN
≤
0.2V, f=0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 5V, TA = 25oC. Not 100% tested.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
8
Unit
pF
Input Capacitance
Output Capacitance
COUT
VOUT = 0V
10
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/16/06
®
IS61C64AL
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-10 ns
Min. Max
-12 ns
Min. Max.
1
Symbol
tRC
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE toPower-Up
10
—
2
—
10
—
10
6
12
—
2
—
12
—
12
6
tAA
2
tOHA
tACS
—
—
0
—
—
0
tDOE
(2)
3
tLZOE
—
5
—
6
(2)
tHZOE
—
2
—
3
(2)
tLZCS
—
5
—
7
(2)
4
tHZCS
—
0
—
0
(3)
tPU
—
10
—
12
(3)
tPD
CEtoPower-Down
—
—
5
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
6
AC TEST CONDITIONS
7
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Unit
0V to 3.0V
3 ns
8
1.5V
Output Load
See Figures 1 and 2
9
AC TEST LOADS
10
11
12
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
5 pF
255 Ω
30 pF
Including
jig and
Including
jig and
scope
scope
Figure 2
Figure 1
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. A
03/16/06
®
IS61C64AL
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACS
CE
t
HZCS
t
LZCS
HIGH-Z
D
OUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/16/06
®
IS61C64AL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-10ns
Min.
-12 ns
Min. Max.
Symbol
tWC
Parameter
Max
—
Unit
ns
1
Write Cycle Time
CE to Write End
10
9
12
10
10
—
—
—
tSCS
—
ns
tAW
Address Setup Time
to Write End
9
—
ns
2
tHA
AddressHold
from Write End
0
—
0
—
ns
3
tSA
Address Setup Time
0
9
—
—
—
—
—
6
0
9
—
—
—
—
—
6
ns
ns
ns
ns
ns
ns
ns
tPWE1
tPWE2
tSD
WE Pulse Width (OE LOW)
WE Pulse Width (OE HIGH)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
8
8
4
7
7
tHD
0
0
(2)
tHZWE
—
0
—
0
5
(2)
tLZWE
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
6
7
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
8
t
WC
VALID ADDRESS
SCS
ADDRESS
9
t
SA
t
t
HA
CE
10
11
12
t
AW
t
tPPWWEE21
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR1.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. A
03/16/06
®
IS61C64AL
ISSI
WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR2.eps
WRITE CYCLE NO. 3(OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE
≥ VIH.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/16/06
®
IS61C64AL
ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
DD forDataRetention
TestCondition
Min. Typ.(1)
Max. Unit
1
VDR
V
SeeDataRetentionWaveform
2.0
5.5
V
I
DR
DataRetentionCurrent
V
DD =2.0V,CE≥VDD –0.2V
Com.
Ind.
—
—
50
90
µA
VIN ≥ VDD – 0.2V, or VIN
≤
VSS + 0.2V
100
2
t
SDR
DataRetentionSetupTime
RecoveryTime
SeeDataRetentionWaveform
SeeDataRetentionWaveform
0
—
—
ns
ns
tRDR
t
RC
Note:
1. Typical Values are measured at VDD = 5V, T
= 25oC and not 100% tested.
A
3
4
DATA RETENTION WAVEFORM (CE Controlled)
t
Data Retention Mode
t
RDR
SDR
5
VDD
4.5V
2.2V
6
V
DR
CE ≥ VDD - 0.2V
CE
GND
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. A
03/16/06
®
IS61C64AL
ISSI
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Speed (ns) Order Part No.
Package
10
IS61C64AL-10JI
IS61C64AL-10JLI
IS61C64AL-10TI
IS61C64AL-10TLI
300-mil Plastic SOJ
300-mil Plastic SOJ, Lead-free
Plastic TSOP
Plastic TSOP, Lead-free
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/16/06
®
PACKAGING INFORMATION
300-mil Plastic SOJ
Package Code: J
ISSI
N
E1
E
1
SEATING PLANE
D
A
A2
B
C
e
b
A1
E2
Notes:
1. Controlling dimension: inches, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash
protrusionsandshouldbemeasuredfromthebottomof
MILLIMETERS
INCHES
Min. Typ. Max.
Sym. Min. Typ. Max.
N0.
thepackage
.
4. Formed leads shall be planar with respect to one
another within 0.004 inches at the seating plane.
Leads
24/26
A
—
—
—
—
—
—
—
—
—
—
—
3.56
—
—
—
—
—
—
—
—
—
—
—
—
0.140
—
A1
A2
b
0.64
2.41
0.41
0.66
0.20
17.02
8.26
7.49
6.27
0.025
0.095
0.016
0.026
0.008
0.670
0.325
0.295
0.247
2.67
0.51
0.81
0.25
17.27
8.76
7.75
7.29
0.105
0.020
0.032
0.010
0.680
0.345
0.305
0.287
B
C
D
E
E1
E2
e
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/25/03
®
PACKAGING INFORMATION
300-mil Plastic SOJ
Package Code: J
ISSI
MILLIMETERS
INCHES
MILLIMETERS
INCHES
Sym. Min. Typ. Max.
Min. Typ. Max.
Sym. Min. Typ. Max.
Min. Typ. Max.
N0.
N0.
Leads
28
Leads
32
A
—
—
—
—
—
—
—
—
—
—
—
3.56
—
—
—
—
—
—
—
—
—
—
—
—
0.140
—
A
—
—
—
—
—
—
—
—
—
—
—
3.56
—
—
—
—
—
—
—
—
—
—
—
—
0.140
—
A1
A2
b
0.64
2.41
0.41
0.66
0.20
18.29
8.26
7.49
6.27
0.025
0.095
0.016
0.026
0.008
0.720
0.325
0.295
0.247
A1
A2
b
0.64
2.41
0.41
0.66
0.20
20.83
8.26
7.49
6.27
0.025
0.095
0.016
0.026
0.008
0.820
0.325
0.295
0.247
2.67
0.51
0.81
0.25
18.54
8.76
7.75
7.29
0.105
0.020
0.032
0.010
0.730
0.345
0.305
0.287
2.67
0.51
0.81
0.25
21.08
8.76
7.75
7.29
0.105
0.020
0.032
0.010
0.830
0.345
0.305
0.287
B
B
C
C
D
D
E
E
E1
E2
e
E1
E2
e
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.D
02/25/03
®
PACKAGINGINFORMATION
ISSI
Plastic TSOP - 28-pins
Package Code: T (Type I)
1
E
H
N
D
SEATING PLANE
A
S
L
α
e
B
C
A1
Plastic TSOP (T—Type I)
Millimeters
Inches
Symbol
Min
Max
Min
Max
Ref. Std.
No. Leads
Notes:
28
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and
A
A1
B
C
D
E
H
e
1.00
0.05
0.16
0.10
7.90
11.70
13.20
0.55 BSC
1.20
0.20
0.27
0.20
8.10
0.037
0.002
0.006
0.004
0.308
0.456
0.515
0.047
0.008
0.011
0.008
0.316
0.465
0.531
should be measured from the bottom of the package
.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
11.90
13.60
0.022 BSC
L
0.30
0.70
0.011
0.027
α
0°
5°
0°
5°
Integrated Silicon Solution, Inc.
PK13197T28 Rev. B 01/31/97
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