IS61C64B-12N [ISSI]
Standard SRAM, 8KX8, 12ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28;
| 型号： | IS61C64B-12N |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 8KX8, 12ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总7页 (文件大小：52K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61C64B
8K x 8 HIGH-SPEED CMOS STATIC RAM
ISSI
JULY 2001
FEATURES
DESCRIPTION
The ISSI IS61C64B is a very high-speed, low power,
8192-word by 8-bit static RAM. It is fabricated using ISSI's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 10 ns with low power consumption.
• High-speed access time: 10, 12, and 15 ns
• Automatic power-down when chip is
deselected
• CMOS low power operation
— 450 mW (typical) operating
— 250 µW (typical) standby
• TTL compatible interface levels
• Single 5V power supply
WhenCEisHIGH(deselected),thedeviceassumesastandby
mode at which the power dissipation can be reduced down to
250 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using one Chip
Enableinput, CE. TheactiveLOWWriteEnable(WE)controls
both writing and reading of the memory.
• Fully static operation: no clock or refresh
required
• Three state outputs
The IS61C64B is packaged in the JEDEC standard 28-pin,
300-mil DIP and SOJ, and TSOP.
• One Chip Enables (CE) for increased speed
FUNCTIONAL BLOCK DIAGRAM
256 X 256
MEMORY ARRAY
A0-A12
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. C
07/17/01
®
IS61C64B
ISSI
PIN CONFIGURATION
28-Pin DIP and SOJ
PIN CONFIGURATION
28-Pin TSOP (Type 1)
NC
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
OE
A11
A9
22
23
24
25
26
27
28
1
2
3
4
5
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CE
2
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
*
A6
4
A8
A8
A5
5
A9
*
WE
A4
6
A11
OE
VCC
NC
A12
A7
A3
7
A2
8
A10
CE
A1
9
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
A6
A5
A4
A3
I/O0
I/O1
I/O2
GND
6
7
A1
A2
8
TRUTH TABLE
PIN DESCRIPTIONS
Mode
WE
CE
OE
I/O Operation Vcc Current
A0-A12
CE
Address Inputs
Not Selected
(Power-down)
Output Disabled
Read
X
X
H
H
L
H
X
L
L
L
X
X
H
L
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
Chip Enable 1 Input
Output Enable Input
Write Enable Input
Input/Output
OE
High-Z
DOUT
DIN
ICC
ICC
ICC
WE
I/O0-I/O7
*
Write
X
Must be tied to either
Vcc or GND
OPERATING RANGE
Vcc
Power
Range
Commercial
Ambient Temperature
Speed
VCC
GND
Ground
0°C to +70°C
10 ns
12 ns
15 ns
5V 5ꢀ
5V 10ꢀ
5V 10ꢀ
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
°C
°C
W
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
–0.5 to +7.0
–10 to +85
–65 to +150
1.0
Temperature Under Bias
Storage Temperature
Power Dissipation
IOUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/17/01
®
IS61C64B
ISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.4
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
—
1
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
0.4
V
2.2
–0.5
–2
VCC + 0.5
V
0.8
2
V
2
GND - VIN - VCC
µA
µA
ILO
Output Leakage
GND - VOUT - VCC, Outputs Disabled
–2
2
Notes:
3
1. VIL = –3.0V for pulse width less than 10 ns.
4
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
5
-10ns
Min. Max.
-12ns
Min. Max.
-15ns
Min. Max.
Symbol Parameter
Test Conditions
Unit
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max.,
IOUT = 0 mA, f = fMAX
—
185
30
—
175
—
135
30
mA
6
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
—
—
30
—
mA
VIN = VIH or VIL
CE1 • VIH or
CE2 - VIL, f = 0
7
ISB2
CMOS Standby
VCC = Max.,
—
10
—
10
—
10
mA
Current (CMOS Inputs)
CE1 • VCC – 0.2V,
CE2 - 0.2V,
8
VIN • VCC – 0.2V, or
VIN - 0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
9
10
11
12
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
8
Unit
pF
Input Capacitance
Output Capacitance
COUT
VOUT = 0V
10
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. C
07/17/01
®
IS61C64B
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
–10ns
Min.
-12ns
Min.
-15ns
Min.
Symbol Parameter
Max.
—
10
—
10
5
Max.
—
12
—
12
6
Max.
—
15
—
15
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
10
—
2
12
—
2
15
—
2
tAA
Address Access Time
Output Hold Time
CE Access Time
tOHA
tACE
tDOE
tLZOE
—
—
0
—
—
0
—
—
0
OE Access Time
(2)
(2)
OE to Low-Z Output
—
5
—
6
—
6
tHZOE
OE to High-Z Output
—
2
—
3
—
3
tLZCE1(2) CE to Low-Z Output
—
5
—
7
—
8
(2)
tHZCE
CE to High-Z Output
—
—
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100ꢀ tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
3 ns
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1a and 1b
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
255 Ω
30 pF
5 pF
Including
jig and
scope
Including
jig and
scope
Figure 1a.
Figure 1b.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/17/01
®
IS61C64B
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
1
t
RC
ADDRESS
2
t
AA
t
OHA
t
OHA
DATA VALID
D
OUT
PREVIOUS DATA VALID
3
4
READ CYCLE NO. 2(1,3)
tRC
5
ADDRESS
OE
tAA
tOHA
6
tHZOE
tDOE
tLZOE
CE
7
tACE
tLZCE
tHZCE
8
HIGH-Z
D
OUT
DATA VALID
9
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. C
07/17/01
®
IS61C64B
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
–10ns
Min.
-12ns
Min.
-15ns
Min.
Symbol Parameter
Max.
—
—
—
—
—
—
—
—
6
Max.
—
—
—
—
—
—
—
—
6
Max.
—
—
—
—
—
—
—
—
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tSCE
tAW
tHA
Write Cycle Time
10
9
12
10
10
0
15
12
12
0
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
9
0
tSA
0
0
0
(4)
tPWE
tSD
WE Pulse Width
8
8
10
9
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
8
8
tHD
0
0
0
(2)
tHZWE
—
0
—
0
—
0
(2)
tLZWE
—
—
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100ꢀ tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
ADDRESS
CE
t
HA
t
SCE
t
AW
t
PWE
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DOUT
DATA UNDEFINED
t
t
HD
DATA-IN VALID
D
IN
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/17/01
®
IS61C64B
ISSI
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
t
WC
ADDRESS
CE
1
t
SA
tHA
t
SCE
2
t
AW
t
PWE
WE
t
HZWE
tLZWE
3
HIGH-Z
D
OUT
DATA UNDEFINED
t
HD
t
SD
4
D
IN
DATA-IN VALID
Notes:
5
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE = VIH.
6
7
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
8
Speed (ns) Order Part No.
Package
10
12
15
IS61C64B-10N
IS61C64B-10J
IS61C64B-10T
300-mil Plastic DIP
300-mil Plastic SOJ
Plastic TSOP
9
IS61C64B-12N
IS61C64B-12J
IS61C64B-12T
300-mil Plastic DIP
300-mil Plastic SOJ
Plastic TSOP
10
11
12
IS61C64B-15N
IS61C64B-15J
IS61C64B-15T
300-mil Plastic DIP
300-mil Plastic SOJ
Plastic TSOP
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. C
07/17/01
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