IS61C64B-10J [ISSI]
8K x 8 HIGH-SPEED CMOS STATIC RAM; 8K ×8高速CMOS静态RAM
| 型号： | IS61C64B-10J |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 8K x 8 HIGH-SPEED CMOS STATIC RAM |
| 文件： | 总9页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61C64B
8K x 8 HIGH-SPEED CMOS STATIC RAM
ISSI
July 2002
FEATURES
DESCRIPTION
The ISSI IS61C64B is a very high-speed, low power,
8192-wordby8-bitstaticRAM.ItisfabricatedusingISSI'shigh-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 10 ns with low power consumption.
• High-speed access time: 10, 12, and 15 ns
• Automatic power-down when chip is
deselected
• CMOS low power operation
— 450 mW (typical) operating
— 250 µW (typical) standby
• TTL compatible interface levels
• Single 5V power supply
WhenCEisHIGH(deselected),thedeviceassumesastandby
mode at which the power dissipation can be reduced down to
250 µW (typical) with CMOS input levels.
EasymemoryexpansionisprovidedbyusingoneChipEnable
input, CE. The active LOW Write Enable (WE) controls both
writing and reading of the memory.
• Fully static operation: no clock or refresh
required
• Three state outputs
The IS61C64B is packaged in the JEDEC standard 28-pin,
300-mil SOJ, and TSOP.
• One Chip Enables (CE) for increased speed
FUNCTIONAL BLOCK DIAGRAM
256 X 256
MEMORY ARRAY
A0-A12
DECODER
VCC
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device
specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/01/02
®
IS61C64B
ISSI
TRUTH TABLE
Mode
WE CE
OE
I/OOperation VccCurrent
Not Selected
(Power-down)
X
X
H
X
X
X
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
OutputDisabled
Read
H
H
L
L
L
L
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
Write
X
PIN CONFIGURATION
28-Pin SOJ
PIN CONFIGURATION
28-Pin TSOP (Type 1)
1
28
VCC
*
A7
A6
OE
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CE
A12
2
27
26
25
24
23
22
21
20
19
18
17
16
15
WE
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
*
4
A8
A8
A5
5
A9
*
A4
6
A11
OE
WE
A3
7
VCC
A2
8
A10
CE
*
A12
2
A1
9
A7
A6
A5
A4
A3
3
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
4
I/O0
I/O1
I/O2
GND
5
6
A1
A2
7
8
PIN DESCRIPTIONS
A0-A12
CE
Address Inputs
Chip Enable 1 Input
Output Enable Input
Write Enable Input
Input/Output
OE
WE
I/O0-I/O7
*
Must be tied to either
Vcc or GND
Vcc
Power
GND
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/01/02
®
IS61C64B
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to +7.0
–10 to +85
–65 to +150
1.0
Unit
V
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND
TemperatureUnderBias
StorageTemperature
1
°C
°C
PowerDissipation
W
2
IOUT
DCOutputCurrent(LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
3
4
OPERATING RANGE
Range
AmbientTemperature
Speed
10 ns
12 ns
15 ns
VCC
5
Commercial
0°C to +70°C
5V ± 5%
5V ± 10%
5V ± 10%
6
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
7
Symbol Parameter
TestConditions
Min.
2.4
—
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
—
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage(1)
InputLeakage
0.4
V
8
2.2
–0.5
–2
VCC + 0.5
V
0.8
2
V
GND - VIN - VCC
µA
µA
9
ILO
OutputLeakage
GND - VOUT - VCC, Outputs Disabled
–2
2
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/01/02
®
IS61C64B
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10ns
Min. Max.
-12ns
Min. Max.
-15ns
Min. Max.
Symbol Parameter
Test Conditions
Unit
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max.,
IOUT = 0 mA, f = fMAX
—
185
30
—
175
—
135
30
mA
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
—
—
30
—
mA
mA
VIN = VIH or VIL
CE1 • VIH or
CE2 - VIL, f = 0
ISB2
CMOS Standby
VCC = Max.,
—
10
—
10
—
10
Current (CMOS Inputs)
CE1 • VCC – 0.2V,
CE2 - 0.2V,
VIN • VCC – 0.2V, or
VIN - 0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
8
Unit
pF
Input Capacitance
Output Capacitance
COUT
VOUT = 0V
10
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/01/02
®
IS61C64B
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
–10ns
Min.
-12ns
Min.
-15ns
Min.
1
Symbol Parameter
Max.
—
10
—
10
5
Max.
—
12
—
12
6
Max.
—
15
—
15
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
10
—
2
12
—
2
15
—
2
tAA
Address Access Time
Output Hold Time
CE Access Time
2
tOHA
tACE
tDOE
tLZOE
—
—
0
—
—
0
—
—
0
OE Access Time
(2)
(2)
3
OE to Low-Z Output
OE to High-Z Output
—
5
—
6
—
6
tHZOE
—
2
—
3
—
3
tLZCE1(2) CE to Low-Z Output
—
5
—
7
—
8
4
(2)
tHZCE
CE to High-Z Output
—
—
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
5
6
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
3 ns
Input Pulse Level
Input Rise and Fall Times
7
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1a and 1b
8
AC TEST LOADS
9
480 Ω
480 Ω
10
11
12
5V
5V
OUTPUT
OUTPUT
255 Ω
255 Ω
5 pF
30 pF
Including
jig and
Including
jig and
scope
scope
Figure 1b.
Figure 1a.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/01/02
®
IS61C64B
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
LZOE
CE
t
ACE
t
LZCE
t
HZCE
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/01/02
®
IS61C64B
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
–10ns
Min.
-12ns
Min.
-15ns
Min.
1
Symbol Parameter
Max.
—
—
—
—
—
—
—
—
6
Max.
—
—
—
—
—
—
—
—
6
Max.
—
—
—
—
—
—
—
—
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tSCE
tAW
tHA
Write Cycle Time
10
9
12
10
10
0
15
12
12
0
CE to Write End
2
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
9
0
tSA
0
0
0
3
(4)
tPWE
tSD
WE Pulse Width
8
8
10
9
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
8
8
tHD
0
0
0
4
(2)
tHZWE
—
0
—
0
—
0
(2)
tLZWE
—
—
—
Notes:
5
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/01/02
®
IS61C64B
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
ADDRESS
CE
t
HA
t
SCE
t
AW
t
PWE
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DOUT
DATA UNDEFINED
t
t
HD
DATA-IN VALID
DIN
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
t
WC
ADDRESS
CE
t
SA
tHA
t
SCE
t
AW
t
PWE
WE
t
HZWE
tLZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
SD
DIN
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/01/02
®
IS61C64B
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
1
Speed(ns) Order Part No.
Package
10
12
15
IS61C64B-10J
IS61C64B-10T
300-mil Plastic SOJ
Plastic TSOP
2
IS61C64B-12J
IS61C64B-12T
300-mil Plastic SOJ
Plastic TSOP
IS61C64B-15J
IS61C64B-15T
300-mil Plastic SOJ
Plastic TSOP
3
4
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/01/02
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