ISL97646_07 [INTERSIL]
Boost + LDO + VON Slice + VCOM; 升压+ LDO + VON片+ VCOM
| 型号： | ISL97646_07 |
| 厂家： | 
Intersil |
| 描述： | Boost + LDO + VON Slice + VCOM |
| 文件： | 总15页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL97646
®
Data Sheet
December 14, 2007
FN6265.1
Boost + LDO + V Slice + V
Features
ON
COM
The ISL97646 represents an integrated DC/DC regulator for
monitor and notebook applications with screen sizes up to
20”. The device integrates a boost converter for generating
• 2.7V to 5.5V Input
• 2.6A Integrated Boost for Up to 20V AVDD
• Integrated VON Slice
AVDD, a VON slice circuit, an integrated logic LDO and a high
performance VCOM amplifier.
• 350mA VLOGIC LDO
The boost converter features a 2.6A FET and has user
programmable soft-start and compensation. With efficiencies
up to 92%, the AVDD is user selectable from 7V to 20V.
- 2.5V, 2.85V, 3.3V Output Voltage Selectable
• 600kHz/1.2MHz fS
• VCOM Amplifier
- 30MHz BW
The logic LDO includes a 350mA FET for driving the low
voltage needed by the external digital circuitry.
- 50V/µs SR
The VON slice circuit can control gate voltages up to 30V.
High and low levels are programmable, as well as discharge
rate and timing.
- 400mA Peak Output Current
• UV and OT Protection
• 24 Ld 4x4 QFN
The integrated VCOM features high speed and drive
• Pb-Free (RoHS Compliant)
capability. With 30MHz bandwidth and 50V/µs slew rate, the
V
COM amplifier is capable of driving 400mA peaks, and
Applications
100mA continuous output current.
• LCD Monitors (15”+)
• Notebook Display (up to 16”)
Pinout
ISL97646
(24 LD 4x4 QFN)
TOP VIEW
Ordering Information
TEMP.
PART NUMBER
(Note)
PART
MARKING
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
24 23 22 21 20 19
ISL97646IRZ-T* 976 46IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4D
Tape & Reel
GND
1
LX
18
17
16
15
14
13
ISL97646IRZ-TK* 976 46IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4D
Tape & Reel
VGH_M
2
VIN_2
FREQ
COMP
SS
VFLK
VDPM
VDD_1
VDD_2
3
4
5
6
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
VIN_1
7
8
9
10 11
12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL97646
Pin Descriptions
PIN NUMBER
PIN NAME
GND
FUNCTION
1
2
Ground
VGH_M
VFLK
Gate Pulse Modulation Output
Gate Pulse Modulation Control Input
Gate Pulse Modulation Enable
3
4
VDPM
VDD_1
VDD_2
OUT
5
Gate Pulse Modulation Lower Voltage Input
6
V
V
V
COM Amplifier Supply
7
COM Amplifier Output
8
NEG
COM Amplifier Inverting Input
9
POS
VCOM Amplifier Noninverting Input
VCOM Amplifier Ground
10
11
12
13
14
AGND
ADJ
LDO Output Adjust Pin
LDO Output
LDO_OUT
VIN_1
SS
LDO power supply
Boost Converter Soft-start. Connect a capacitor between this pin and GND to set the soft-start
time.
15
COMP
Boost Converter Compensation Pin. Connect a series resistor and capacitor between this pin and
GND to optimize transient response.
16
17
18
19
20
21
22
FREQ
VIN_2
LX
Boost Converter Frequency Select.
Boost Converter Power Supply
Boost Converter Switching Node
ENABLE
FB
Chip Enable Pin. Connect to VIN1 for normal operation, GND for shutdown.
Boost Converter Feedback
PGND
CE
Boost Converter Power Ground
Gate Pulse Modulator Delay Control. Connect a capacitor between this pin and GND to set the
delay time.
23
24
RE
Gate Pulse Modulator Slew Control. Connect a resistor between this pin and GND to set the falling
slew rate.
VGH
Gate Pulse Modulator High Voltage Input
FN6265.1
December 14, 2007
2
ISL97646
Absolute Maximum Ratings
Thermal Information
Lx to GND, AGND and PGND . . . . . . . . . . . . . . . . . . . . -0.5 to +25V
VDD2, OUT, NEG and POS
Thermal Resistance
θ
JA (°C/W)
39
θ
JC (°C/W)
2.5
4x4 QFN Package (Notes 1, 2) . . . . . .
to GND, AGND and PGND . . . . . . . . . . . . . . . . . . . . . -0.5 to +25V
VDD1, VGH and VGH_M
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Continuous Junction Temperature . . . . . . . . . . . +125°C
Power Dissipation
TA ≤ +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.44W
TA = +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.34W
TA = +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.98W
TA = +100°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.61W
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
to GND, AGND and PGND . . . . . . . . . . . . . . . . . . . . . -0.5 to +32V
Differential Voltage Between POS and NEG . . . . . . . . . . . . . . . ±6V
Voltage Between GND, AGND and PGND . . . . . . . . . . . . . . . ±0.5V
All Other Pins to GND, AGND and PGND . . . . . . . . . . -0.5 to +6.5V
Input, Output, or I/O Voltage . . . . . . . . . . .GND -0.3V to VIN + 0.3V
Recommended Operating Conditions
Input Voltage Range, VS . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Boost Output Voltage Range, AVDD . . . . . . . . . . . . . . . . . 8V to 20V
Input Capacitance, CIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22µF
Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH to 10µH
LDO Output Capacitance. . . . . . . . . . . . . . . . . . . . . . .2.2µF to 10µF
Output Capacitance, COUT. . . . . . . . . . . . . . . . . . . . . . . . . .2x22µF
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VIN1 = VIN2 = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, TA = -40°C to +85°C
Unless Otherwise Noted.
SYMBOL
GENERAL
VS
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VIN1, VIN2 Input Voltage Range
See separate LDO specifications on
page 4
2.7
5.0
0.2
1
5.5
2
V
IS_DIS
Sum of VIN1, VIN2 Supply Currents ENABLE = 0V
when Disabled
µA
mA
IS
Sum of VIN1, VIN2 Supply Currents ENABLE = 5V, LX not switching, LDO
not loaded
UVLO
Undervoltage Lockout Threshold
VIN2 Rising
2.3
2.2
2.45
2.35
140
100
2.6
2.5
V
V
VIN2 Falling
OTR
OTF
Thermal Shutdown Temperature
Temperature Rising
Temperature Falling
°C
°C
LOGIC INPUT CHARACTERISTICS - ENABLE, VFLK, FREQ, VDPM
VIL
VIH
RIL
Low Voltage Threshold
High Voltage Threshold
Pull-Down Resistor
0.8
400
20
V
V
2.2
Enabled, Input at VIN2
150
250
kΩ
STEP-UP SWITCHING REGULATOR
AVDD
Output Voltage Range
Load Regulation
VIN*1.25
V
%
ΔAVDD/ΔIOUT
ΔAVDD/ΔVIN
ACCAVDD
50mA < ILOAD < 250mA
0.2
Line Regulation
ILOAD = 150mA, 3.0 < VIN1 < 5.5V
0.15
0.25
3
%/V
%
Overall Accuracy (Line, Load,
Temperature)
10mA < ILOAD < 300mA, 3.0 < VIN1
< 5.5V, 0°C < TA < +85°C
-3
FN6265.1
December 14, 2007
3
ISL97646
Electrical Specifications VIN1 = VIN2 = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, TA = -40°C to +85°C
Unless Otherwise Noted. (Continued)
SYMBOL
VFB
PARAMETER
TEST CONDITION
MIN
1.20
1.19
TYP
1.21
1.21
250
150
92
MAX
1.22
1.23
500
UNIT
V
Feedback Voltage (VFB
)
ILOAD = 100mA, TA = +25°C
I
LOAD = 100mA, TA = -40°C to +85°C
V
IFB
FB Input Bias Current
Switch On Resistance
Peak Efficiency
nA
mΩ
%
rDS(ON)
EFF
ILIM
300
Switch Current Limit
Max Duty Cycle
2.1
85
2.6
A
DMAX
fOSC
90
%
Oscillator Frequency
FREQ = 0V
550
1.0
650
1.2
800
1.4
kHz
MHz
µA
FREQ = VIN2
ISS
Soft-Start Slew Current
SS < 1V, TA = +25°C
2.75
LDO REGULATOR
VSL
Input Voltage Range VIN1
ADJ = LDO_OUT
3.0
3.35
3.8
5.5
5.5
5.5
V
V
ADJ OPEN
ADJ = 0V
V
VLDO
Output Voltage
ADJ = GND, ILDO = 1mA
ADJ = GND, ILDO = 350mA
ADJ OPEN, ILDO = 1mA
ADJ OPEN, ILDO = 350mA
ADJ = LDO_OUT, ILDO = 1mA
ADJ = LDO_OUT, ILDO = 350mA
1mA < ILDO < 350mA
ILDO = 1mA, 3.0V < VIN1 < 5.5V
1mA < ILDO < 350mA
Output drops by 2%, ILDO = 350mA
Output drops by 2%
3.31
3.29
2.86
2.84
2.51
2.49
V
V
V
V
V
V
ACCLDO
ΔVLDO/ΔVIN
ΔVLDO/ΔIOUT
VDO
Overall Accuracy
Line Regulation
Load Regulation
Dropout Voltage
Current Limit
-4
4
%
2
mV/V
%
0.75
300
400
500
20
mV
mA
ILIML
350
4.5
VCOM AMPLIFIER RLOAD = 10k, CLOAD = 10pF, Unless Otherwise Stated
VSAMP
ISAMP
VOS
Supply Voltage
V
mA
mV
nA
V
Supply Current
3
3
0
Offset Voltage
20
100
IB
Noninverting Input Bias Current
CMIR
Common Mode Input Voltage
Range
0
VDD2
CMRR
PSRR
VOH
VOH
VOL
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Output Voltage Swing High
Output Voltage Swing High
Output Voltage Swing Low
Output Voltage Swing Low
50
70
70
85
dB
dB
IOUT(SOURCE) = 5mA
OUT(SOURCE) = 50mA
VDD2 - 50
VDD2 - 450
50
mV
mV
mV
mV
I
IOUT(SINK) = 5mA
IOUT(SINK) = 50mA
VOL
450
FN6265.1
December 14, 2007
4
ISL97646
Electrical Specifications VIN1 = VIN2 = ENABLE = 5V, VDD1 = VDD2 = 14V, VGH = 25V, AVDD = 10V, TA = -40°C to +85°C
Unless Otherwise Noted. (Continued)
SYMBOL
PARAMETER
Output Short Circuit Current
Slew Rate
TEST CONDITION
MIN
TYP
400
50
MAX
UNIT
mA
ISC
SR
250
V/µs
MHz
BW
Gain Bandwidth
-3dB gain point
30
GATE PULSE MODULATOR
VGH
IVGH
VGH Voltage
7
30
V
µA
µA
V
VGH Input Current
VFLK = 0
260
40
RE = 33kΩ, VFLK = VDD1
VDD1
VDD1 Voltage
3
VGH - 2
2
IVDD1
VDD1 Input Current
-2
0.1
70
8
µA
Ω
RONVGH
IDIS_VGH
TDEL
VGH to VGH_M On Resistance
VGH_M Discharge Current (Note 3) RE = 33kΩ
DELAY Time (Note 4) CE = 470pF, RE = 33kΩ
mA
µs
1.9
NOTES:
3. Nominal discharge current = 300/(RE + 5kΩ).
4. Nominal delay time = 4000*CE.
FN6265.1
December 14, 2007
5
ISL97646
I
Typical Performance Curves
100
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
f
= 650kHz
OSC
90
80
70
60
50
40
30
20
10
0
f
= 1.2MHz
OSC
f
= 650kHz
= 1.2MHz
OSC
f
OSC
0
200
400
600
(mA)
800
1000
1200
0
200
400
600
IA (mA)
VDD
800
1000
1200
IA
VDD
FIGURE 1. AVDD EFFICIENCY vs IAVDD
FIGURE 2. AVDD LOAD REGULATION vs IAVDD
10.50
10.45
10.40
10.35
10.30
10.25
10.20
10.15
L = 10µH, C
= 40µF, C
= 2.2nF, R
= 10k
COMP
OUT
COMP
A
150mA
VDD
IA
VDD
A
500mA
VDD
A
(AC COUPLED)
VDD
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
V
IN
FIGURE 3. LINE REGULATION AVDD vs VIN
FIGURE 4. BOOST CONVERTER TRANSIENT RESPONSE
0
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
3.3V OUTPUT, 100mA
3.3V OUTPUT, 350mA
-0.2
ADJ = 0
-0.4
-0.6
-0.8
-1.0
-1.2
2.85V OUTPUT, 100mA
2.85V OUTPUT, 350mA
ADJ = LDO_OUT
ADJ = OPEN
2.5V OUTPUT, 350mA
2.5V OUTPUT, 100mA
0
100
200
300
400
3
4
5
6
V
(V)
I
(mA)
IN
O
FIGURE 5. LINE REGULATION LDO_OUT vs VIN
FIGURE 6. LDO LOAD REGULATION vs IO
FN6265.1
December 14, 2007
6
ISL97646
Typical Performance Curves (Continued)
CE = 1pF, RE = 100k
CE = 1000pF, RE = 100k
VGH_M
VFLK
VGH_M
VFLK
FIGURE 7. GPM CIRCUIT WAVEFORM
FIGURE 8. GPM CIRCUIT WAVEFORM
CE = 10pF, RE = 100k
CE = 10pF, RE = 150k
VGH_M
VGH_M
VFLK
VFLK
FIGURE 9. GPM CIRCUIT WAVEFORM
FIGURE 10. GPM CIRCUIT WAVEFORM
INPUT
SIGNAL
INPUT SIGNAL
OUTPUT SIGNAL
OUTPUT
SIGNAL
(-3dB ATTENUATION
FROM INPUT SIGNAL)
FIGURE 11. VCOM RISING SLEW RATE
FIGURE 12. VCOM BANDWIDTH MEASUREMENT
FN6265.1
December 14, 2007
7
ISL97646
Block Diagram
FREQ
LX
OSCILLATION
GENERATOR
SLOPE
COMPENSATION
COMP
SUMMING
AMPLIFIER
FB
-
PWM
LOGIC
+
2.5µA
-
+
PGND
SS
VIN2
REFERENCE
GENERATOR
START-UP AND
FAULT CONTROL
VDPM
ENABLE
LDO
CONTROLLER
ADJ
V
LDO_OUT
VDD2
IN1
POS
NEG
GND
+
-
OUT
GPM
CIRCUIT
VDD1
VFLK VGH VGH_M CE
RE
FIGURE 13. ISL97646 BLOCK DIAGRAM
FN6265.1
December 14, 2007
8
ISL97646
Typical Application Diagram
L1
10µH
D1
A
V
VDD
IN
VIN2
C2
47µF
R1
10k
LX
C1
22µF
C3
2.2nF
C9 (OPTIONAL)
COMP
BOOST
FB
R5
10k
C4
10nF
R2
1.3k
PGND
SS
ENABLE
FREQ-
VDPM
V
ON
VGH
VDD_1
VFLK
C5
GPM
CIRCUIT
470P
VGH_M
VDD2
CE
TO ROW DRIVER
RE
R6
130k
C10
2.2µF
R3
2k
POS
A
VDD
C11
1µF
NEG-
OUT
VIN1
R7
80k
V
+4.0V
COM
V
LOGIC
LDO_OUT
ADJ
C6
0.1µF
C7
4.7µF
AGND
GND
LDO
CONTROLLER
FIGURE 14. TYPICAL APPLICATION DIAGRAM
Applications Information
Boost Converter
The ISL97646 provides a complete power solution for TFT
LCD applications. The system consists of one boost
converter to generate AVDD voltage for column drivers, one
logic LDO regulator to provide voltage to logic circuit in the
LCD panel, one integrated VCOM buffer which can provide
up to 400mA peak current. This part also integrates a Gate
Pulse Modulator circuit that can help to optimize the picture
quality.
Frequency Selection
The ISL97646 switching frequency can be user selected to
operate at either constant 650kHz or 1.2MHz. Lower
switching frequency can save power dissipation, while
higher switching frequency can allow smaller external
components like inductor and output capacitors, etc.
Connecting FREQ pin to ground sets the PWM switching
frequency to 650MHz, or connecting FREQ pin to VIN for
1.2MHz.
Enable Control
Soft-Start
When enable pin is pulling down, the ISL97646 is shut down
reducing the supply current to <10µA. When the voltage at
enable pin reaches 2.2V, the ISL97646 is on.
The soft-start is provided by an internal 2.5µA current source
to charge the external soft start capacitor. The ISL97646
ramps up current limit from 0A up to full value, as the voltage
at SS pin ramps from 0V to 1.2V. Hence the soft-start time is
4.8ms when the soft-start capacitor is 10nF, 22.6ms for 47nF
and 48ms for 100nF.
FN6265.1
December 14, 2007
9
ISL97646
The current through the MOSFET is limited to 2.6APEAK
.
Operation
The boost converter is a current mode PWM converter
operating at either a 650kHz or 1.2MHz. It can operate in
both discontinuous conduction mode (DCM) at light load and
continuous mode (CCM). In continuous current mode,
current flows continuously in the inductor during the entire
switching cycle in steady state operation. The voltage
conversion ratio in continuous current mode is given by:
This restricts the maximum output current (average) based
on the Equation 3:
ΔI
V
IN
V
O
L
⎛
⎝
⎞
⎠
--------
---------
I
=
I
–
LMT
×
(EQ. 3)
OMAX
2
Where ΔIL is peak to peak inductor ripple current, and is set
by:
V
1
BOOST
-----------------------
-------------
=
(EQ. 1)
V
1 – D
V
D
f
s
IN
IN
--------- ---
ΔI
=
×
(EQ. 4)
L
L
Where D is the duty cycle of the switching MOSFET.
where fS is the switching frequency (650kHz or 1.2MHz).
Figure 13 shows the block diagram of the boost regulator. It
uses a summing amplifier architecture consisting of gm
stages for voltage feedback, current feedback and slope
compensation. A comparator looks at the peak inductor
current cycle by cycle and terminates the PWM cycle if the
current limit is reached.
Table 2 gives typical values (margins are considered 10%,
3%, 20%, 10% and 15% on VIN, VO, L, fS and IOMAX).
Capacitor
An input capacitor is used to suppress the voltage ripple
injected into the boost converter. The ceramic capacitor with
capacitance larger than 10µF is recommended. The voltage
rating of input capacitor should be larger than the maximum
input voltage. Some capacitors are recommended in Table 1
for input capacitor.
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60kΩ is recommended.
The boost converter output voltage is determined by
Equation 2:
TABLE 1. BOOST CONVERTER INPUT CAPACITOR
RECOMMENDATION
CAPACITOR
10µF/16V
SIZE
1206
0805
1210
MFG
TDK
PART NUMBER
C3216X7R1C106M
R
+ R
2
R
2
1
10µF/10V
22µF/10V
Murata GRM21BR61A106K
Murata GRB32ER61A226K
--------------------
V
=
× V
(EQ. 2)
BOOST
FB
TABLE 2. MAXIMUM OUTPUT CURRENT CALCULATION
VIN (V)
VO (V)
9
L (µH)
10
fs (MHz)
0.65
0.65
0.65
0.65
0.65
0.65
0.65
1.2
IOMAX (mA)
636
3
3
3
5
5
5
5
3
3
3
5
5
5
5
12
15
9
10
419
10
289
10
1060
699
12
15
18
9
10
10
482
10
338
10
742
12
15
9
10
1.2
525
10
1.2
395
10
1.2
1236
875
12
15
18
10
1.2
10
1.2
658
10
1.2
514
FN6265.1
December 14, 2007
10
ISL97646
NOTE: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across then increases.
OUT in Equation 6 above assumes the effective value of the
capacitor at a particular voltage and not the manufacturer’s stated
value, measured at zero volts.
Inductor
The boost inductor is a critical part which influences the
output voltage ripple, transient response, and efficiency.
Values of 3.3µH to 10µH are used to match the internal
slope compensation. The inductor must be able to handle
the following average and peak current:
C
Table 5 lists some selections of output capacitors.
TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION
I
O
-------------
I
I
=
LAVG
CAPACITOR
10µF/25V
SIZE
1210
1210
MFG
TDK
Murata
PART NUMBER
C3225X7R1E106M
GRM32DR61E106K
(EQ. 5)
1 – D
ΔI
L
--------
+
= I
LPK
LAVG
2
10µF/25V
Some inductors are recommended in Table 3.
Compensation
TABLE 3. BOOST INDUCTOR RECOMMENDATION
The boost converter of ISL97646 can be compensated by a
RC network connected from the CM1 pin to ground. 4.7nF
and 10k RC network is used in the demo board. The larger
value resistor and lower value capacitor can lower the
transient overshoot, however, at the expense of stability of
the loop.
DIMENSIONS
INDUCTOR
6.8µH/3APEAK
10µH/4APEAK
(mm)
MFG
TDK
Sumida
PART NUMBER
RLF7030T-6R8N3R0
CDR8D43-100NC
CD1-5R2
7.3x6.8x3.2
8.3x8.3x4.5
5.2µH/4.55APEAK 10x10.1x3.8 Cooper
Bussmann
Cascaded MOSFET Application
A 20V N-Channel MOSFET is integrated in the boost
regulator. For the applications where the output voltage is
greater than 20V, an external cascaded MOSFET is needed,
as shown in Figure 15. The voltage rating of the external
Rectifier Diode
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of their
fast recovery time and low forward voltage. The reverse voltage
rating of this diode should be higher than the maximum output
voltage. The rectifier diode must meet the output current and
peak inductor current requirements. Table 4 lists some
recommendations for boost converter diode.
MOSFET should be greater than AVDD
.
A
V
VDD
IN
TABLE 4. BOOST CONVERTER RECTIFIER DIODE
RECOMMENDATION
LX
DIODE
SS23
VR/IAVG RATING
PACKAGE
MFG
FB
INTERSIL
ISL97646
30V/2A
SMB
Fairchild
Semiconductor
MBRS340
SL23
40V/3A
30V/2A
SMC
SMB
International
Rectifier
Vishay
Semiconductor
FIGURE 15. CASCADED MOSFET TOPOLOGY FOR HIGH
OUTPUT VOLTAGE APPLICATIONS
Output Capacitor
The output capacitor supplies the load directly and reduces
the ripple voltage at the output. Output ripple voltage
consists of two components: the voltage drop due to the
inductor ripple current flowing through the ESR of output
capacitor, and the charging and discharging of the output
capacitor.
Linear-Regulator (LDO)
The ISL97646 includes a LDO with adjustable output, and it
can supply current up to 350mA. The output voltage is
adjusted by connection of ADJ pin. When ADJ pin is
connected to ground, the output voltage is set to 3.3V; when
ADJ pin is floating, the output voltage is set to 2.85V, and
when ADJ pin is connected to LDO_OUT pin, the output
voltage is set to 2.5V.
V
– V
I
O
1
f
s
O
IN
----------------------- --------------- ---
V
= I
× ESR +
LPK
×
×
(EQ. 6)
RIPPLE
V
C
O
OUT
For low ESR ceramic capacitors, the output ripple is
dominated by the charging and discharging of the output
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
FN6265.1
December 14, 2007
11
ISL97646
The efficiency of LDO is depended on the difference
between input voltage and output voltage, as well as the
output current:
Gate Pulse Modulator Circuit
The gate pulse modulator circuit functions as a three way
multiplexer, switching VGHM between ground, VDD1 and
VGH. Voltage selection is provided by digital inputs VDPM
(enable) and VFLK (control). High to low delay and slew
control is provided by external components on pins CE and
RE, respectively. A block diagram of the gate pulse
modulator circuit is shown in Figure 16.
η(%) = (V
– V
) × I
× 100%
LDO_OUT
(EQ. 7)
IN1
LDO_OUT
The less difference between input and output voltage, the
higher efficiency it is. The minimum dropout voltage of LDO
of ISL97646 is 300mV.
When VDPM is LOW, the block is disabled and VGHM is
grounded. When VDPM is HIGH, the output is determined
by VFLK. When VFLK goes high, VGHM is pulled to VGH by
a 70Ω switch. When VFLK goes low, there is a delay
controlled by capacitor CE, following which VGHM is driven
to VDD1, with a slew rate controlled by resistor RE. Note
that VDD1 is used only as a reference voltage for an
amplifier, thus does not have to source or sink a significant
DC current.
The ceramic capacitors are recommended for the LDO input
and output capacitor. Larger capacitors help reduce noise
and deviation during transient load change.
VGH
VGH_M
EnGPM1
+
-
VDD1
x240
VREF
+
-
RE
CE
200µA
-
CONTROL AND
TIMING
VFLK
FIGURE 16. GATE PULSE MODULATOR CIRCUIT BLOCK DIAGRAM
FN6265.1
December 14, 2007
12
ISL97646
Low to high transition is determined primarily by the switch
resistance and the external capacitive load. High to low
INPUT
TO INDUCTOR
transition is more complex. Take the case where the block is
already enabled (VDPM is H). When VFLK is H, pin CE is
grounded. On the falling edge of VFLK, a current is passed
into pin CE, to charge an external capacitor to 1.2V. This
creates a delay, equal to CE*4200. At this point, the output
begins to pull down from VGH to VDD1. The slew current is
equal to 300/(RE + 5000)*Load Capacitance.
ENABLE
FIGURE 19. CIRCUIT TO DISCONNECT THE DC PATH OF
BOOST CONVERTER
VDPM
0
V
Amplifier
COM
The VCOM amplifier is designed to control the voltage on the
back plate of an LCD display. This plate is capacitively
coupled to the pixel drive voltage which alternately cycles
positive and negative at the line rate for the display. Thus,
the amplifier must be capable of sourcing and sinking
capacitive pulses of current, which can occasionally be quite
large (a few 100mA for typical applications).
VFLK
SLOPE CONTROLLED
BY RE AND LOAD
CAPACITANCE
0
VGH
VGH_M
VDD_1
0
The ISL97646 VCOM amplifier's output current is limited to
400mA. This limit level, which is roughly the same for
sourcing and sinking, is included to maintain reliable
operation of the part. It does not necessarily prevent a large
temperature rise if the current is maintained. (In this case the
whole chip may be shut down by the thermal trip to protect
functionality). If the display occasionally demands current
pulses higher than this limit, the reservoir capacitor will
provide the excess and the amplifier will top the reservoir
capacitor back up once the pulse has stopped. This will
happen on the µs time scale in practical systems and for
pulses 2 or 3 times the current limit, the VCOM voltage will
have settled again before the next line is processed.
DELAY TIME
CONTROLLED BY CE
FIGURE 17. GATE PULSE MODULATOR TIMING DIAGRAM
Start-Up Sequence
Figure 18 shows a detailed start-up sequence waveform.
V
IN
0
ENABLE
0
VIN THRESHOLD
Fault Protection
VDPM
0
ISL97646 provides the overall fault protections including
overcurrent protection and over-temperature protection.
An internal temperature sensor continuously monitors the
die temperature. In the event that die temperature exceeds
the thermal trip point, the device will shut down and disable
itself. The upper and lower trip points are typically set to
+140°C and +100°C, respectively.
AVDD
VGH_M
LDO OUTPUT
0
FIGURE 18. START-UP SEQUENCE
When VIN exceeds 2.5V and ENABLE reaches the VIH
threshold value, Boost converter and LDO start-up, and gate
pulse modulator circuit output holds until VDPM goes to
high. Note that there is a DC path in the boost converter from
the input to the output through the inductor and diode, hence
the input voltage will be seen at output with a forward voltage
drop of diode before the part is enabled. If this voltage is not
desired, the following circuit can be inserted between input
and inductor to disconnect the DC path when the part is
disabled.
FN6265.1
December 14, 2007
13
ISL97646
Layout Recommendation
The device’s performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place VIN and VDD bypass capacitors close to the pins.
3. Reduce the loop area with large AC amplitudes and fast
slew rate.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point.
6. The exposed die plate, on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
8. A signal ground plane, separate from the power ground
plane and connected to the power ground pins only at the
exposed die plate, should be used for ground return
connections for control circuit.
9. Minimize feedback input track lengths to avoid switching
noise pick-up.
A demo board is available to illustrate the proper layout
implementation.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6265.1
December 14, 2007
14
ISL97646
Package Outline Drawing
L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/06
4X
2.5
4.00
A
20X
0.50
PIN #1 CORNER
(C 0 . 25)
B
19
24
PIN 1
INDEX AREA
1
18
2 . 50 ± 0 . 15
13
0.15
(4X)
12
24X 0 . 4 ± 0 . 1
7
0.10 M C
A B
TOP VIEW
+ 0 . 07
24X 0 . 23
4
- 0 . 05
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
0 . 90 ± 0 . 1
C
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08
SIDE VIEW
C
(
2 . 50 )
( 20X 0 . 5 )
5
C
0 . 2 REF
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6265.1
December 14, 2007
15
相关型号：
ISL97648IRTZ
LIQUID CRYSTAL DISPLAY DRIVER, PQCC56, 8 X 8 MM, ROHS COMPLIANT, PLASTIC, TQFN-56
RENESAS
ISL97648IRTZ-T
LIQUID CRYSTAL DISPLAY DRIVER, PQCC56, 8 X 8 MM, ROHS COMPLIANT, PLASTIC, TQFN-56
RENESAS
ISL97648IRTZ-TK
LIQUID CRYSTAL DISPLAY DRIVER, PQCC56, 8 X 8 MM, ROHS COMPLIANT, PLASTIC, TQFN-56
RENESAS
©2020 ICPDF网 联系我们和版权申明