ISL97648IRTZ-T [RENESAS]
LIQUID CRYSTAL DISPLAY DRIVER, PQCC56, 8 X 8 MM, ROHS COMPLIANT, PLASTIC, TQFN-56;
| 型号： | ISL97648IRTZ-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | LIQUID CRYSTAL DISPLAY DRIVER, PQCC56, 8 X 8 MM, ROHS COMPLIANT, PLASTIC, TQFN-56 驱动 接口集成电路 |
| 文件： | 总21页 (文件大小：566K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL97648
®
Data Sheet
April 14, 2008
FN6684.0
Integrated TFT LCD Supply and Logic
Driver
Features
• 2.6V to 5.5V input supply
The ISL97648 represents a high power, integrated LCD
supply IC which is targeted at Notebook, Monitor and TV
LCD displays. The ISL97648 integrates a level shift with
• Integrated 2.7A Boost Converter
• 1.4MHz Switching Frequency
charge sharing function, boost converter for A
VDD
• Level Shifter
generation of high power with HVS and temperature sensor,
2
- Up to 332kHz Input Logic Frequency
4 high power V
calibrator.
amplifiers, and I C LCD VCOM digital
COM
- +40V to -25V Output Swing Capability
- 100mA Output Peak Current
- TTL-Compatible Logic Input
The ISL97648 integrates a high-performance boost converter
with 2.7A FET for generating A supply up to 18V.
VDD
• Four High Speed V
COM
Amplifiers
The ISL97648 has a high voltage TFT-LCD logic driver with
+40V and -25V output swing capability. It is capable of
delivering 100mA output peak current into 5nF of capacitive
load. To simplify external circuitry, the ISL97648 integrates
additional logic circuits.
• ±5°C Accuracy Thermal Sensor Over the -40°C to +150°C
Temperature Range.
2
• I C Calibrator
- 128-Step Adjustable Sink Current Output
- Output Adjustment SET Pin
The integrated HVS circuit is used to provide high voltage
stress testing of the LCD panel for production purpose.
• 56 Ld 8mmx8mm TQFN Package
• Pb-Free (RoHS Compliant)
An on-board temperature sensor is also provided for system
thermal management control.
Applications
The 4 integrated amplifiers feature high slew-rate and high
output current capability. They are permanently enabled
• LCD-Notebook, Monitor and TV
• Industrial/medical LCD Displays
when A
VDD
is present.
The VCOM voltage of an LCD panel needs to be adjusted to
remove flicker. This part provides a digital interface to control
the sink-current output that attaches to an external voltage
divider. The increase in output sink current lowers the
voltage on the external divider, which is applied to an
external VCOM buffer amplifier. The desired VCOM setting
is loaded from an external source via a standard 2 wire I C
serial interface. At power-up the part automatically comes up
at last programmed setting in an on-board 7-bit EEPROM.
Ordering Information
PART NUMBER
(Note)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL97648IRTZ
97648IRTZ 56 Ld 8x8 TQFN L56.8x8D
2
ISL97648IRTZ-T* 97648IRTZ 56 Ld 8x8 TQFN L56.8x8D
ISL97648IRTZ-TK* 97648IRTZ 56 Ld 8x8 TQFN L56.8x8D
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
The ISL97648 is packaged in a 56 Ld, 8mmx8mm TQFN
package and is specified for operation over the -40°C to
+85°C temperature range.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL97648
Pinout
ISL97648
(56 LD TQFN)
TOP VIEW
56 55 54 53 52 51 50 49 48 47 46 45 44 43
CKVCS1
CKVBCS1
CKVB1
SW2
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SW1
TEST
AVDD
CGND
VCOM4
3
STVP1
4
STVP2
5
CKVB2
6
THERMAL PAD
CONNECTED TO GND
CKVBCS2
CKVCS2
CKV2
IN4-
7
IN4+
8
VCOM3
9
STV1
STV2
CPV1
CPV2
OE
IN3-
10
11
12
13
14
IN3+
VCOM2
IN2-
IN2+
15 16 17 18 19 20 21 22 23 24 25 26 27 28
FN6684.0
April 14, 2008
2
ISL97648
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
All Other Pins except the following . . . . . . . . . . . . . . -0.3V to +6.5V
VIN to PGND, AGND, and LGND . . . . . . . . . . . . . . . . -0.3V to 6.5V
VDD to PGND, AGND, and LGND. . . . . . . . . . . . . . . . . . . . . . . 6.5V
SW to PGND, AGND, and LGND . . . . . . . . . . . . . . . . . -0.3V to 22V
EN, FB, COMP, TEMP, HVS, RHVS
to PGND, AGND, and LGND . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
IN1+, IN1-, and VCOM1 to PGND, AGND, and LGND . -0.3V to 20V
IN2+, IN2-, and VCOM2 to PGND, AGND, and LGND . -0.3V to 20V
IN3+, IN3-, and VCOM3 to PGND, AGND, and LGND . -0.3V to 20V
IN4+, IN4-, and VCOM4 to PGND, AGND, and LGND . -0.3V to 20V
AVDD to PGND, AGND, and LGND . . . . . . . . . . . . . . . -0.3V to 22V
DISH to PGND, AGND, and LGND . . . . . . . . . . . . . . . -3.6V to 5.5V
OECON to PGND, AGND, and LGND. . . . . . . . . . . . . -0.3V to 5.5V
Thermal Resistance (Typical)
θ
(°C/W)
θ
(°C/W)
JA
48.33
). . . -40°C to +125°C
JC
TQFN Package (Notes 1, 2). . . . . . . . .
Functional Junction Temperature (T
12.07
JUNCTION
) . . . . . . . . . . . . -65°C to +150°C
Storage Temperature (T
STORAGE
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Operating Temperature (T ) . . . . . . . . . . . . . . . . . . -40°C to +85°C
A
V
V
V
to PGND, AGND, and LGND. . . . . . . . . . . . . . . . . . . . . . . .44V
ON
to PGND, AGND, and LGND . . . . . . . . . . . . . . . . . . . . . . -28V
OFF
V
V
V
V
V
CKV1, CKV2, CKVB1, CKVB2, CKVCS1, CKVCS2,
STVP1,STVP2 to
V
V
CKVBCS1, CKVBCS2,
PGND, AGND, and LGND . . . . . . . . . . . . . . . . . . . . . -28V to 44V
SDA, SCL, SCLS-S, W , W to PGND,
pn pp
AGND, and LGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V
OUT to PGND, AGND, and LGND. . . . . . . . . . . . . . . . . . . . . . . .20V
Voltage between PGND, AGND, and LGND . . . . . . . . . . . . . +-0.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications VDD = V = 3.3V, A
= 12V, V
= 20V, V = -14V, T from -40°C to +85°C, Fcpv1 and Fcpv2 = 105kHz,
OFF A
IN
VDD
ON
unless otherwise specified. Unless otherwise specified, parts are 100% tested at +25°C. Temperature limits
established by characterization and are not production tested.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
2.25
2.6
TYP
MAX
3.6
UNIT
V
V
V
V
V
Supply Range -- Operating
Supply Range -- EEPROM
DD
DD
DD
3.6
V
Programming
Analog Supply Voltage
AVDD Output Voltage
Positive Supply Voltage
Negative Supply Voltage
Input Quiescent Current
2.2
5
3.3
5.5
18
40
V
V
IN
AVDD
V
V
25
V
ON
OFF
IN_Q
-25
-15
V
I
Not switching (OVP active)
Pin EN to ground
3
1
mA
µA
BOOST
r
Switch ON-resistance
V
= 2.7V, I
= 1A
200
2.9
450
5
mΩ
(DS)ON
IN SW
ΔV /ΔV
Feedback Voltage Line Regulation
2.2V < V < 5.5V, I
IN OUT
= 200mA, V
AVDD
= 8V,
mV/V
FB
IN
L = 6.8µH, C = 10µF
OUT
ΔV
/ΔI
Load Regulation
50mA < I
OUT
L = 6.8µH
< 0.5A, V = 3.3V, V
= 7.8V,
90
mV/A
V
AVDD OUT
IN AVDD
V
Boost Feedback Voltage
Closed loop: V
= 8V, L = 6.8µH,
1.205
1.230
130
1.255
FB
AVDD
I
= 200mA, T = +25°C
OUT
A
I
I
FB Pin Bias Current
RHVS Pin Leakage Current
HVS Pin Resistor
0.1
100
155
µA
nA
Ω
B
HVS pin to ground
HVS pin to ground
RHVS
Res
105
1.5
HVS
V
V
HVS
Input Voltage HIGH
Input Voltage LOW
V
= 2.2V
V
IH
IL
IN
HVS
0.44
V
FN6684.0
April 14, 2008
3
ISL97648
Electrical Specifications VDD = V = 3.3V, A
= 12V, V
= 20V, V = -14V, T from -40°C to +85°C, Fcpv1 and Fcpv2 = 105kHz,
OFF A
IN
VDD
ON
unless otherwise specified. Unless otherwise specified, parts are 100% tested at +25°C. Temperature limits
established by characterization and are not production tested. (Continued)
PARAMETER
DESCRIPTION
Soft-Start Time
CONDITIONS
MIN
80
TYP
10
MAX
UNIT
ms
t
SS
D
Max Duty Cycle
85
%
max
min
D
Min Duty Cycle
15
20
%
F
Oscillator Switching Frequency
V
= 8V, I
= 200mA, L = 6.8µH,
= 30µF
1.1
1.38
1.5
MHz
OSC
AVDD OUT
D = ZHC750, C
OUT
I
Switch Leakage Current
10
µA
°C
°C
V
L
T
Thermal Shutdown Threshold
Activation threshold
150
130
SH
De-activation threshold
Output High
Th
Enable Threshold
Enable Pin Current
0.7
1.1
0.1
3.2
EN
I
I
µA
A
EN
OCP
Overcurrent Protection in the Power L = 6.8µH
MOS
2.2
2.7
OVP
Overvoltage Protection on Threshold
Overvoltage Protection Hysteresis
Undervoltage Protection on Threshold
UVLO Hysteresis
18.5
21.5
2.2
V
V
OVP_HYS
UVLO
2
2.0
2.1
100
V
UVLO_HYS
mV
VCOM AMPLIFIERS R
LOAD
= 10kΩ, C
= 10pF, unless otherwise stated
4 Op amps combined
LOAD
I
Supply Current
Supply Voltage
8
5
18
mA
V
SAMP
V
8
18.5
SAMP
CMRR
PSRR
VOH
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Output Voltage Swing High
50
70
70
85
dB
dB
V
I
I
(source) = 5mA
(source) = 50mA
A
-
-
OUT
OUT
VDD
0.05
A
V
VDD
0.5
VOL
Output Voltage Swing Low
Input Offset Voltage
I
I
(sink) = 5mA
(sink) = 50mA
0.05
0.5
V
V
OUT
OUT
V
-15
15
mV
OFFSET
(V ) - (V ) = V
OFFSET
IN+
IN-
BW
Bandwidth
-3dB gain point
30
100
40
MHz
nA
I
INx+, INx-, (x = 1, 2, 3, 4)
Slew Rate
-1000
150
1000
B
SR
V/µs
mA
I
Output Short Circuit Current
250
SC
TEMPERATURE SENSOR, T = +25°C
A
I
Drive Current
For +1°C additional error
70
µA
V
TEMP
V
Offset Output Voltage at T = +100°C
J
1.600
±5
TEMP
T
Temperature Accuracy
Temperature Coefficient
+50°C < T < +150°C
°C
ACCURACY
J
T
9.5
mV/°C
RATIO
LEVEL SHIFT, T = +25°C, 4.7nF in series with 50Ω loadings on CKV1, CKV2, CKVB1, CKVB2
A
V
V
Positive Supply Voltage
Negative Supply Voltage
25
-15
105
40
V
V
ON
-25
OFF
CPV
F
Operating Frequency on CPV1, CPV2
Inputs
166
332
kHz
F
Operating Frequency on OE Input
210
kHz
OE
FN6684.0
April 14, 2008
4
ISL97648
Electrical Specifications VDD = V = 3.3V, A
= 12V, V
= 20V, V = -14V, T from -40°C to +85°C, Fcpv1 and Fcpv2 = 105kHz,
OFF A
IN
VDD
ON
unless otherwise specified. Unless otherwise specified, parts are 100% tested at +25°C. Temperature limits
established by characterization and are not production tested. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
I
I
VDD Average Supply Current
CPV1 = CPV2 = 0, STV = 0, OE = 105kHz
500
1000
µA
DD
(V
AVDD
< 4V)
CPV1 Input Current
CPV2 Input Current
STV1 Input Current
STV2 Input Current
OE Input Current
CPV1 = 1
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
-0.1
-1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
1
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
V
CPV1
CPV2
STV1
STV2
OE
CPV1 = 0
I
I
I
I
I
I
CPV2 = 1
CPV2 = 0
STV1 = 1
STV1 = 0
STV2 = 1
STV2 = 0
OE = 1
OE = 0
OECON Input Current
OE = 1
OECON
OE = 0
-1
1
VDD Quiescent Current (V
< 4V) CPV1 = CPV2 = 0, STV = 0, OE = 0
< 4V) CPV1 = CPV2 = 0, STV = 0, OE = 0
< 4V) CPV1 = CPV2 = 0, STV = 0, OE = 0
Activation threshold
250
700
600
500
1100
1000
13
VDD
AVDD
AVDD
AVDD
IV
IV
V
V
Quiescent Current (V
Quiescent Current (V
ON_quiescent
OFF_quiescent
ON
ON
UVLO
UVLO on VON
De-activation threshold
10
V
V
V
Level Shift
Level Shift
Low Input Voltage CPV1, CPV2, STV,
OE
0.4
V
IL
High Input Voltage CPV1, CPV2, STV,
OE
70% V
1.6
V
IH
DD
V
V
OECON Threshold Voltage
STV = 0, OE = 3.3V
No load
1.7
V
V
threshold
Level Shift Low Output Voltage CKV1, CKV2,
CKVB1, CKVB2, STVP
-13.5
OL
V
Level Shift High Output Voltage CKV1, CKV2,
CKVB1, CKVB2, STVP
No load
19.5
V
OH
t _CKV
CKV Rise Time
CKV Fall Time
STVP Rise Time
CKV rise time from +6V to +17V
CKV fall time from 0V to -11V
STVP rise time from -7V to +13V, C
0.73
0.73
0.5
µs
µs
µs
r
t _CKV
f
t _STVP
= 4.7nF
= 4.7nF
r
LOAD
and in series with R
LOAD
= 200Ω
t _STVP
STVP Fall Time
STVP fall time from +13V to -7V, C
and in series with R = 200Ω
0.28
µs
f
LOAD
LOAD
t -OE-CKV+
CKV Rising Edge Delay Time
CKV Falling Edge Delay Time
STVP Rising Edge Delay Time
STVP Falling Edge Delay Time
CKV_CS Rising Edge Delay Time
CKV_CS Falling Edge Delay Time
OE rising above 1.65V to CKV crossing + 11.5V
OE rising above 1.65V to CKV crossing - 5.5V
STV crossing 1.65V to STVP crossing + 3V,
OE rising above 1.65V to CKV crossing - 5.5V
CPV falling below 1.65V to CKV crossing - 11V
CPV falling below 1.65V to CKV crossing + 17V
0.68
0.68
0.48
0.35
2.44
2.44
µs
µs
µs
µs
µs
µs
d
t -OE-CKV-
d
t -STVP+
d
t -STVP-
d
t -CKV-CS+
1.6
1.6
d
t -CKV-CS-
d
2
I C DC SPECIFICATION A
= 10V, V
= 5V, R
= 24.9kΩ
SET
VDD
OUT
A
A
Supply Range
Supply Current
DD
VDD range 2.6V to 3.6V
VDD range 2.25V to 3.6V
(Note 5)
4.5
4.5
18
13
V
V
VDD
VDD
-I
V
50
µA
DD_DCP
FN6684.0
April 14, 2008
5
ISL97648
Electrical Specifications VDD = V = 3.3V, A
= 12V, V
= 20V, V = -14V, T from -40°C to +85°C, Fcpv1 and Fcpv2 = 105kHz,
OFF A
IN
VDD
ON
unless otherwise specified. Unless otherwise specified, parts are 100% tested at +25°C. Temperature limits
established by characterization and are not production tested. (Continued)
PARAMETER
DESCRIPTION
AVDD Supply Current
CONDITIONS
MIN
TYP
25
7
MAX
UNIT
µA
I
(Note 3)
AVDD_DCP
SET
SET
SET
SET
SET Voltage Resolution
SET Differential Non-linearity
SET Zero-Scale Error
SET Full-Scale Error
SET Current
Bits
LSB
LSB
LSB
µA
VR
Monotonic Over-Temperature
±1
±2
±8
DN
ZSE
FSE
ISET
SET
Through R
SET
(Note 6)
= 18V
20
SET External Resistance
To GND, A
To GND, A
(Note 4)
10
200
45
kΩ
ER
VDD
VDD
= 4.5V
2.25
kΩ
A
to SET
A
to SET Voltage Attenuation
1:20
8
V/V
µs
VDD
VDD
OUT
OUT Settling Time
OUT Voltage Range
To ±0.5 LSB Error Band (Note 4)
(Note 4)
St
OUT
V
VSET +
0.5V
AVDD
V
SET
VD
SET Voltage Drift
<10
mV
V
VIH
SDA, SCL, SCL_S, WPn Input Logic
High
0.7*
VDD
S
VIL
SDA, SCL, SCL_S, WPn Input Logic
Low
0.3*
VDD
V
S
SDA, SCL, SCL_S, WPn Hysteresis (Note 4)
WPn IL
0.22*VDD
30
V
µA
V
IL
37
WPN
VOH
SDA, SCL Output Logic High
SDA, SCL Output Logic Low
WPp Output Logic High
WPp Output Logic Low
WPp Delay
@ 3mA
@ 3mA
@ 3mA
@ 3mA
0.4
S
VOL
0.4
V
S
VOH
VDD - 0.4
0.4
V
WPP
WPP
VOL
V
t
100
75
ns
Ω
DWPP
R
SCL_S to SCL ON-resistance
Delay From SCL_S to SCL
SCL
t
60
ns
S
2
I C
F
SCL Clock Frequency
0
0.6
1.3
0
400
50
kHz
µs
µs
ns
ns
ns
ns
SCL
2
t
t
t
t
t
t
I C Clock High Time
SCH
SCL
DSP
SDS
SDH
ICR
2
I C Clock Low Time
2
I C Spike Rejection Filter Pulse Width
2
I C Data Set-up Time
100
0
2
I C Data Hold Time
900
2
I C SDA, SCL Input Rise Time
Dependent on Load (Note 4)
(Note 4)
20 +
0.1*Cb
1000
2
t
t
I C SDA, SCL Input Fall Time
20 +
0.1*Cb
300
ns
µs
ICF
2
I C Bus Free Time Between Stop and
1.3
BUF
Start
2
t
t
t
I C Repeated Start Condition Set-up
0.6
0.6
0.6
µs
µs
µs
pF
pF
STS
STH
SPS
2
I C Repeated Start Condition Hold
2
I C Stop Condition Set-up
2
Cb
I C Bus Capacitive Load
(Note 4)
(Note 4)
400
10
C
Capacitance on SDA
SDA
FN6684.0
April 14, 2008
6
ISL97648
Electrical Specifications VDD = V = 3.3V, A
= 12V, V
= 20V, V = -14V, T from -40°C to +85°C, Fcpv1 and Fcpv2 = 105kHz,
OFF A
IN
VDD
ON
unless otherwise specified. Unless otherwise specified, parts are 100% tested at +25°C. Temperature limits
established by characterization and are not production tested. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
WPn = 0 (Note 4)
WPn = 1 (Note 4)
MIN
TYP
MAX
10
UNIT
pF
C
Capacitance on SCL, SCL_S
S
22
pF
t
Write Cycle Time
100
ms
W
NOTES:
3. Tested at A
= 18V.
VDD
4. Limits established by characterization and are not production tested.
5. Simulated maximum current draw when programming EEPROM is 23mA, should be considered when designing Power Supply.
6. A typical current of 20µA is calculated using the A
= 10V and R
= 24.9kΩ. The maximum suggested SET Current should be 120µA.
SET
VDD
Timing Diagrams
3.3V
OE
1.65V
0V
3.3V
1.65V
0V
CPV
17V
11.5V
6V
17V
CKV_CS-
t
OE_CKV+
d_
t
OE_CKV-
d_
t
d_
CKV
0V
t
CKV
r_
t
CKV_CS+
d_
-5.5V
-11V
-11V
t
CKV
r_
FIGURE 1. TIMING DIAGRAM OF OE, CPV, AND CKV
3.3V
1.65V
STV
0V
13V
13V
t
STVP+
d_
t
STVP-
d_
STVP
3V
3V
-7V
t
STVP
r_
t
STVP
r_
FIGURE 2. TIMING DIAGRAM OF STV AND STVP
FN6684.0
April 14, 2008
7
ISL97648
Typical Application Diagram
µF
µF
µH
2kΩ
µF
µF
10Ω
4.7µF
100nF
µF
µF
µF
µF
FN6684.0
April 14, 2008
8
ISL97648
Pin Descriptions
PIN NUMBER
PIN NAME
CKVCS1
CKVBCS1
CKVB1
STVP1
STVP2
CKVB2
CKVBCS2
CKVCS2
CKV2
DESCRIPTION
1
2
Discharge switch input 1, CKV1 charge share
Discharge switch input 1, CKVB1 charge share
High voltage output 1 , scan clock even
High voltage output 1, scan start pulse 1
High voltage output 2, scan start pulse 2
High voltage output 2, scan clock even
Discharge switch input 2, CKVB2 charge share
Discharge switch input 2, CKV2 charge share
High voltage output 2, scan clock odd
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
STV1
V
V
timing, V
timing, V
timing, H
timing, H
timing, H
SYNC
SYNC1
SYNC2
SYNC
SYNC
SYNC
STV2
SYNC
CPV1
H
H
H
clock 1
clock 2
clock 3
SYNC
SYNC
SYNC
CPV2
OE
OECON
LGND
DISH
OE disable input, OE blank
Logic GND
Discharge function input, V
discharge
OFF
VDD
Logic power supply for scan driver and module calibrator
Write Protection Active Low. CMOS Level.
Serial Clock Input.
WPn
SCL_S
SCL
Serial Clock Input for internal and inter-IC use.
2
SDA
I C Serial Data Input/Output.
WPp
Write Protection Active High. CMOS Level.
RSET
Maximum Sink Current Adjustment Point. Connect a resistor from SET to GND to set the maximum
adjustable sink current of the OUT pin. The maximum adjustable sink current is equal to (AVDD/20)
divided by RSET.
25
OUT
Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times
the maximum adjustable sink current divided by 128. See SET pin function description for the maxim
adjustable sink current setting.
26
27
28
29
30
31
32
33
34
35
36
37
IN1+
IN1-
Op amp 1 non-inverting input
Op amp 1 inverting input
Op amp 1 output
VCOM1
IN2+
Op amp 2 non-inverting input
Op amp 2 inverting input
Op amp 2 output
IN2-
VCOM2
IN3+
Op amp 3 non-inverting input
Op amp 3 inverting input
Op amp 3 output
IN3-
VCOM3
IN4+
Op amp 4 non-inverting input
Op amp 4 inverting input
Op amp 4 output
IN4-
VCOM4
FN6684.0
April 14, 2008
9
ISL97648
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
CGND
AVDD
TEST
SW1
DESCRIPTION
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
VCOM GND
VCOM amplifier positive supply pin
Test Pin
Boost switch output 1
Boost switch output 2
Boost ground pins
Boost ground pins
Boost supply voltage
Chip Enable
SW2
PGND1
PGND2
VIN
EN
AGND
COMP
FB
Analog GND
Boost compensation pin
A
boost feedback pin
VDD
RHVS
HVS
Voltage set pin for HVS test
High-voltage stress input select pin
Temperature sensor output voltage
Negative supply
TEMP
VOFF
SGND
VON
Scan driver GND
Positive supply
CKV1
High voltage output 1 , scan clock odd
Typical Performance Curves
95
90
85
95
90
85
80
75
70
65
60
5.0V V TO 15.7V V
IN
OUT
5.0V V TO 10.7V V
IN
OUT
80
75
70
65
60
3.3V V TO 10.7V V
IN OUT
3.3V V TO 15.7V V
IN
OUT
0
200
400
600
(mA)
800
1000
0
100
200
300
(mA)
400
500
I
I
OUT
OUT
FIGURE 3. BOOST EFFICIENCY @ VIN = 5V
FIGURE 4. BOOST EFFICIENCY @ VIN = 3.3V
FN6684.0
April 14, 2008
10
ISL97648
Typical Performance Curves (Continued)
0.20
0.15
0.10
0.05
0
0.20
0.15
0.10
V
= 3.3V
IN
V
= 5.0V
IN
V
= 3.3V
IN
0.05
0
V
= 5.0V
600
IN
-0.05
-0.05
0
300
600
900
1200
0
200
400
(mA)
800
I
(mA)
I
OUT
OUT
FIGURE 5. BOOST LOAD REGULATION @ AVDD = 10.7V
FIGURE 6. BOOST LOAD REGULATION @ AVDD = 15.7V
CH4 = I
OUT
0.6
0.5
0.4
0.3
A
= 15.7V
VDD
0.2
0.1
0
A
= 10.7V
VDD
CH3 = A
VDD
(AC COUPLED)
2
3
4
5
V
(V)
IN
FIGURE 7. BOOST LINE REGULATION @ I
= 50mA
FIGURE 8. BOOST TRANSIENT RESPONSE
OUT
2500
2000
1500
1000
500
0
INPUT SIGNAL
OUTPUT SIGNAL
-50
-25
0
25
50
75
100 125 150 175
TEMPERATURE(°C)
FIGURE 10. TEMPERATURE SENSOR OUTPUT vs JUNCTION
TEMPERATURE
FIGURE 9. VCOM SLEW RATE
FN6684.0
April 14, 2008
11
ISL97648
Typical Performance Curves (Continued)
0.30
900
800
700
600
500
400
300
200
100
0
V
V
= 20V
ON
VDD = 3.3V
= -14V
0.25
0.20
0.15
0.10
0.05
0.00
= 14V
OFF
V
OFF
ALL INPUTS LOW
0
10
20
30
40
50
0.0
1.0
2.0
3.0
VDD (V)
4.0
5.0
V
(V)
ON
FIGURE 11. VDD SUPPLY CURRENT vs VDD
FIGURE 12. V
SUPLY CURRENT vs V
ON
ON
1400
800
600
400
200
0
V
= 20V
ON
1200
1000
800
600
400
200
0
VDD = 3.3V
= 20V
4700pF
V
= -14V
OFF
V
ON
R
= 500Ω
CS
ALL INPUTS LOW
2200pF
0
40k
80k
INPUT FREQUENCY (Hz)
120k
160k
-30
-25
-20
-15
-10
-5
0
V
(V)
OFF
FIGURE 14. LEVEL SHIFT POWER CONSUMPTION vs CPV
FREQUENCY
FIGURE 13. V
SUPPLY CURRENT vs V
OFF
OFF
5.40
5.20
5.00
4.80
3500
V
= 35V
ON
3000
2500
2000
1500
1000
500
V
= 20V
OFF
= 500Ω
4700pF
R
CS
R
R
R
A
= 100k
= 90.9k
4.60
4.40
4.20
4.00
1
2
= 24.3k
= 10V
SET
2200pF
VDD
20
0
0
40
60
80
100
120
0
40k
80k
120k
160k
SETTING
INPUT FREQUENCY (Hz)
FIGURE 15. LEVEL SHIFT POWER CONSUMPTION vs CPV
FREQUENCY
FIGURE 16. V
vs SETTING
OUT
FN6684.0
April 14, 2008
12
ISL97648
ripple current will be from 0 to the threshold of the current
Application Information
limit. In turn, the bigger ripple current will increase the output
voltage ripple. Hence, it will need more output capacitors to
keep the output ripple at the same level. When the input
voltage equals, or is larger than, the output voltage, the
boost converter will stop switching. The boost converter is
not regulated any more, but the part will still be on and other
channels are still regulated.
A
Boost Converter
VDD
The AVDD boost converter features a fully integrated 2.7A
boost FET. The regulator uses a current mode, PI control
scheme which provides good line regulation and good
transient response. A network connected to the COMP pin is
used to compensate the device. In normal operation the
output voltage is set using a resistor divider to the feedback
pin FBB. The feedback reference voltage is set is to 1.23V.
Boost Converter Input Capacitor
An input capacitor is used to suppress the voltage ripple
injected into the boost converter. A ceramic capacitor with
capacitance larger than 10µF is recommended. The voltage
rating of input capacitor should be larger than the maximum
input voltage. Some capacitors are recommended in Table 1
for input capacitor.
In continuous current mode, current flows continuously in the
inductor during the entire switching cycle in steady state
operation. The voltage conversion ratio in continuous current
mode is given by Equation 1:
V
1
BOOST
(EQ. 1)
-----------------------
-------------
=
V
1 – D
IN
TABLE 1. BOOST CONVERTER INPUT CAPACITOR
RECOMMENDATION
Where D is the duty cycle of the switching MOSFET.
CAPACITOR
10µF/25V
SIZE
VENDOR
PART NUMBER
C3225X7R1E106M
GRM32DR61E106K
The boost converter uses a summing amplifier architecture
consisting of gm stages for voltage feedback, current
feedback and slope compensation. A comparator looks at
the peak inductor current cycle by cycle and terminates the
PWM cycle if the current limit is reached.
1210 TDK
10µF/25V
1210 Murata
Boost Inductor
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60kΩ is recommended.
The boost converter output voltage is determined by
Equation 2:
The boost inductor is a critical part which influences the
output voltage ripple, transient response, and efficiency.
Values of 3.3µH to 10µH should be selected to match the
internal slope compensation. The inductor must be able to
handle the following average and peak current shown in
Equations 5 and 6:
I
O
(EQ. 5)
-------------
I
I
=
LAVG
1 – D
ΔI
L
--------
+
(EQ. 6)
= I
R
+ R
2
LPK
LAVG
1
2
(EQ. 2)
--------------------
V
=
× V
BOOST
FB
R
2
Some inductors are recommended in Table 2.
The current through the MOSFET is limited to 2.7A
.
TABLE 2. BOOST INDUCTOR RECOMMENDATION
PEAK
This restricts the maximum output current (average) based
on Equation 3:
DIMENSIONS
INDUCTOR
(mm)
VENDOR
PART NUMBER
ΔI
V
IN
V
O
L
(EQ. 3)
⎛
⎝
⎞
⎠
--------
---------
6.8µH/
7.3x6.8x3.2 TDK
RLF7030T-6R8N3R0
I
=
I
–
LMT
×
OMAX
2
3A
PEAK
6.8µH/
2.9A
Where ΔIL is peak-to-peak inductor ripple current, and is set by
7.6X7.6X3.0 Sumida
10x10.1x3.8 Cooper
CDR7D28MNNP-6R8NC
CD1-5R2
Equation 4:
PEAK
5.2µH/
4.55A
V
D
f
S
IN
(EQ. 4)
--------- ----
ΔI
=
×
L
L
Bussmann
PEAK
where f is the switching frequency.
s
Rectifier Diode (Boost Converter)
The minimum boost duty cycle of the ISL97648 is ~20% for
1.4MHz. When the operating duty cycle is lower than the
minimum duty cycle, the part will not switch in some cycles
randomly, which will cause some LX pulses to be skipped. In
this case, LX pulses are not consistent any more, but the
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The reverse
voltage rating of this diode should be higher than the
maximum output voltage. The rectifier diode must meet the
output current and peak inductor current requirements.
output voltage (A
) is still regulated by the ratio of R and
VDD
1
R . Because some LX pulses are skipped, the ripple current
2
in the inductor will become bigger. Under the worst case, the
FN6684.0
April 14, 2008
13
ISL97648
Table 3 shows some recommendations for boost converter
diode.
HVS Operation
When the HVS input is taken high, the ISL97648 enters HVS
test mode. In this mode, the output of A is increased by
TABLE 3. BOOST CONVERTER RECTIFIER DIODE
RECOMMENDATION
VDD
switching RSET-HVS to ground to select the test voltage.
V /I
R AVG
Fault Protection
DIODE
SS23
SL23
RATING
30V/2A
30V/2A
PACKAGE
SMB
VENDOR
The ISL97648 integrates OVP, OCP and over-temperature
protection.
Fairchild Semiconductor
Vishay Semiconductor
SMB
Temperature Sensor
The ISL97648 also includes a temperature output for use in
system thermal management control. The integrated sensor
measures the die temperature over the 0°C to +150°C
range. Output is in the form of an analog voltage on the
TEMP pin in the range of 0.5V to 2.0V. Temperature
accuracy is ±5°C.
Output Capacitor
The output capacitor supplies the load directly and reduces
the ripple voltage at the output. Output ripple voltage consists
of two components: the voltage drop due to the inductor ripple
current flowing through the ESR of output capacitor, and the
charging and discharging of the output capacitor, as shown in
Equation 7.
Soft-Start
The ISL97648 integrates the soft-start function and the
timing diagram is shown in the Figure 17. The boost switch
goes through soft-start sequence after the EN pin is pulled to
high.
V
– V
I
O
1
f
s
O
IN
(EQ. 7)
----------------------- ------------------- ---
V
= I
× ESR +
LPK
×
×
RIPPLE
V
C
O
AVDD
For low ESR ceramic capacitors, the output ripple is
dominated by the charging and discharging of the output
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
EN
Note: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across then
increases. C
of the capacitor at a particular voltage and not the
manufacturer's stated value, measured at 0V.
in Equation 7 assumes the effective value
OUT
I
OCP
I
SWITCH
Table 4 shows some selections of output capacitors.
TABLE 4. BOOST OUTPUT CAPACITOR RECOMMENDATION
t
SS
I
/8
CAPACITOR
10µF/25V
SIZE
VENDOR
PART NUMBER
C3225X7R1E106M
GRM32DR61E106K
OCP
1210 TDK
FIGURE 17. BOOST SOFT-START OF CURRENT LIMIT
10µF/25V
1210 Murata
High Performance VCOM Amplifiers
Loop Compensation (Boost Converter)
The VCOM Amplifiers are designed to control the voltage on
the back plate of an LCD display or to drive the repaired
column lines. The plate is capacitive coupled to the pixel
drive voltage which alternately cycles positive and negative
at the line rate for the display. Thus, the amplifier must be
capable of sourcing and sinking capacitive pulses of current,
which can occasionally be quite large (a few 100mA for
typical applications).
The boost converter of ISL97648 can be compensated by a
RC network connected from VC pin to ground. C = 4.7nF
C
and R = 10k RC network is used in the demo board. A
C
higher resistor value can be used to lower the transient load
change A
overshoot (however, this may be at the
VDD
expense of stability to the loop).
The stability can be examined by repeatedly changing the
load between 100mA and a max level that is likely to be
The ISL97648 VCOM Amplifier’s output current is limited to
150mA. This limit level, which is roughly the same for
sourcing and sinking, is included to maintain reliable
operation of the part. It does not necessarily prevent a large
temperature rise if the current is maintained (in this case the
whole chip may be shut down by the thermal trip to protect
functionality.) If the display occasionally demands current
pulses higher than this limit, the reservoir capacitor will
provide the excess and the amplifier will top the reservoir
used in the system being used. The A
voltage should be
VDD
examined with an oscilloscope set to AC 100mV/div and the
amount of ringing observed when the load current changes.
Reduce excessive ringing by reducing the value of the
resistor in series with the COMP pin capacitor.
FN6684.0
April 14, 2008
14
ISL97648
AVDD
VCOM
COLUMN DRIVER
STVP1
CKV1
CKVCS1
CKVB1
CKVBCS1
CKV2
STV1
STV2
CPV1
VIDEO
SOURCE
ISL97648
CPV2
OE
CKVCS2
CKVB2
CKVBCS2
STVP2
FIGURE 18. SYSTEM BLOCK DIAGRAM RELATED TO LEVEL SHIFT OUTPUT
capacitor back up once the pulse has stopped. This will
happen on the µs time scale in practical systems and for
Output Signals
The output signals, CKV and CKVB are generated by
ISL97648 internal switches. Figure 19 depicts the simplified
schematic of the output stage and interface.
pulses 2x or 3x the current limit, the V
voltage will have
COM
settled again before the next line is processed.
Level Shifter
C capacitors model the capacitive loading appeared at the
L
inputs of the TFT-LCD panel for the CKV1, CKVB1, CKV2,
GENERAL DESCRIPTION
and the CKVB2 signals. The C is typically between 1nF and
L
The ISL97648 is a high performance 65V TFT-LCD level
shifter. It level shifts TTL level timing signals from the video
source into 65V peak-to-peak output voltage. Its output is
capable of delivering 100mA peak current into 5nF of
capacitive load. It also incorporates logic to control the
output timings. The logic timing control circuit is powered
rom VDD supply. Figure 18 shows the system block diagram
related to level shifter part.
5nF.
In addition to switches SW1, SW2, SW3, SW4, SW5, SW6,
SW7, and SW8, the ninth and tenth switches are added to
reduce the power dissipation and shape the output
waveform. Figure 19 shows the location of the additional
SW9 and SW10 switches.
Input Signals
The device performs beside of level transformation also logic
operation between the input signals:
• STV1 - Vertical Sync Timing signal 1, frequency range
from 60Hz to 120Hz
• STV2 - Vertical Sync Timing signal 2, frequency range
from 60Hz to 120Hz
• CPV1- Horizontal Sync Timing signal 1, frequency range
up to 166kHz
• CPV2- Horizontal Sync Timing signal 2, frequency range
up to 166kHz
• OE- Output Enable Write Signal, frequency range up to
332kHz
FN6684.0
April 14, 2008
15
ISL97648
.
Step 1: Generation of internal clock from the inputs,
CLK = CPV ⊕ (OE ⊗ OECON)
OECON = Low( STV = High)
OECON = Hi – Z( STV = Low)
TABLE 5. CLK SIGNAL GENERATION
CPV
0
OE
0
OECON
CLK
0
1
0
1
0
1
0
1
0
0
1
0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Step 2: The CLK clock dries a flip-flop with complementary
output Q and Q. The flip-flop is reset by STV signal.
FIGURE 19. SIMPLIFIED SCHEMATIC OF OUTPUT STAGE
In reality, each switch consists of two such switches, one for
the positive discharge and one for the negative discharge,
see Figure 20..
TABLE 6. INTERNAL FLIP-FLOP OUTPUTS
CLK
0 --> 1
X
STV
0
Q
Q(N-1)
0
Q
Q(N-1)
1
SW9
1
CKVCS1
CKVCS2
SW9
CKVBCS1
CKVBCS2
Step 3: The 2 complementary outputs CKV and CKVB can
be high, low or high-impedance, as shown in Table 7:
SW10
TABLE 7. CKV, CKVB, CKVCS AND CKVBCS
CLK
Q
0
1
0
1
0
1
0
1
STV
0
CKV
Hi-Z
Hi-Z
Low
High
NA
CKVB
Hi-Z
Hi-Z
High
Low
NA
SW10
0
0
1
1
0
0
1
1
FIGURE 20. BI-DIRECTIONAL SWITCHES
0
0
Due to the actual solid-state construction of the switches, the
capacitors C does not get discharged entirely. The amount
of left over charges depends on the value of the voltages of
0
L
1
V
and V on the capacitors.
OFF
ON
1
Low
NA
High
NA
1
Internal Logic Block Diagram
1
High
Low
Figure 21 shows the internal block diagram. In order to
reduce power dissipation, most of the logic circuitry is
powered from VDD logic supply. The output of the VDD logic
is level-shifted to drive the output switches.
Hi-Z is output high impedance and charge sharing is
enabled. NA is illegal state and cannot occur.
Internal Logic Table
STVP
STVP output is controlled by STV input and the internal CLK
signal. Table 8 shows the relationship:
CKV, CKB, CKVCS AND CKVBCS
The Internal logic block of CKV1 and CKV2 are identical and
only one logic block and truth table are shown in Figure 21
and Table 5. To generate the CKV, CKVB and charge
sharing outputs, the internal logic goes through 3 steps as
outlined in the following paragraphs.
TABLE 8. STVP OUTPUT
CLK
STV
STVP
Low
0
0
1
1
0
1
0
1
High
Low
Hi-Z
FN6684.0
April 14, 2008
16
ISL97648
FIGURE 21. INTERNAL LOGIC BLOCK DIAGRAM
FN6684.0
April 14, 2008
17
ISL97648
Output Waveforms
Power Dissipation
The dissipated power of chagrge sharing in R and R could
Figure 22 shows a typical CKV and CKVB output
1
2
waveforms. The output droop rate depends on the external
discharge resistor value and the output capacitor load.
be calculated as follows:
We assume that:
CKV
• V
• V
• H
= 40V
ON
= -20V
OFF
timing (CPV); frequency = 60kHz
SYNC
• C = 5nF
L
The value of V , the left over voltage in the capacitors in that
L
case is 23V for the positive discharge and 3.0V for the
CKVB
negative discharge.
The voltage change across the capacitor is therefore 23V
(see Figure 25).
FIGURE 22. CKV AND CKVB OUTPUT WAVEFORMS
The stored energy in the capacitor is shown in Equation 8:
2
2
-9
(EQ. 8)
1/2 × V C = 1/2 × 23 × 5 × 10 = 1.32μW
CKV
CKVB
The energy which is stored in the capacitor will be
dissipated on the resistor (see Figure 26). The switch will
close 60,000 in every second.
Since the process will be repeated 2x, for the CKV and the
CKVB. In 60,000 cycles per second the power dissipation in
CPV
R and R becomes Equation 9.
1
2
(EQ. 9)
-6
3
2 × 1.32 × 10 × 60x10 = 160mW
FIGURE 23. CPV TO CKV/CKVB DELAY
The dissipated power of level shift driving in R and R
la
could be calculated as follows:
Figure 23 shows the delay time between the incoming
horizontal sync timing pulse CPV and the generated output
lb
pulses. Δt is dependent mainly on the value of C . Figure 24
shows the effect of STV..
L
The voltage change across the capacitor is 37V when the
level shift driving the capacitor to V
(see Figure 27).
or V
OFF
ON
CKV
The stored energy in the capacitor is calculated in
Equation 10:
CKVB
2
2
-9
(EQ. 10)
1/2 × V C = 1/2 × 37 × 5 × 10 = 3.42μW
Consequently, in 60,000 cycles per second the power
dissipation in R and R becomes Equation 11:
STV
la
lb
-6
3
(EQ. 11)
2 × 3.42 × 10 × 60x10 = 410mW
CPV
Since there are also the same power consumption at R , R ,
3
4
FIGURE 24. EFFECT OF STV
R
and R , the total power dissipation is Equation 12:
ld
lc
2x(410 + 160)= 1140mW
(EQ. 12)
Auxiliary Functions
DISH: It discharges V
when the logic power voltage level
OFF
drops out, when 'DISH' is < -0.6V (V
Figures 25, 26, 27, and 28 show the total power dissipation
over a range of possible voltages, operating frequencies and
system power turns
CC
is connected to ground level by 1kΩ.
off), V
OFF
loads. The values of the R and R must be selected such
1
2
OECON: It provides continuos polarity changes to the
TFT-LCD panel during the vertical blanking.
that the capacitor C is discharged via R or R resistor in
L
1
2
one half period of the H
timing. Care should be taken to
SYNC
prevent the power from exceeding the maximum rating of
the package.
FN6684.0
April 14, 2008
18
ISL97648
+40V
SW
23V
R
1
2
+17V
3.0V
C
23V
23V
-20V
FIGURE 25. VOLTAGE CHANGE ACROSS THE CAPACITOR
FIGURE 26. ENERGY DISSIPATED ON THE RESISTOR WHEN
CHARGE SHARING
WHEN CHARGE SHARING BETWEEN CKV AND
CKVB
+40V
SW
37V
R
1
2
+17V
3.0V
C
37V
37V
-20V
FIGURE 27. VOLTAGE CHANGE ACROSS THE CAPACITOR
WHEN DRIVING
FIGURE 28. ENERGY DISSIPATED ON THE RESISTOR WHEN
DRIVING
2
I C LCD Module Calibrator
Truth Table
TABLE 9. DVR WRITE PROTECTION TRUTH TABLE
OUTPUT
REGISTER
INPUT
WPn
SCL_S
SCL
WPp
EEPROM
LOW
UNUSED
INPUT
HIGH
Write Protect
Write Protect
HIGH
CONNECTED TO CONNECTED TO
LOW
LOW to HIGH
HIGH
Writeable
Writeable
SCL
SCL_S
HIGH to LOW
DISCONECTS
FROM SCL
DISCONECTS
FROM SCL_S
EEPROM is Read into
Register
EEPROM is Read into
Register
FLOAT
(Pull-Down Resistor
Included)
UNUSED
INPUT
Write Protect
Write Protect
NOTE: When the device is not write-protected SCL_S and SCL signals should not be driven at the same time. When SCL_S signal is “Unused”
should be left floating.
FN6684.0
April 14, 2008
19
ISL97648
2
I C Bus Format
W
A
START
SLAVE ADDRESS
DATA
A
STOP
R
1
0
0
1
1
1
1
D6 D5 D4 D3 D2 D1 D0
P
P: PROGRAM
SCL
SDA
0
0
RW
D6
D5 D4
D3 D2 D1 D0
P
A
START
STOP
When Read Operation, don’t care P.
P = 1: Register Writing
P = 0: EEPROM Writing (Program)
Adjustable Sink Current Output
Output Connection
The device provides an output sink current which lowers the
voltage on the external voltage divider. Equations 13 and 14
control the output. See Figure 29.
This device provides the ability to reduce the flicker of an
LCD panel by adjustment of the VCOM voltage during
production test and alignment. A 128-step resolution is
provided under digital control, which adjusts the sink current
of the output. The output is connected to an external voltage
divider, so that the device will have the capability to reduce
the voltage on the output by increasing the output sink
current (see Figure 29).
Setting
128
AVDD
20(RSET)
(EQ. 13)
-------------------- ----------------------------
IOUT =
X
R2
----------------------
Setting
128
R1
20(RSET)
⎛
⎝
⎞
⎠
⎛
⎞
⎠
-------------------- ----------------------------
VOUT =
VAVDD 1 –
X
(EQ. 14)
⎝
R1 + R2
AVDD
AVDD
Note: Where setting is an integer between 1 and 128.
ISL97648
Ramp-up of the VDD Power Supply
R
1
-
+
It is required that the ramp-up from 10% VDD to 90% VDD
level be achieved in less than or equal to 10ms to assure
that the EEPROM and Power-on-reset circuits are
synchronized and the correct value is read from the
EEPROM Memory.
OUT
SET
R
2
R
SET
FIGURE 29. OUTPUT CONNECTION CIRCUIT EXAMPLE
2
The adjustment of the output is provided by the 2-wire I C
serial interface.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6684.0
April 14, 2008
20
ISL97648
Package Outline Drawing
L56.8x8D
56 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 04/07
4X
6.5
8.00
0.50
52X
A
6
B
56
43
PIN #1 INDEX AREA
1
42
6
PIN 1
INDEX AREA
6 . 50 ± 0 . 15
29
14
(4X)
0.15
28
15
0.10 M C A B
56X 0 . 4 ± 0 . 1
4
0.25 +0.05 / -0.07
b
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
PACKAGE OUTLINE
0.10
C
C
0 . 75
BASE PLANE
SEATING PLANE
0.08
C
SIDE VIEW
( 7 . 8 TYP )
(
6 . 5 )
( 52X 0 . 5 )
5
C
0 . 2 REF
( 56X 0 . 25 )
( 56X 0 . 6 )
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6684.0
April 14, 2008
21
相关型号：
ISL97648IRTZ-TK
LIQUID CRYSTAL DISPLAY DRIVER, PQCC56, 8 X 8 MM, ROHS COMPLIANT, PLASTIC, TQFN-56
RENESAS
©2020 ICPDF网 联系我们和版权申明