ISL97649AIRTZ-EVALZ [INTERSIL]
TFT-LCD Supply + DCP + VCOM Amplifier + Gate Pulse Modulator + RESET; TFT -LCD电源+ DCP + VCOM放大器+栅极脉冲调制器+ RESET
| 型号： | ISL97649AIRTZ-EVALZ |
| 厂家： | 
Intersil |
| 描述： | TFT-LCD Supply + DCP + VCOM Amplifier + Gate Pulse Modulator + RESET |
| 文件： | 总20页 (文件大小：1004K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TFT-LCD Supply + DCP + VCOM Amplifier + Gate Pulse
Modulator + RESET
ISL97649A
Features
The ISL97649A is an integrated power management IC (PMIC) for
TFT-LCDs used in notebooks, tablet PCs, and monitors. The device
• 2.5V to 5.5V Input
• 1.5A Integrated Boost for up to 15V A
VDD
integrates a boost converter for generating A , an LDO for
VLOGIC. VON and VOFF are generated by a charge pump driven by
the switch node of the boost. The ISL97649A also includes a V
slice circuit, reset function, and a high performance VCOM
amplifier with DCP (Digitally Controlled Potentiometer) that is
used as a VCOM calibrator.
VDD
• V /V
ON OFF
Supplies Generated by Charge Pumps Driven By
the Boost Switch Node
ON
• LDO for VLOGIC Channel
• 600/1200kHz Selectable Switching Frequency
• Integrated Gate Pulse Modulator
• Reset Signal Generated by Supply Monitor
• Integrated VCOM Amplifier
• DCP
The AVDD boost converter features a 1.5A/0.18Ω boost FET with
600/1200kHz switching frequency.
The logic LDO includes a 350mA FET for driving the low voltage
needed by external digital circuitry.
2
- I C Serial Interface, Address: 0101000, MSB Left
The gate pulse modulator can control the gate voltage up to 30V,
and both the rate and slew delay times are selectable.
- Wiper Position Stored in 8-bit Nonvolatile Memory and
Recalled on Power-up
The supply monitor generates a reset signal when the system is
powered down.
- Endurance, 1,000 Data Changes Per Bit
• UVLO, UVP, OVP, OCP, and OTP Protection
• Pb-Free (RoHS Compliant)
• 28 Ld 4x5 QFN
2
It provides a programmable VCOM with I C interface. One VCOM
amplifier is also integrated in the chip. The output of the VCOM is
powered up with the voltage at the last programmed 8-bit
EEPROM setting.
Applications
• LCD Notebook, Tablet, and Monitor
Pin Configuration
ISL97649A
(28 LD 4x5 QFN)
TOP VIEW
28
27
26
25
24
23
FB
PGND
CE
L_IN
1
2
3
4
5
6
7
8
22
21
20
CD2
L_OUT
RESET
ADJ
RE
19
18
17
16
15
GND
THERMAL
PAD
VGH
VGHM
VFLK
VDPM
VDIV
NEG
VOUT
9
10
11
12
13
14
December 5, 2011
FN7928.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL97649A
Application Diagram
VIN
AVDD
AVDD
L1 10µH
LX
C1, 2
20µF
C4, 5, 6
30µF
D1
C7
0.1µF
SW
R1
73.2k
VIN
C32
0.1µF
PGND
AVDD BOOST
CONTROLLER
VIN
EN
SS
SEQUENCER
R2 8.06k
FREQ
FB
COMP
R12 5.5k
D4
C20 15nF
Q1
L_IN
VOFF
C16
LDO VIN
C25
1µF
VLOGIC
C15
1µF
C11
0.1µF
R6 1k
SW
1µF
Z1
L_OUT
VLOGIC
AVDD
LDO
C24
2.2µF
C8
47nF
C10
47nF
R17
8.25k
VON
R18
3.92k
C12
1µF
D2 C9
1µF
D3
VFLK
VGH
ADJ
C17 1nF
VDPM
C28
0.1µF
SCL
C14 100pF
CE
RE
GPM
R9
10k
SDA
RSET
POS
VGH GPM
R5 100k
DCP
VGHM
R22 22k
GPM_LO
133k
R8
AVDD
VGH
R7
83k
C18
0.47µF
R14 85k
R26 100k
VIN
AVDD
OUT
VDIV
AVDD
VCOM
VOLTAGE
DETECTOR
C19
0.47uF
OPEN
VCOM OP
NEG
R15 115k
CD2
C26 1nF
RESET
RESET
THERMAL PAD
R16
10k
VLOGIC
FN7928.0
December 5, 2011
2
ISL97649A
Pin Descriptions
PIN#
SYMBOL
DESCRIPTION
1
FB
AVDD boost converter feedback. Connect to the center of a voltage divider between AVDD and GND to set the AVDD voltage.
Power ground
2
PGND
CE
3
Gate Pulse Modulator Delay Control. Connect a capacitor between this pin and GND to set the delay time.
Gate Pulse Modulator Slew Control. Connect a resistor between this pin and GND to set the falling slew rate.
Gate Pulse Modulator High Voltage Input. Place a 0.1µF decoupling capacitor close to the VGH pin.
Gate Pulse Modulator Output for gate driver IC
4
RE
5
VGH
6
VGHM
VFLK
VDPM
7
Gate Pulse Modulator Control input from T
CON
8
Gate Pulse Modulator Enable. Connect a capacitor from VDPM to GND to set the delay time before GPM is enabled. A current
source charges the capacitor on VDPM.
9
GPM_LO Gate Pulse Modulator Low Voltage Input; place a 0.47µF decoupling capacitor close to the GPM_LO pin.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AVDD
SCL
DCP and VCOM amplifier high voltage analog supply; place a 0.47µF decoupling capacitor close to the AVDD pin.
2
I C comparable clock input
2
SDA
I C compatible serial bidirectional data line
POS
VCOM Positive Amplifier Non-inverting input
RSET
VOUT
NEG
DCP sink current adjustment pin; connect a resistor between this pin and GND to set the resolution of the DCP output voltage.
VCOM Amplifier output
VCOM Negative Amplifier Non-inverting input
VDIV
ADJ
Voltage detector threshold. Connect to the center of a resistive divider between V and GND.
IN
VLOGIC LDO feedback. Connect to the center of a resistive divider between L_OUT and GND to set V
voltage for T .
CON
Logic
RESET
L_OUT
CD2
Voltage detector reset output
LDO output. Connect at least one 1µF capacitor to GND for stable operation.
Voltage detector rising edge delay. Connect a capacitor between this pin and GND to set the rising edge delay.
LDO input. Connect a 1µF decoupling capacitor close to this pin.
L_IN
SS
Boost Converter Soft-Start. Connect a capacitor between this pin and GND to set the soft-start time.
COMP
Boost converter compensation pin. Connect a series resistor and capacitor between this pin and GND to optimize transient
response and stability.
25
FREQ
Boost Converter frequency select; pull it to logic high to operate boost at 1.2MHz. Connect this pin to GND to operate boost at
600kHz.
26
27
28
VIN
LX
IC input supply. Connect a 0.1µF decoupling capacitor close to this pin.
AVDD boost converter switching node
EN
AVDD enable pin
Ordering Information
PART NUMBER
PART
V
RANGE
(V)
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
IN
(Notes 2, 3)
MARKING
ISL97649AIRZ (Note 1)
ISL97649AIRTZ-EVALZ
NOTES:
97649 AIRZ
2.5 to 5.5
-40 to +85
28 Ld 4x5 QFN
L28.4x5A
ISL97649A Evaluation Board
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97649A For more information on MSL please see techbrief TB363.
FN7928.0
December 5, 2011
3
ISL97649A
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Interface Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Rectifier Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Linear Regulator (LDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Supply Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Gate Pulse Modulator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VCOM Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DCP Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protocol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Communication with ISL97649A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Register Description: Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Register Description: IVP and WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Initial VCOM Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Start-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ISL97649A I2C EEPROM Reading/Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FN7928.0
December 5, 2011
4
ISL97649A
Absolute Maximum Ratings
Thermal Information
RE, VGHM, GPM_LO and VGH to GND . . . . . . . . . . . . . . . . . . . . -0.3 to +36V
LX, AVDD, POS, OUT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18V
Voltage Between GND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5V
All Other Pins to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0V
ESD Rating
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 1kV
Thermal Resistance (Typical)
28 Ld 4x5 QFN Package (Notes 4, 5). . . . .
θ
JA (°C/W)
38
θ
JC (°C/W)
4.5
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Functional Junction Temperature. . . . . . . . . . . . . . . . . . . .-40°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature During Soldering . . . . . . . . . . . . . . . . . . . . . . . . +260°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications
V
= ENABLE = 3.3V, A
VDD
= 8V, V
= 2.5V, V = 24V, V = - 6V. Boldface limits apply over the
ON OFF
IN
operating temperature range, -40°C to +85°C.
LDO
MIN
TYP
MAX
SYMBOL
GENERAL
VIN
PARAMETER
TEST CONDITIONS
(Note 6)
(Note 7)
(Note 6) UNITS
V
V
V
Supply Voltage Range
Supply Currents when Disabled
Supply Currents
2.5
3.3
390
0.7
0
5.5
500
1.0
V
IN
IN
IN
I
VIN < UVLO
µA
mA
µA
S_DIS
I
ENABLE = 3.3V, overdrive AVDD and VGH
ENABLE = 0V
S
I
ENABLE Pin Current
EBABLE
LOGIC INPUT CHARACTERISTICS - ENABLE, FLK, SCL, SDA, FREQ
V
Low Voltage Threshold
High Voltage Threshold
Pull-Down Resistor
0.65
1.65
V
V
IL
V
1.75
0.85
IH
R
Enable, FLK, FREQ
1.25
MΩ
IL
INTERNAL OSCILLATOR
Switching Frequencies
F
FREQ = low, T = +25°C
550
600
650
kHz
kHz
OSC
A
FREQ = high, T = +25°C
1100
1200
1300
A
AVDD BOOST REGULATOR
DAVDD/
DIOUT
AVDD Load Regulation
50mA < I
< 250mA
0.2
0.15
0.8
%
%
LOAD
DAVDD/
DVIN
AVDD Line Regulation
I
I
= 150mA, 2.5V < V < 5.5V
IN
LOAD
LOAD
V
Feedback Voltage (V
)
= 100mA, T = +25°C
0.792
0.808
100
V
nA
mΩ
A
FB
FB
A
I
FB Input Bias Current
Switch ON-resistance
Switch Current Limit
Max Duty Cycle
FB
r
T
= +25°C
180
1.5
90
230
DS(ON)
A
I
1.125
80
1.875
LIM
D
Freq = 1.2MHz
%
MAX
EFF
Freq = 1.2MHz, IAVDD = 100mA
91
%
FN7928.0
December 5, 2011
5
ISL97649A
Electrical Specifications
V
= ENABLE = 3.3V, A
VDD
= 8V, V
= 2.5V, V = 24V, V = - 6V. Boldface limits apply over the
ON OFF
IN
operating temperature range, -40°C to +85°C. (Continued)
LDO
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 6)
(Note 7)
(Note 6) UNITS
LDO REGULATOR
DV
DV
/
Line Regulation
ILDO = 1mA, 3.0V < V
< 5.5V
1
mV/V
%
LDO
IN1
IN
DV
/
Load Regulation
1mA < ILDO < 350mA
0.2
LDO
DI
OUT
V
Dropout Voltage
Output drops by 2%, ILDO = 350mA
Output drops by 5%
225
425
0.8
300
mV
mA
V
DO
I
Current Limit
330
LIML
V
ADJ Reference Voltage
ADJ Input Bias Current
I
= 50mA, T = +25°C
0.792
0.808
0.1
ADJ
ADJ
LOAD
A
I
µA
GATE PULSE MODULATOR
V
VGH Voltage
7
33
V
V
GH
V
VDPM Enable Threshold
VGH Input Current
1.13
1.215
125
1.30
IH_VDPM
I
VFLK = 0
µA
µA
V
VGH
RE = 100kΩ, VFLK = VIN
27.5
V
GPM_LO Voltage
2
VGH-2
2
GPM_LO
I
VGPM_LO Input Current
CE Threshold Voltage 1
CE Threshold Voltage 2
CE Current
-2
0.1
0.6xVIN
1.215
100
µA
V
GPM_LO
VCE
VCE
0.8xVIN
th1
V
th2
I
µA
kΩ
Ω
CE
R
VGHM Pull-down Resistance
VGH to VGHM On Resistance
VDPM Charge Current
1.1
VGHM_PD
R
23
ONVGH
IDPM
SUPPLY MONITOR
10
µA
V
VDIV High Threshold
VDIV rising
VDIV falling
1.265
1.21
1.280
1.222
1.217
10
1.295
1.234
1.234
V
V
IH_VDIV
V
VDIV Low Threshold
IL_VDIV
VthCD2
CD2 Threshold voltage
CD2 Charge Current
1.200
V
I
µA
Ω
s
CD2
R
RESET Pull-Down Resistance
RESET Delay on the Rising Edge
650
IL_RESET
t
121.7k*
CD
DELAY_RESET
VCOM AMPLIFIER R
LOAD
= 10k, C
= 10pF, Unless Otherwise Stated
LOAD
I
VCOM Amplifier Supply Current
Offset Voltage
0.7
2.5
0
1.08
15
mA
mV
nA
V
S_com
V
OS
I
Non-inverting Input Bias Current
Common Mode Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Output Voltage Swing High
B
CMIR
0
AVDD
CMRR
PSRR
60
70
75
dB
dB
mV
V
85
AVDD - 1.39
AVDD - 1.27
1.2
V
I
I
I
I
(source) = 0.1mA
(source) = 75mA
(sink) = 0.1mA
(sink) = 75mA
OH
OUT
OUT
OUT
OUT
V
Output Voltage Swing Low
mV
V
OL
1
FN7928.0
December 5, 2011
6
ISL97649A
Electrical Specifications
V
= ENABLE = 3.3V, A
VDD
= 8V, V
= 2.5V, V = 24V, V = - 6V. Boldface limits apply over the
ON OFF
IN
operating temperature range, -40°C to +85°C. (Continued)
LDO
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 6)
(Note 7)
(Note 6) UNITS
I
Output Short Circuit Current
Pull-up
Pull-down
150
225
200
25
mA
mA
SC
150
SR
Slew Rate
V/µs
MHz
BW
Gain Bandwidth
-3dB gain point
20
DIGITAL CONTROLLED POTENTIOMETER
SET
SET Voltage Resolution
8
Bits
VR
(Note 12)
SET
SET Differential Nonlinearity
T
= +25°C
±1
LSB
DNL
A
(Note 8, 9,
14)
SET
SET Zero-Scale Error
SET Full-Scale Error
RSET Current
T
= +25°C
= +25°C
±2
±8
LSB
LSB
ZSE
(Note 10, 14)
A
SET
FSE
(Note 11,14)
T
A
I
100
µA
RSET
AVDD to SET AVDD to SET Voltage Attenuation
FAULT DETECTION THRESHOLD
1:20
V/V
V
Undervoltage Lock out Threshold
PV rising
IN
2.25
2.125
15.0
2.33
2.20
15.5
2.41
2.27
16.0
V
V
V
UVLO
PV falling
IN
OVP
AVDD
(Note 13)
Boost Overvoltage Protection Off
Threshold to Shutdown IC
T
Thermal Shut-Down all Channels
Temperature rising
153
°C
OFF
POWER SEQUENCE TIMING
t
VLOGIC
ss
VLOGIC Soft-start Time
Boost Soft-start Current
0.45
5.5
ms
µA
I
3
8
ss
Serial Interface Specifications For SCL and SDA Unless Otherwise Noted.
MIN
(Note 14)
TYP
(Note 7)
MAX
(Note 14) UNITS
SYMBOL
PARAMETER
SCL Frequency
TEST CONDITIONS
f
400
kHz
SCL
(Note 6)
t
Pulse Width Suppression Time at SDA
Any pulse narrower than the max spec is
suppressed
50
ns
iN
(Note 6) and SCL Inputs
t
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of V , until
IN
480
ns
AA
SDA exits the 30% to 70% of V window
IN
t
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of V during a STOP
CC
480
ns
BUF
condition, to SDA crossing 70% of V during
IN
the following START condition
t
Clock LOW Time
Measured at the 30% of V crossing
IN
480
400
480
ns
ns
ns
LOW
t
Clock HIGH Time
Measured at the 70% of V crossing
IN
HIGH
t
START Condition Set-up Time
SCL rising edge to SDA falling edge; both
SU:STA
crossing 70% of V
IN
t
START Condition Hold Time
From SDA falling edge crossing 30% of V to
400
ns
HD:STA
IN
SCL falling edge crossing 70% of V
IN
FN7928.0
December 5, 2011
7
ISL97649A
Serial Interface Specifications For SCL and SDA Unless Otherwise Noted. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
Input Data Set-up Time
TEST CONDITIONS
(Note 14)
(Note 7)
(Note 14) UNITS
t
From SDA exiting the 30% to 70% of V
40
ns
SU:DAT
IN
window, to SCL rising edge crossing 30% of
V
IN
t
Input Data Hold Time
From SCL rising edge crossing 70% of V to
0
ns
ns
ns
HD:DAT
IN
SDA entering the 30% to 70% of V window
IN
t
STOP Condition Set-up Time
From SCL rising edge crossing 70% of V , to
400
400
SU:STO
IN
SDA rising edge crossing 30% of V
IN
t
STOP Condition Hold Time for Read, or
Volatile Only Write
From SDA rising edge to SCL falling edge;
both crossing 70% of V
HD:STO
IN
C
Capacitive on SCL
5
5
pF
pF
SCL
C
Capacitive on SDA
SDA
t
Non-Volatile Write Cycle Time
EEPROM Endurance
EEPROM Retention
25
1
ms
Wp
T = +25°C
kCyc
kHrs
A
T
= +25°C
88
A
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Typical values are for T = +25°C and V = 3.3V.
IN
A
8. LSB = I V
- V I / 254. V
and V are the measured voltages for the DCP register set to FF hex and 01 hex respectively.
1
255
9. DNL = I V
1
255
- V I / LSB-1, i ∈ [1, 255]
i+1
i
10. ZS error = (V -VMIN) / LSB. VMIN = (VAVDD*R2) * [1-254*R1/(255*20*RSET)]/ (R1+R2).
1
11. FS error = (V
- VMAX) / LSB. VMAX= (VAVDD*R2) * [1-0*R1/(255*20*RSET)]/ (R1+R2).
255
12. Established by design. Not a parametric spec.
13. Boost will stop switching as soon as boost output reaches OVP threshold.
14. Compliance to limits is assured by characterization and design.
FN7928.0
December 5, 2011
8
ISL97649A
Typical Performance Curves
92
90
88
0.00
-0.01
-0.02
-0.03
f
= 600kHz
OSC
f
= 1.2MHz
OSC
f
= 600kHz
OSC
86
84
82
80
78
76
f
= 1.2MHz
OSC
V
= 3.3V, V
250
= 8.06V
IN
OUT
V
= 3.3V, V
= 8.06V
IN
OUT
-0.04
50
0.0
50
100
150
200
(mA)
300
350
100
150
(mA)
200
250
I
I
AVDD
AVDD
FIGURE 1.
EFFICIENCY vs I
FIGURE 2.
I
LOAD REGULATION vs I
AVDD AVDD
AVDD
AVDD
L = 10µH, C
= 40µF, C
= 15nF, R = 5.5k
COMP
OUT
COMP
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
I
= 150mA
AVDD
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
IN
FIGURE 3.
I
LINE REGULATION vs V
FIGURE 4. BOOST CONVERTER TRANSIENT RESPONSE
AVDD
IN
CE = 1pF, RE = 100k
CE = 100pF, RE = 100k
VGHM
VGHM
FIGURE 5. GPM CIRCUIT WAVEFORM
FIGURE 6. GPM CIRCUIT WAVEFORM
FN7928.0
December 5, 2011
9
ISL97649A
Typical Performance Curves(Continued)
CE = 10pF, RE = 50k
CE = 10pF, RE = 150k
VGHM
VGHM
FIGURE 7. GPM CIRCUIT WAVEFORM
FIGURE 8. GPM CIRCUIT WAVEFORM
VGHM
FIGURE 9. V
FOLLOWS V WHEN THE SYSTEM POWERS OFF
GH
FIGURE 10. VCOM RISING SLEW RATE
GHM
2.4854
2.4852
2.4850
2.4848
2.4846
2.4844
2.4842
2.4840
2.4838
0.000
-0.005
-0.010
-0.015
-0.020
-0.025
-0.030
ILDO = 1mA
VLDO = 2.5V
2.4836
3.0
3.5
4.0
4.5
5.0
5.5
0
50
100
150
200
250
300
350
VLDO_IN (V)
ILDO (mA)
FIGURE 11. LDO LINE REGULATION vs V
FIGURE 12.
LOAD REGULATION vs I
LDO LDO
IN
FN7928.0
December 5, 2011
10
ISL97649A
This restricts the maximum output current (average) based on
Applications Information
Enable Control
With VIN > UVLO, only the Logic output channel is activated. All
other functions in ISL97649A are shut down when the enable pin
is pulled down. When the voltage at the enable pin reaches H
threshold, the whole chip turns on.
Equation 3:
ΔI
V
IN
V
O
L
(EQ. 3)
⎛
⎞
⎠
-------
--------
I
=
I
–
LMT
×
OMAX
⎝
2
where ΔI is the peak-to-peak inductor ripple current, and is set
L
by Equation 4:
V
D
f
s
IN
(EQ. 4)
-------- ---
ΔI
=
×
L
L
Frequency Selection
where f is the switching frequency (600kHz or 1.2MHz).
S
The ISL97649A switching frequency can be user selected to
operate at either constant 600kHz or 1.2MHz. Lower switching
frequency can save power dissipation at very light load
conditions. Also, low switching frequency more easily leads to
discontinuous conduction mode, while higher switching
frequency allows for smaller external components, such as
inductor and output capacitors, etc. Higher switching frequency
will get higher efficiency within some loading range depending
on VIN, VOUT, and external components, as shown in Figure 1.
Connecting the FREQ pin to GND sets the PWM switching
Capacitor
An input capacitor is used to suppress the voltage ripple injected
into the boost converter. The ceramic capacitor with a
capacitance larger than 10µF is recommended. The voltage
rating of the input capacitor should be larger than the maximum
input voltage. Some input capacitors are recommended in
Table 1.
TABLE 1. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATION
frequency to 600kHz, or connecting FREQ pin to V for 1.2MHz.
IN
CAPACITOR
10µF/6.3V
10µF/16V
10µF/10V
22µF/10V
SIZE
0603
1206
0805
1210
MFG
TDK
PART NUMBER
C1608X5R0J106M
C3216X7R1C106M
GRM21BR61A106K
GRB32ER61A226K
Soft-Start
The soft-start is provided by an internal current source to charge
the external soft-start capacitor. The ISL97649A ramps up the
current limit from 0A up to the full value, as the voltage at the SS
pin ramps from 0V to 0.8V. Hence, the soft-start time is 3.2ms
when the soft-start capacitor is 22nF, 6.8ms for 47nF and
14.5ms for 100nF.
TDK
Murata
Murata
Inductor
Operation
The boost inductor is a critical part that influences the output
voltage ripple, transient response, and efficiency. Values of
3.3µH to 10µH are used to match the internal slope
compensation. The inductor must be able to handle the following
average and peak currents shown in Equation 5:
The boost converter is a current mode PWM converter operating
at either 600kHz or 1.2MHz. It can operate in both discontinuous
conduction mode (DCM) at light load and continuous conduction
mode (CCM). In continuous conduction mode, current flows
continuously in the inductor during the entire switching cycle in
steady state operation. The voltage conversion ratio in
continuous current mode is given by Equation 1:
V
I
O
------------
I
=
LAVG
1 – D
(EQ. 5)
ΔI
L
--------
+
LAVG
I
= I
LPK
2
1
1 – D
Boost
(EQ. 1)
-----------------
------------
=
V
Some inductors are recommended in Table 2 for different design
considerations.
IN
where D is the duty cycle of the switching MOSFET.
Rectifier Diode
The boost regulator uses a summing amplifier architecture
consisting of gm stages for voltage feedback, current feedback
and slope compensation. A comparator looks at the peak
inductor current cycle-by-cycle and terminates the PWM cycle if
the current limit is reached.
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of their
fast recovery time and low forward voltage. The reverse voltage
rating of this diode should be higher than the maximum output
voltage. The rectifier diode must meet the output current and
peak inductor current requirements. Table 3 shows some
recommendations for boost converter diode.
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current drawn by
the resistor network should be limited to maintain the overall
converter efficiency. The maximum value of the resistor network
is limited by the feedback input bias current and the potential for
noise being coupled into the feedback pin. A resistor network in
the order of 60kΩ is recommended. The boost converter output
voltage is determined by Equation 2:
TABLE 2. BOOST CONVERTER INDUCTOR RECOMMENDATION
DIMENSIONS
(mm)
PART
NUMBER
INDUCTOR
MFG
NOTE
10µH/
8.3x8.3x4.5 Sumida CDR8D43-100NC
Efficiency
R
+ R
4Apeak
Optimization
1
2
(EQ. 2)
--------------------
V
=
× V
Boost
FB
R
2
6.8µH/
5.0x5.0x2.0
TDK PLF5020T-6R8M1R8
1.8Apeak
The current through the MOSFET is limited to 1.5A
.
PEAK
FN7928.0
December 5, 2011
11
ISL97649A
TABLE 2. BOOST CONVERTER INDUCTOR RECOMMENDATION
The efficiency of the LDO depends on the difference between
input voltage and output voltage (Equation 7) by assuming LDO
quiescent current is much lower than LDO output current:
DIMENSIONS
(mm)
PART
NUMBER
INDUCTOR
MFG
NOTE
PCB
space/profile
optimization
V
⎛
⎜
⎝
⎞
⎟
⎠
LDO_IN
10uH/
2.2Apeak
6.6x7.3x1.2 Cyntec PCME061B-100MS
-------------------------
η(%) =
× 100%
(EQ. 7)
V
LDO_OUT
The less difference between input and output voltage, the higher
efficiency it is.
TABLE 3. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION
Ceramic capacitors are recommended for the LDO input and
output capacitors. Intersil recommends an output capacitor
within the 1µF to 4.7µF range and a maximum feedback resistor
impedance of 20kΩ. Larger capacitors help to reduce noise and
deviation during transient load change. Some capacitors are
recommended in Table 5.
DIODE
V /I
AVG
RATING
PACKAGE
MFG
R
PMEG2010ER
MSS1P2U
20V/1A
20V/1A
SOD123W NXP
MicroSMP VISHAY
Output Capacitor
The output capacitor supplies the load directly and reduces the
ripple voltage at the output. Output ripple voltage consists of two
components:
TABLE 5. LDO OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR
1µF/10V
SIZE
0603
0603
0603
MFG
TDK
PART NUMBER
C1608X7R1A105K
1. The voltage drop due to the inductor ripple current flowing
through the ESR of the output capacitor.
1µF/6.3V
2.2µF/6.3V
MURATA GRM188R70J105K
TDK C1608X7R0J225K
2. Charging and discharging of the output capacitor.
V
– V
I
O
1
f
s
O
IN
-------------------- ------------ ---
V
= I
× ESR +
LPK
×
×
(EQ. 6)
Supply Monitor Circuit
RIPPLE
V
C
O
OUT
The Supply Monitor circuit monitors the voltage on VDIV, and sets
open-drain output RESET low when VDIV is below 1.28V (rising)
or 1.22V (falling).
For low ESR ceramic capacitors, the output ripple is dominated
by the charging and discharging of the output capacitor. The
voltage rating of the output capacitor should be greater than the
maximum output voltage.
There is a delay on the rising edge, controlled by a capacitor on
CD2. When VDIV exceeds 1.28V (rising), CD2 is charged up from
0V to 1.217V by a 10µA current source. Once CD2 exceeds
1.217V, RESET will go tri-state. When VDIV falls below 1.22V,
RESET will become low with a 650Ω pull-down resistance. The
delay time is controlled by Equation 8:
Note: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across them increases.
C
in Equation 6 assumes the effective value of the capacitor
OUT
at a particular voltage and not the manufacturer’s stated value,
measured at 0V.
(EQ. 8)
t
= 121.7k × CD2
delay
Table 4 shows some selections of output capacitors.
TABLE 4. BOOST OUTPUT CAPACITOR RECOMMENDATION
For example, the delay time is 12.17ms if the CD2 = 100nF.
Figure 13 shows the Supply Monitor Circuit timing diagram.
CAPACITOR
10µF/25V
10µF/25V
SIZE
1210
1210
MFG
TDK
PART NUMBER
C3225X7R1E106M
Murata GRM32DR61E106K
1.28V
1.22V
VDIV
Compensation
The boost converter of ISL97649A can be compensated by an RC
network connected from the COMP pin to ground. 15nF and 5.5k
RC network is used in the demo board. The larger value resistor
and lower value capacitor can lower the transient overshoot,
however, at the expense of the stability of the loop.
1.217V
CD2
Linear Regulator (LDO)
The ISL97649A includes an LDO with adjustable output. It can
supply current up to 350mA. The output voltage is adjusted by
connection of the ADJ pin.
RESET DELAY TIME IS
CONTROLLED BY CD2
CAPACITOR
RESET
FIGURE 13. SUPPLY MONITOR CIRCUIT TIMING DIAGRAM
FN7928.0
December 5, 2011
12
ISL97649A
VIN
UVLO
THRESHOLD
0
VGH
RESET
VDPM
1.215V
VFLK
VGH
VGHM IS FORCED
TO VGH WHEN VIN
VGHM
GPM_LO
FALLS TO UVLO AND
CONTROLLED BY RE
SLOPE IS
VGH>3V
Power on delay tme
POWER-ON DELAY TIME
CONTROLLED BY C
cn
DELAY TIME IS
CONTROLLED BY CE
DPM
FIGURE 14. GATE PULSE MODULATOR TIMING DIAGRAM
3V, VGHM will not be actively driven until VIN is driven. Figure 14
Gate Pulse Modulator Circuit
shows the VGHM voltage based on V , VGH and RESET.
IN
The gate pulse modulator circuit functions as a three way
multiplexer, switching VGHM between ground, GPM_LO and VGH.
Voltage selection is provided by digital inputs VDPM (enable) and
VFLK (control). High to low delay and slew control is provided by
external components on pins CE and RE, respectively.
VCOM Amplifier
The VCOM amplifier is designed to control the voltage on the back
plane of an LCD display. This plane is capacitively coupled to the
pixel drive voltage, which alternately cycles positive and negative at
the line rate for the display. Thus, the amplifier must be capable of
sourcing and sinking pulses of current, which can occasionally be
quite large (in the range of 100mA for typical applications).
When VDPM is LOW, the block is disabled and VGHM is
grounded. When the input voltage exceeds UVLO threshold,
VDPM starts to drive an external capacitor. Once VDPM exceeds
1.215V, the GPM circuit is enabled, and the output VGHM is
determined by VFLK, RESET signal and VGH voltage. If RESET
signal is high and VFLK is high, VGHM is pulled to VGH. When
VFLK goes low, there is a delay controlled by capacitor CE,
following which, VGHM is driven to GPM_LO, with a slew rate
controlled by resistor RE. Note that GPM_LO is used only as a
reference voltage for an amplifier, and thus does not have to
source or sink a significant DC current.
The ISL97649A VCOM amplifier's output current is limited to
225mA typical. This limit level, which is roughly the same for
sourcing and sinking, is included to maintain reliable operation
of the part. It does not necessarily prevent a large temperature
rise if the current is maintained. (In this case, the whole chip may
be shut down by the thermal trip to protect functionality.) If the
display occasionally demands current pulses higher than this
limit, the reservoir capacitor will provide the excess and the
amplifier will top the reservoir capacitor back up once the pulse
has stopped. This will happen in the µs time scale in practical
systems and for pulses 2 or 3 times the current limit; the VCOM
voltage will have settled again before the next line is processed.
Low to high transition is determined primarily by the switch
resistance and the external capacitive load. High to low transition
is more complex. Take the case where the block is already
enabled (VDPM is H). When VFLK is H, if CE is not externally
pulled above threshold voltage 1, pin CE is pulled low. On the
falling edge of VFLK, a current is passed into pin CE to charge the
external capacitor up to threshold voltage 2, providing a delay
which is adjustable by varying the capacitor on CE. Once this
threshold is reached, the output starts to be pulled down from
VGH to GPM_LO. The maximum slew current is equal to 500/(RE
DCP Memory Description
The ISL97649A contains one non-volatile byte known as the
2
Initial Value Register (IVR). It is accessed by the I C interface
operations with Address 00h. The IVR contains the value that is
loaded into the Volatile Wiper Register (WR) at power-up.
+ 40k), and the dv/dt slew rate is Isl/C
, where C is the
LOAD
LOAD
load capacitance applied to VGHM. The slew rate reduces as
VGHM approaches GPM_LO.
The volatile WR and the non-volatile IVR of a DCP are accessed
with the same address.
If CE is always pulled up to a voltage above threshold 1, zero
delay mode is selected; thus, there will be no delay from FLK
falling to the point where VGHM starts to fall. Slew down currents
will be identical to the previous case.
The Access Control Register (ACR) determines which word at
address 00h is accessed (IVR or WR). The volatile ACR must be
set as follows:
When the ACR is all zeroes, which is the default at power-up:
At power-down, when VIN falls to UVLO, VGHM will be tied to VGH
until the VGH voltage falls to 3V. Once the VGH voltage falls below
• A read operation to address 0 outputs the value of the
non-volatile IVR.
FN7928.0
December 5, 2011
13
ISL97649A
• A write operation to address 0 writes the identical values to the
WR and IVR of the DCP.
An ACK (Acknowledge) is a software convention used to indicate a
successful data transfer. The transmitting device, either master or
slave, releases the SDA bus after transmitting eight bits. During the
ninth clock cycle, the receiver pulls the SDA line LOW to
• When the ACR is 80h:
acknowledge the reception of the eight bits of data (see Figure 16).
- A read operation to address 0 outputs the value of the
volatile WR.
The ISL97649A DCP responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and once
again after successful receipt of an Address Byte. The ISL97649A
also respond with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
- A write operation to address 0 only writes to the
volatile WR.
It is not possible to write to an IVR without writing the same value
to its WR.
00h and 80h are the only values that should be written to
address 2. All other values are reserved and must not be written
to address 2.
A valid Identification Byte contains 0101000 as the seven MSBs.
The LSB is in the Read/Write bit. Its value is "1" for a Read
operation, and "0" for a Write operation (see Table 7).
TABLE 6. MEMORY MAP
TABLE 7. IDENTIFICATION BYTE FORMAT
ADDRESS
NON-VOLATILE
-
VOLATILE
ACR
0
1
0
1
0
0
0
R/W
2
1
0
(MSB)
(LSB)
Reserved
IVR
WR
Write Operation
WR: Wiper Register, IVR: Initial value Register.
A write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition (see Figure 17). After each of the three bytes, the
ISL97649A responds with an ACK. At this time, if the Data Byte is
to be written only to volatile registers, the device enters its
standby state. If the Data Byte is to be written also to non-volatile
memory, the ISL97649A begins its internal write cycle to
non-volatile memory. During the internal non-volatile write cycle,
the device ignores transitions at the SDA and SCL pins and the
SDA output is at high impedance state. When the internal
non-volatile write cycle is completed, the ISL97649A enters its
standby state. The byte at address 02h determines if the Data
Byte is to be written to volatile and/or non-volatile memory.
2
I C Serial Interface
The ISL97649A supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data on to the bus as
a transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the DCP of the ISL97649A operates as a slave device
in all applications. The fall and rise time of SDA and SCL signal
2
should be in the range listed in Table 8. Capacitive load on I C
bus is also specified in Table 8.
2
All communication over the I C interface is conducted by sending
Data Protection
the MSB of each byte of data first.
A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile and
non-volatile registers. During a Write sequence, the Data Byte is
loaded into an internal shift register as it is received. If the
Address Byte is 0 or 2, the Data Byte is transferred to the Wiper
Register (WR) or to the Access Control Register respectively, at
the falling edge of the SCL pulse that loads the last bit (LSB) of
the Data Byte. If the Address Byte is 0, and the Access Control
Register is all zeros (default), then the STOP condition initiates
the internal write cycle to non-volatile memory.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 15). On
power-up of the ISL97649A, the SDA pin is in the input mode.
2
All I C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
DCP continuously monitors the SDA and SCL lines for the START
condition and does not respond to any command until this
condition is met (see Figure 15). A START condition is ignored
during the power-up sequence and during internal non-volatile
write cycles.
2
TABLE 8. I C INTERFACE SPECIFICATION
PARAMETER
SDA and SCL Rise Time
SDA and SCL Fall Time
MIN
TYP
MAX
1000
300
UNITS
ns
2
All I C interface must be terminated by a STOP condition, which
is a LOW to HIGH transition of SDA while SCL is high (see
Figure 15). A STOP condition at the end of a read operation, or at
the end of a write operation to volatile bytes only places the
device in its standby mode. A STOP condition during a write
operation to a non-volatile write byte, initiates an internal
non-volatile write cycle. The device enters its standby state when
the internal non-volatile write cycle is completed.
ns
2
I C Bus Capacitive Load
400
pF
FN7928.0
December 5, 2011
14
ISL97649A
SCL
SDA
START
DATA
DATA
DATA
STOP
STABLE
CHANGE STABLE
FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
S
T
SIGNALS FROM
THE MASTER
S
T
O
P
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
X
0
SIGNAL AT SDA
0
1
0
1
0 0
0
0
0
0
0
0
0
0
SIGNALS FROM
THE ISL97649A
A
C
K
A
C
K
A
C
K
FIGURE 17. BYTE WRITE SEQUENCE
S
T
A
R
T
S
T
A
R
T
SIGNALS
FROM THE
MASTER
S
T
O
P
A
C
K
A
C
K
IDENTIFICATION
BYTE WITH
R/W = 0
IDENTIFICATION
BYTE WITH
R/W = 1
ADDRESS
BYTE
SIGNAL AT SDA
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0 0
0
1
0
0
0
X
A
C
K
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 18. READ SEQUENCE
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December 5, 2011
15
ISL97649A
should be zero (0). The ACR controls which word is accessed at
Read Operation
A read operation consists of a three-byte instruction followed by
one or more Data Bytes (see Figure 18). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to "0", an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to "1". After each of the three bytes, the ISL97649A responds
with an ACK; then the ISL97649A transmits the Data Byte. The
master then terminates the read operation (issuing a STOP
condition) following the last bit of the Data Byte (see Figure 16).
register 00h as follows:
• 00h = Nonvolatile IVR
• 80h = Volatile WR
All other bits of the ACR should be written 0 or 1. Power-up
default for this address is 00h.
Register Description: IVP and WR
The output of the DCP is controlled directly by the WR. Writes and
reads can be made directly to this register to control and monitor
without any non-volatile memory changes. This is done by setting
address 02h to data 80h, then writing the data.
The byte at address 02h determines if the Data Bytes being read
are from volatile or non-volatile memory.
Communication with ISL97649A
The non-volatile IVR stores the power-up value of the DCP output.
On power -up, the contents of the IVR are transferred to the WR.
There are three register addresses in the ISL97649A, of which
two can be used. Address 00h and address 02h are used to
control the device. Address 01h is reserved and should not be
used. Address 00h contains the non-volatile Initial Value Register
(IVR), and the volatile Wiper Register (WR). Address 02h contains
only a volatile word and is used as a pointer to either the IVR or
WR.
To write to the IVR, first address 02h is set to data 00h and then
the data is written. Writing a new value to the IVR register will set
a new power- up position for the wiper. Also, writing to this
register will load the same value into the WR as the IVR.
Therefore, if a new value is loaded into the IVR, not only will the
non-volatile IVR change, but the WR will also contain the same
value after the write, and the wiper position will change. Reading
from the IVR will not change the WR, if its contents are different.
Register Description: Access Control
The Access Control Register (ACR) is volatile and is at address
02h. It is 8 bits, and only the MSB is significant; all other bits
Writing a new value to the IVR
Write to ACR first
0
1
0
1
0
0
0
0
0
0
0
0
A
A
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
A
A
0
0
0
0
0
0
0
0
A
A
Then, write to IVR
0
1
0
1
D0
D7
D6
D5
D4
D3
D2
D1
Note that the WR will also reflect this new value since both registers get writen at the same time
D0:LSB, D7:MSB
Writing a new value to WR only
Write to ACR first
0
1
0
1
0
0
0
0
0
0
0
0
A
A
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
A
A
1
0
0
0
0
0
0
0
A
A
Then, write to WR
0
1
0
1
D0
D7
D6
D5
D4
D3
D2
D1
Note that the IVR value will NOT change
D0:LSB, D7:MSB
Reading from IVR
Write to the ACR first
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
A
A
A
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
A
A
0
0
0
0
0
0
0
0
A
Then set the IVR address
0
1
0
0
Read from the IVR
0
1
D0
D7
D6
D5
D4
D3
D2
D1
Example 2
Reading from the WR
Write to the ACR first
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
A
A
A
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
A
A
1
0
0
0
0
0
0
0
A
Then set the WR address
0
1
0
0
Read from the WR
0
1
D0
D7
D6
D5
D4
D3
D2
D1
FN7928.0
December 5, 2011
16
ISL97649A
PCB layout. PCB layout is critical, especially at high switching
frequency.
Initial VCOM Setting
A 256-step resolution is provided under digital control, which
adjusts the sink current of the output. The output is connected to
an external voltage divider, so that the device will have the
capability to reduce the voltage on the output by increasing the
output sink current. The equations that control the output are
given in the following. The initial setting value is at 128. The WR
Following are some general guidelines for layout:
1. Place the external power components (the input capacitors,
output capacitors, boost inductor and output diodes, etc.) in
close proximity to the device. Traces to these components
should be kept as short and wide as possible to minimize
parasitic inductance and resistance.
2
value is set back to 128 if any error occurs during I C read or
write communication. When writing to the EEPROM, VGH needs
to be higher than 12V when AVDD is 8V. Outside these
conditions, writing operations may be not successful. The
maximum resistor value of RSET is determined by the following
equations:
2. Place V and V
DC
bypass capacitors close to the pins.
REF
3. Loops with large AC amplitudes and fast slew rate should be
made as small as possible.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from the LX
node as possible.
RSET < V_AVDD ⁄ 100μA
(EQ. 9)
(EQ. 10)
(EQ. 11)
V
255 – Setting
AVDD
------------------------------------- --------------------------
IOUT =
VOUT =
⋅
5. The power ground (PGND) should be connected at the
ISL97649A exposed die plate area.
255
⋅ V
20(RSET)
R
R
U
20(RSET)
255 – Setting
L
AVDD
⎛
⎝
⎞
⎠
----------------------------
------------------------------------- --------------------------
×
⋅
1 –
6. The exposed die plate, on the underside of the package,
should be soldered to an equivalent area of metal on the PCB.
This contact area should have multiple via connections to the
back of the PCB as well as connections to intermediate PCB
layers, if available to maximize thermal dissipation away from
the IC.
(R + R )
255
U
L
where R , R and RSET in Equation 11 correspond to R , R and
L
U
7
8
R in the Application Diagram on page 2.
9
Start-up Sequence
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track and
ground plane area connected to the exposed die plate should
be maximized and spread out as far as possible from the IC.
The bottom and top PCB areas especially should be
When VIN rising exceeds UVLO, it takes 120µs to read the
settings stored in the chip in order to activate the chip correctly.
After all the settings are written in the registers, VLOGIC starts up
with a 0.5ms soft-start time. When both VLOGIC is in regulation
and EN is high, the boost converter starts up. The Gate Pulse
modulator output VGHM is held low until VDPM is charged to
1.215V. The detailed power on sequence is shown in Figure 19.
maximized to allow thermal dissipation to the surrounding air.
8. Minimize feedback input track lengths to avoid switching
noise pick-up.
Layout Recommendation
The device's performance, including efficiency, output noise,
transient response and control loop stability, is affected by the
A demo board is available to illustrate the proper layout
implementation.
FN7928.0
December 5, 2011
17
ISL97649A
EN
VIN
UVLO
UVLO
tSS_VLOGIC
PANEL NORMAL OPERATION
VLOGIC
AVDD
VOFF
tSS_AVDD CONTROLLED BY VSS
VON
VCOM
1.280V
1.222V
1.217V
VDIV
CD2
1.215V
RESET
VDPM
GPM ENABLED WHEN BOTH
1) EN = HIGH AND
2) VDPM > 1.215V
VGHM
VGHM OUTPUT TIED TO VGH WHEN VIN FALLS TO UVLO
FIGURE 19. ISL97649A POWER ON/OFF SEQUENCE
FN7928.0
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18
ISL97649A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
FN7928.0
CHANGE
December 5, 2011
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
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For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
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FN7928.0
December 5, 2011
19
ISL97649A
Package Outline Drawing
L28.4x5A
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 06/08
2.50
0.50
6
4.00
A
24X
PIN #1 INDEX AREA
B
28
23
6
22
1
PIN 1
INDEX AREA
3.50
Exp. DAP
3.50
8
0.10 M C A B
28X 0.25
15
(4X)
0.15
4
9
14
SIDE VIEW
TOP VIEW
2.50
Exp. DAP
28X 0.400
BOTTOM VIEW
SEE DETAIL "X"
( 3.80 )
( 2.50)
C
0.10
C
Max 0.90
SEATING PLANE
0.08
C
SIDE VIEW
( 4.80 )
( 24X 0.50)
( 3.50 )
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
(28X .250)
DETAIL "X"
( 28 X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7928.0
December 5, 2011
20
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