ISL95870IRUZ [INTERSIL]
PWM DC/DC Controller with VID Inputs for Portable GPU Core-Voltage Regulator;
| 型号： | ISL95870IRUZ |
| 厂家： | 
Intersil |
| 描述： | PWM DC/DC Controller with VID Inputs for Portable GPU Core-Voltage Regulator |
| 文件： | 总29页 (文件大小：633K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PWM DC/DC Controller with VID Inputs for
Portable GPU Core-Voltage Regulator
ISL95870, ISL95870A, ISL95870B
The ISL95870, ISL95870A, ISL95870B ICs are
Features
• Input Voltage Range: 3.3V to 25V
• Output Voltage Range: 0.5V to 5V
• Precision Regulation
- Proprietary R ™ Frequency Control Loop
- ±0.5% System Accuracy Over -10°C to +100°C
Single-Phase Synchronous-Buck PWM regulators
4
featuring Intersil’s proprietary R Technology™. The wide
3.3V to 25V input voltage range is ideal for systems that
run on battery or AC-adapter power sources. The
ISL95870A and ISL95870B are low-cost solutions for
applications requiring dynamically selected slew-rate
controlled output voltages. The soft-start and dynamic
setpoint slew-rates are capacitor programmed. Voltage
identification logic-inputs select four (ISL95870A,
ISL95870B) resistor-programmed setpoint reference
voltages that directly set the output voltage of the
converter between 0.5V and 1.5V, and up to 5V with a
feedback voltage divider.
4
• Optimal Transient Response
4
- Intersil’s R ™ Modulator Technology
• Output Remote Sense
• Extremely Flexible Output Voltage Programmability
- 2-Bit VID Selects Four Independent Setpoint
Voltages for ISL95870B
- 2-Bit VID Selects Four Dependent or Three
Independent Setpoint Voltages for ISL95870A
- Simple Resistor Programming of Setpoint Voltages
3
4
Compared with R modulator, the R modulator has
equivalent light-load efficiency, faster transient
performance, accurately regulated frequency control and
all internal compensation. These updates, together with
integrated MOSFET drivers and schottky bootstrap diode,
allow for a high-performance regulator that is highly
compact and needs few external components. The
differential remote sensing for output voltage and
selectable switching frequency are another two new
functions. For maximum efficiency, the converter
automatically enters diode-emulation mode (DEM)
during light-load conditions such as system standby.
• Selectable 300kHz, 500kHz, 600kHz or 1MHz PWM
Frequency in Continuous Conduction
• Automatic Diode Emulation Mode for Highest Efficiency
• Power-Good Monitor for Soft-Start and Fault Detection
Applications*(see page 26)
• Mobile PC Graphical Processing Unit VCC Rail
• Mobile PC I/O Controller Hub (ICH) VCC Rail
• Mobile PC Memory Controller Hub (GMCH) VCC Rail
R
C
VCC
+5V
C
VCC
PVCC
V
IN
3.3V TO 25V
CIN
Q
HS
1
12
11
10
9
GND
RTN
BOOT
R
FB1
RTN1
2
V
UGATE
PHASE
PGOOD
L
OUT
O
0.5V TO 5V
3
4
EN
GPIO
Q
LS
CO
SREF
C
SEN
RTN1
C
BOOT
R
O
0
R
FB
R
OFS
FIGURE 1. ISL95870 APPLICATION SCHEMATIC WITH ONE OUTPUT VOLTAGE SETPOINT AND DCR CURRENT SENSE
December 22, 2009
FN6899.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL95870, ISL95870A, ISL95870B
Applications Schematics: ISL95870
R
VCC
+5V
C
VCC
C
PVCC
V
IN
3.3V TO 25V
CIN
Q
HS
GND
RTN
EN
BOOT
1
2
3
4
12
11
10
9
R
FB1
RTN1
UGATE
PHASE
PGOOD
V
L
OUT
O
0.5V TO 5V
GPIO
Q
LS
SREF
CO
C
SEN
RTN1
C
BOOT
R
O
R
FB
0
R
OFS
FIGURE 2. ISL95870 APPLICATION SCHEMATIC WITH ONE OUTPUT VOLTAGE SETPOINT AND DCR CURRENT SENSE
R
VCC
+5V
C
VCC
C
PVCC
V
IN
3.3V TO 25V
CIN
Q
HS
GND
RTN
EN
BOOT
1
2
3
4
12
11
10
9
R
FB1
RTN1
UGATE
PHASE
PGOOD
V
L
OUT
O
R
SEN
0.5V TO 5V
GPIO
Q
LS
SREF
CO
C
SEN
RTN1
C
BOOT
R
O
R
FB
0
R
OFS
FIGURE 3. ISL95870 APPLICATION SCHEMATIC WITH ONE OUTPUT VOLTAGE SETPOINT AND RESISTOR CURRENT
SENSE
FN6899.0
December 22, 2009
2
ISL95870, ISL95870A, ISL95870B
Applications Schematics: ISL95870A
R
VCC
+5V
V
IN
3.3V TO 25V
C
C
VCC
PVCC
CIN
PGND
VCC
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
Q
HS
GND
RTN
BOOT
UGATE
PHASE
EN
R
FB1
V
L
OUT
O
VID1
VID0
0.5V TO 5V
RTN1
GPIO
Q
LS
CO
RTN1
SREF
SET0
SET1
PGOOD
FSEL
VO
C
SEN
C
BOOT
R
O
R
FB
R
R
R
SET3
SET1
SET2
R
OFS
0
FIGURE 4. ISL95870A APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT
SENSE
R
VCC
+5V
V
IN
3.3V TO 25V
C
C
VCC
PVCC
CIN
V
PGND
VCC
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
Q
HS
GND
RTN
BOOT
UGATE
PHASE
EN
R
FB1
R
L
OUT
SEN
O
VID1
VID0
0.5V TO 5V
RTN1
GPIO
CO
Q
LS
SREF
SET0
SET1
PGOOD
FSEL
VO
C
SEN
RTN1
C
BOOT
R
O
R
FB
R
R
R
SET3
SET1
SET2
R
OFS
0
FIGURE 5. ISL95870A APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND RESISTOR
CURRENT SENSE
FN6899.0
December 22, 2009
3
ISL95870, ISL95870A, ISL95870B
Applications Schematics: ISL95870B
R
VCC
+5V
V
IN
C
PVCC
3.3V TO 25V
C
VCC
CIN
R
FB1
Q
HS
RTN
VID1
BOOT
UGATE
PHASE
EN
1
2
3
4
5
6
16
15
14
13
12
11
RTN1
V
L
OUT
O
GPIO
0.5V TO 5V
VID0
GND
Q
LS
SREF
SET0
SET1
CO
R
SET1
PGOOD
FSEL
C
SEN
C
BOOT
RTN1
R
SET3
R
O
R
FB
0
FIGURE 6. ISL95870B APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT
SENSE
R
VCC
+5V
V
IN
3.3V TO 25V
C
PVCC
C
VCC
CIN
R
FB1
Q
HS
RTN
VID1
BOOT
UGATE
PHASE
EN
1
2
3
4
5
6
16
15
14
13
12
11
RTN1
L
O
V
OUT
R
SEN
0.5V TO 5V
GPIO
VID0
GND
Q
LS
SREF
SET0
SET1
CO
R
SET1
PGOOD
FSEL
C
C
SEN
BOOT
RTN1
R
SET3
R
O
R
FB
0
FIGURE 7. ISL95870B APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND RESISTOR
CURRENT SENSE
FN6899.0
December 22, 2009
4
Block Diagram
VCC
POR
SOFT-START
CIRCUITRY
BOOT
EN
DRIVER
UGATE
PHASE
PGOOD
CIRCUITRY
PGOOD
DEAD-TIME
GENERATION
FB
PVCC
INTERNAL
COMPENSATION
AMPLIFIER
OVERVOLTAGE/
UNDERVOLTAGE
SREF
DRIVER
+
LGATE
PGND
*SET 0
*SET 1
**SET2
*VID1
4
R
MODULATOR
VO
REFERENCE
VOLTAGE
CIRCUITRY
REMOTE SENSE
CIRCUITRY
OVERCURRENT
OCSET
*VID0
GND
Fs SELECTION
CIRCUITRY
*ISL95870A, ISL95870B ONLY
**ISL95870B ONLY
RTN
FSEL
FIGURE 8. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL95870, ISL95870A, ISL95870B
ISL95870, ISL95870A, ISL95870B
Pin Configurations
ISL95870
ISL95870A
(16 LD 2.6X1.8 ΜTQFN)
(20 LD 3.2X1.8 ΜTQFN)
TOP VIEW
TOP VIEW
PGND
GND
VCC
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
BOOT
UGATE
PHASE
EN
GND 1
RTN 2
EN 3
BOOT
12
11 UGATE
10 PHASE
9 PGOOD
RTN
VID1
VID0
SREF
SET0
SET1
4
SREF
PGOOD
FSEL
VO
ISL95870B
(20 LD 3X4 QFN)
TOP VIEW
1
RTN
BOOT
16
VID1 2
VID0 3
15 UGATE
14 PHASE
13 EN
GND
4
SREF
SET0 5
PGOOD
12
6
11 FSEL
SET1
FN6899.0
December 22, 2009
6
ISL95870, ISL95870A, ISL95870B
ISL95870 Functional Pin Descriptions
PIN NUMBER SYMBOL
DESCRIPTION
1
2
GND
RTN
IC ground for bias supply and signal reference.
Negative remote sense input of V
. If resistor divider consisting of R and R
is used at FB pin,
OUT FB
OFS
OFS1
the same resistor divider should be used at RTN pin, i.e. keep R
=R , and R
=R
.
FB1 FB
OFS
3
EN
Enable input for the IC. Pulling EN above the rising threshold voltage initializes the soft-start sequence.
4
SREF
Soft-start and voltage slew-rate programming capacitor input. Connects internally to the inverting input
of the V
SET
voltage setpoint amplifier.
5
FSEL
FB
Input for programming the regulator switching frequency. Pull this pin to VCC for 1MHz switching.
Pull this pin to GND with a 100kΩ resistor for 600kHz switching. Leave this pin floating for 500kHz
switching. Pull this pin directly to GND for 300kHz switching.
6
Voltage feedback sense input. Connects internally to the inverting input of the control-loop error
amplifier. The converter is in regulation when the voltage at the FB pin equals the voltage on the
SREF pin.
7
8
OCSET Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor R
connects from this pin to the sense node.
OCSET
4
VO
Output voltage sense input for the R modulator. The VO pin also serves as the reference input for
the overcurrent detection circuit.
9
PGOOD Power-good open-drain indicator output. This pin changes to high impedance when the converter is
able to supply regulated voltage.
4
10
11
12
PHASE Return current path for the UGATE high-side MOSFET driver, V sense input for the R modulator,
IN
and inductor current polarity detector input.
UGATE High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of the
converter.
BOOT
Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally
connected to the cathode of the Schottky boot-strap diode. Connect an MLCC between the BOOT pin
and the PHASE pin.
13
14
VCC
Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a MLCC to the
GND pin.
PVCC
Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected to the
anode of the Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple with a MLCC to
the PGND pin.
15
16
LGATE
PGND
Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the
converter.
Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET.
FN6899.0
December 22, 2009
7
ISL95870, ISL95870A, ISL95870B
ISL95870A Functional Pin Descriptions
PIN NUMBER SYMBOL
DESCRIPTION
1
LGATE
Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the
converter.
2
3
4
PGND
GND
RTN
Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET.
IC ground for bias supply and signal reference.
Negative remote sense input of V
. If resistor divider consisting of R and R
OUT FB
is used at FB pin,
OFS
OFS1
the same resistor divider should be used at RTN pin, i.e. keep R
=R , and R
=R
.
FB1 FB
OFS
5
6
7
VID1
VID0
SREF
Logic input for setpoint voltage selector. Use in conjunction with the VID0 pin to select among four
setpoint reference voltages.
Logic input for setpoint voltage selector. Use in conjunction with the VID1 pin to select among four
setpoint reference voltages.
Soft-start and voltage slew-rate programming capacitor input and setpoint reference voltage
programming resistor input. Connects internally to the inverting input of the V
amplifier.
voltage setpoint
SET
8
9
SET0
SET1
FB
Voltage set-point programming resistor input.
Voltage set-point programming resistor input.
10
Voltage feedback sense input. Connects internally to the inverting input of the control-loop error
transconductance amplifier. The converter is in regulation when the voltage at the FB pin equals the
voltage on the SREF pin.
11
12
13
OCSET Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor R
connects from this pin to the sense node.
OCSET
4
VO
Output voltage sense input for the R modulator. The VO pin also serves as the reference input for
the overcurrent detection circuit.
FSEL
Input for programming the regulator switching frequency. Pull this pin to VCC for 1MHz switching.
Pull this pin to GND with a 100kΩ resistor for 600kHz switching. Leave this pin floating for 500kHz
switching. Pull this pin directly to GND for 300kHz switching.
14
15
16
17
18
PGOOD Power-good open-drain indicator output. This pin changes to high impedance when the converter is
able to supply regulated voltage.
EN
Enable input for the IC. Pulling EN above the rising threshold voltage initializes the soft-start
sequence.
4
PHASE Return current path for the UGATE high-side MOSFET driver, V sense input for the R modulator,
IN
and inductor current polarity detector input.
UGATE High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of the
converter.
BOOT
Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally
connected to the cathode of the Schottky boot-strap diode. Connect an MLCC between the BOOT pin
and the PHASE pin.
19
20
VCC
Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a MLCC to the
GND pin.
PVCC
Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected to the
anode of the Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple with a MLCC to
the PGND pin.
FN6899.0
December 22, 2009
8
ISL95870, ISL95870A, ISL95870B
ISL95870B Functional Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1
RTN
Negative remote sense input of V
pin, the same resistor divider should be used at RTN pin, i.e. keep R
. If resistor divider consisting of R and R
is used at FB
=R .
OFS
OUT FB OFS
=R , and R
FB1
FB OFS1
2
3
4
VID1
VID0
SREF
Logic input for setpoint voltage selector. Use in conjunction with the VID0 pin to select among four
setpoint reference voltages.
Logic input for setpoint voltage selector. Use in conjunction with the VID1 pin to select among four
setpoint reference voltages.
Soft-start and voltage slew-rate programming capacitor input and setpoint reference voltage
programming resistor input. Connects internally to the inverting input of the V
amplifier.
voltage setpoint
SET
5
6
7
8
SET0
SET1
SET2
FB
Voltage set-point programming resistor input.
Voltage set-point programming resistor input.
Voltage set-point programming resistor input.
Voltage feedback sense input. Connects internally to the inverting input of the control-loop error
transconductance amplifier. The converter is in regulation when the voltage at the FB pin equals
the voltage on the SREF pin.
9
OCSET
VO
Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor R
connects from this pin to the sense node.
OCSET
4
10
11
Output voltage sense input for the R modulator. The VO pin also serves as the reference input
for the overcurrent detection circuit.
FSEL
Input for programming the regulator switching frequency. Pull this pin to VCC for 1MHz switching.
Pull this pin to GND with a 100kΩ resistor for 600kHz switching. Leave this pin floating for 500kHz
switching. Pull this pin directly to GND for 300kHz switching.
12
PGOOD
Power-good open-drain indicator output. This pin changes to high impedance when the converter
is able to supply regulated voltage.
13
14
EN
Enable input for the IC. Pulling EN above the rising threshold voltage initializes the soft-start sequence.
4
PHASE
Return current path for the UGATE high-side MOSFET driver, V sense input for the R modulator,
IN
and inductor current polarity detector input.
15
16
UGATE
BOOT
High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of
the converter.
Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally
connected to the cathode of the Schottky boot-strap diode. Connect an MLCC between the BOOT
pin and the PHASE pin.
17
18
VCC
Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a MLCC to
the GND pin.
PVCC
Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected to
the anode of the Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple with a
MLCC to the PGND pin.
19
LGATE
Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the
converter.
20
PGND
GND
Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET.
IC ground for bias supply and signal reference.
Bottom Pad
FN6899.0
December 22, 2009
9
ISL95870, ISL95870A, ISL95870B
Ordering Information
PART NUMBER
(Note 2)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL95870HRUZ-T (Notes 1, 4) GAV
ISL95870AHRUZ-T (Notes 1, 4) GAW
-10 to +100
-10 to +100
-10 to +100
-10 to +100
-40 to +100
-40 to +100
-40 to +100
-40 to +100
16 Ld 2.6x1.8 µTQFN
20 Ld 3.2x1.8 µTQFN
20 Ld 3x4 QFN
L16.2.6x1.8A
L20.3.2x1.8
L20.3x4
ISL95870BHRZ (Note 3)
870B
ISL95870BHRZ-T (Notes 1, 3) 870B
ISL95870IRUZ-T (Notes 1, 4) GAZ
ISL95870AIRUZ-T (Notes 1, 4) GAX
20 Ld 3x4 QFN
L20.3x4
16 Ld 2.6x1.8 µTQFN
20 Ld 3.2x1.8 µTQFN
20 Ld 3x4 QFN
L16.2.6x1.8A
L20.3.2x1.8
L20.3x4
ISL95870BIRZ (Note 3)
ISL95870BIRZ-T (Notes 1, 3)
NOTES:
870I
870I
20 Ld 3x4 QFN
L20.3x4
1. Please refer to TB347 for details on reel specifications.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL95870, ISL95870A, ISL95870B. For more
information on MSL please see techbrief TB363.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
FN6899.0
December 22, 2009
10
ISL95870, ISL95870A, ISL95870B
Table of Contents
Applications Schematics: ISL95870.................................................................................................... 2
Applications Schematics: ISL95870A.................................................................................................. 3
Applications Schematics: ISL95870B.................................................................................................. 4
Block Diagram .................................................................................................................................... 5
ISL95870 Functional Pin Descriptions ................................................................................................ 7
ISL95870A Functional Pin Descriptions.............................................................................................. 8
ISL95870B Functional Pin Descriptions.............................................................................................. 9
Absolute Maximum Ratings .............................................................................................................. 12
Thermal Information ........................................................................................................................ 12
Recommended Operating Conditions................................................................................................ 12
Electrical Specifications..................................................................................................................... 12
Theory of Operation.......................................................................................................................... 15
Power-On Reset.............................................................................................................................. 15
Start-Up Timing.............................................................................................................................. 15
Start-Up and Voltage-Step Operation for ISL95870.............................................................................. 15
Start-Up and Voltage-Step Operation for ISL95870A, ISL95870B........................................................... 15
Output Voltage Programming for ISL95870......................................................................................... 16
Output Voltage Programming for ISL95870A....................................................................................... 16
Output Voltage Programming for ISL95870B....................................................................................... 17
High Output Voltage Programming ..................................................................................................... 19
R4 Modulator.................................................................................................................................. 19
Stability......................................................................................................................................... 19
Transient Response ......................................................................................................................... 20
Diode Emulation.............................................................................................................................. 20
Overcurrent.................................................................................................................................... 20
Overvoltage ................................................................................................................................... 21
Undervoltage.................................................................................................................................. 21
Over-Temperature........................................................................................................................... 21
PGOOD Monitor............................................................................................................................... 22
Integrated MOSFET Gate-Drivers ....................................................................................................... 22
Adaptive Shoot-Through Protection.................................................................................................... 22
General Application Design Guide ..................................................................................................... 22
Selecting the LC Output Filter ........................................................................................................... 22
Selecting the Input Capacitor ............................................................................................................ 23
Selecting the Bootstrap Capacitor...................................................................................................... 23
Driver Power Dissipation .................................................................................................................. 23
MOSFET Selection and Considerations................................................................................................ 24
Layout Considerations ...................................................................................................................... 24
Revision History ............................................................................................................................... 26
Products ........................................................................................................................................... 26
L16.2.6x1.8A ..................................................................................................................................... 27
L20.3.2x1.8 ........................................................................................................................................ 28
L20.3x4.............................................................................................................................................. 29
FN6899.0
December 22, 2009
11
ISL95870, ISL95870A, ISL95870B
Absolute Maximum Ratings
Thermal Information
VCC, PVCC, PGOOD, FSEL to GND . . . . . . . . -0.3V to +7.0V
VCC, PVCC to PGND . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
EN, SET0, SET1, SET2, VO,
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
16 Ld µTQFN (Note 5). . . . . . . . . .
20 Ld µTQFN (Note 5). . . . . . . . . .
20 Ld QFN (Notes 6, 7). . . . . . . . .
Junction Temperature Range . . . . . . . . . . . -55°C to +150°C
Operating Temperature Range:
For “H” Version Parts. . . . . . . . . . . . . . . . -10°C to +100°C
For “I” Version Parts . . . . . . . . . . . . . . . . -40°C to +100°C
Storage Temperature. . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
90
88
44
N/A
N/A
5
VID0, VID1, FB, RTN, OCSET, SREF-0.3V to GND, VCC + 0.3V
BOOT Voltage (V
BOOT To PHASE Voltage (V
). . . . . . . . . . . . . . . -0.3V to 33V
BOOT-GND
) . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
BOOT-PHASE
PHASE Voltage. . . . . . . . . . . . . . . . . . . .GND - 0.3V to 28V
GND -8V (<20ns Pulse Width, 10µJ)
UGATE Voltage. . . . . . . . . . . . V
- 0.3V (DC) to V
PHASE
BOOT
- 5V (<20ns Pulse Width, 10µJ) to V
BOOT
V
PHASE
LGATE Voltage . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
. . . . . .GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . 1kV
Latch Up . . . . . . . . . . . . . . . . JEDEC Class II Level A at +125°C
Recommended Operating Conditions
Ambient Temperature Range:
For “H” Version Parts. . . . . . . . . . . . . . . . -10°C to +100°C
For “I” Version Parts . . . . . . . . . . . . . . . . -40°C to +100°C
Converter Input Voltage to GND . . . . . . . . . . . . 3.3V to 25V
VCC, PVCC to GND . . . . . . . . . . . . . . . . . . . . . . . .5V ±5%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
JA
TB379 for details.
6. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
JA
features. See Tech Brief TB379.
7. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications All typical specifications T = +25°C, VCC = 5V. Boldface limits apply over the operating
A
temperature range, -40°C to +100°C, unless otherwise stated.
MIN
MAX
PARAMETER
VCC and PVCC
SYMBOL
TEST CONDITIONS
(Note 11) TYP (Note 11) UNIT
VCC Input Bias Current
VCC Shutdown Current
I
EN = 5V, VCC = 5V, FB = 0.55V, SREF < FB
EN = GND, VCC = 5V
-
-
-
1.2
0
1.9
1.0
1.0
mA
µA
µA
VCC
I
VCCoff
PVCC Shutdown Current
VCC POR THRESHOLD
Rising VCC POR Threshold Voltage
Falling VCC POR Threshold Voltage
REGULATION
I
EN = GND, PVCC = 5V
0
PVCCoff
V
4.40
4.10
4.52
4.22
4.60
4.35
V
V
VCC_THR
V
VCC_THF
VID0 = VID1 = VCC, PWM Mode = CCM
-0.5
-
+0.5
%
(For “H” Version Parts, T = -10°C to
+100°C)
A
System Accuracy
PWM
VID0 = VID1 = VCC, PWM Mode = CCM
-0.75
-15
+0.5
+15
%
%
PWM Mode = CCM
(For “H” Version Parts, T = -10°C to
+100°C)
-
-
A
Switching Frequency Accuracy
F
SW
PWM Mode = CCM
-22
+15
%
VO
VO Input Impedance
VO Reference Offset Current
R
EN = 5V
-
-
600
8.5
-
-
kΩ
VO
I
V
< EN, SREF = Soft-Start Mode
ENTHR
µA
VOSS
FN6899.0
December 22, 2009
12
ISL95870, ISL95870A, ISL95870B
Electrical Specifications All typical specifications T = +25°C, VCC = 5V. Boldface limits apply over the operating
A
temperature range, -40°C to +100°C, unless otherwise stated. (Continued)
MIN
MAX
PARAMETER
VO Input Leakage Current
ERROR AMPLIFIER
FB Input Bias Current
SREF (Note 8)
SYMBOL
TEST CONDITIONS
EN = GND, VO = 3.6V
(Note 11) TYP (Note 11) UNIT
I
-
0
-
-
µA
nA
VOoff
I
EN = 5V, FB = 0.50V
-20
+50
FB
Soft-Start Current
I
SREF = Soft-Start Mode
8.5
17
85
25.5
µA
µA
SS
SREF = Setpoint-Stepping Mode
±51
±119
(For “H” Version Parts, T = -10°C to
+100°C)
A
Voltage Step Current
I
VS
SREF = Setpoint-Stepping Mode
±46
±85
±127
µA
POWER GOOD
PGOOD Pull-down Impedance
PGOOD Leakage Current
GATE DRIVER
R
PGOOD = 5mA Sink
PGOOD = 5V
-
-
50
150
1.0
Ω
PG
I
0.1
µA
PG
UGATE Pull-Up Resistance (Note 9)
UGATE Source Current (Note 9)
UGATE Sink Resistance (Note 9)
UGATE Sink Current (Note 9)
LGATE Pull-Up Resistance (Note 9)
LGATE Source Current (Note 9)
LGATE Sink Resistance (Note 9)
LGATE Sink Current (Note 9)
UGATE to LGATE Deadtime
LGATE to UGATE Deadtime
PHASE
R
200mA Source Current
UGATE - PHASE = 2.5V
250mA Sink Current
-
-
-
-
-
-
-
-
-
-
1.1
1.8
1.1
1.8
1.1
1.8
0.55
3.6
21
1.7
-
Ω
A
UGPU
I
UGSRC
R
1.7
-
Ω
A
UGPD
I
UGATE - PHASE = 2.5V
250mA Source Current
LGATE - GND = 2.5V
UGSNK
R
1.7
-
Ω
A
LGPU
I
LGSRC
R
250mA Sink Current
1.0
-
Ω
A
LGPD
I
LGATE - PGND = 2.5V
LGSNK
t
t
UGATE falling to LGATE rising, no load
LGATE falling to UGATE rising, no load
-
ns
ns
UGFLGR
LGFUGR
21
-
PHASE Input Impedance
BOOTSTRAP DIODE
R
-
33
-
kΩ
PHASE
Forward Voltage
V
PVCC = 5V, I = 2mA
F
-
-
0.58
0
-
-
V
F
Reverse Leakage
I
V
= 25V
R
µA
R
CONTROL INPUTS
EN High Threshold Voltage
EN Low Threshold Voltage
EN Input Bias Current
V
2.0
-
-
-
-
1.0
2.55
1.0
-
V
V
ENTHR
V
ENTHF
I
EN = 5V
0.85
-
1.7
0
µA
µA
V
EN
EN Leakage Current
I
EN = GND
ENoff
VID<0,1> High Threshold Voltage
(Note 10)
V
0.65
-
VIDTHR
VID<0,1> Low Threshold Voltage
(Note 10)
V
-
-
0.5
V
VIDTHF
VID<0,1> Input Bias Current (Note 10)
VID<0,1> Leakage Current (Note 10)
PROTECTION
I
EN = 5V
EN=0V
-
-
0.5
0
-
-
µA
µA
VID
I
VIDoff
FN6899.0
December 22, 2009
13
ISL95870, ISL95870A, ISL95870B
Electrical Specifications All typical specifications T = +25°C, VCC = 5V. Boldface limits apply over the operating
A
temperature range, -40°C to +100°C, unless otherwise stated. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
- V
(Note 11) TYP (Note 11) UNIT
OCP Threshold Voltage
V
V
-1.75
7.65
-
1.75
9.35
mV
µA
OCPTH
OCSET
O
EN = 5.0V
8.5
(For “H” Version Parts, T = -10°C to
A
+100°C)
OCP Reference Current
I
OCP
EN = 5.0V
EN = 5.0V
EN = GND
7.05
-
8.5
600
0
9.35
-
µA
kΩ
µA
%
OCSET Input Resistance
OCSET Leakage Current
UVP Threshold Voltage
R
OCSET
OCSET
I
-
-
V
V
= %V
81
113
84
87
120
UVTH
FB
FB
SREF
SREF
V
= %V
116
%
(For “H” Version Parts, T = -10°C to
A
OVP Rising Threshold Voltage
OVP Falling Threshold Voltage
V
V
OVRTH +100°C)
V
V
= %V
= %V
112.5
116
102
150
120
106
-
%
%
°C
FB
FB
SREF
SREF
98
-
OVFTH
OTRTH
OTP Rising Threshold Temperature
(Note 9)
T
OTP Hysteresis (Note 9)
NOTES:
T
-
25
-
°C
OTHYS
8. For ISL95870,there is one internal reference 0.5V. For ISL95870A, ISL95870B, there are four resistor-programmed reference
voltages.
9. Limits established by characterization and are not production tested.
10. VID function is only for ISL95870A, ISL95870B.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
FN6899.0
December 22, 2009
14
ISL95870, ISL95870A, ISL95870B
Where:
Theory of Operation
The following sections will provide a detailed description
of the inner workings of the ISL95870, ISL95870A,
ISL95870B.
- t
- I
is the soft-start delay
is the soft-start current source at the 17µA
SS
SS
limit
- V
is the buffered V
REF
reference voltage
SREF
Power-On Reset
Start-Up and Voltage-Step Operation for
ISL95870A, ISL95870B
When the voltage on the VCC pin has ramped above the
The IC is disabled until the voltage at the VCC pin has
increased above the rising power-on reset (POR)
threshold voltage V
disabled when the voltage at the VCC pin decreases
. The controller will become
VCC_THR
rising power-on reset voltage V
on the EN pin has increased above the rising enable
, and the voltage
VCC_THR
below the falling POR threshold voltage V . The
VCC_THF
POR detector has a noise filter of approximately 1µs.
threshold voltage V , the SREF pin releases its
ENTHR
discharge clamp and enables the reference amplifier
. The soft-start current I is limited to 17µA and is
Start-Up Timing
V
SET SS
Once VCC has ramped above V
, the controller
VCC_THR
sourced out of the SREF pin into the parallel RC network
of capacitor C and resistance R . The resistance R
can be enabled by pulling the EN pin voltage above the
input-high threshold V . Approximately 20µs later,
SOFT
T
T
ENTHR
is the sum of all the series connected R
programming
SET
the voltage at the SREF pin begins slewing to the
designated VID set-point. The converter output voltage
at the FB feedback pin follows the voltage at the SREF
pin. During soft-start, The regulator always operates in
CCM until the soft-start sequence is complete.
resistors and is written as Equation 3:
R
= R
+ R
+ …R
SET2 SET(n)
(EQ. 3)
T
SET1
The voltage on the SREF pin rises as I charges C
SS SOFT
to the voltage reference setpoint selected by the state of
the VID inputs at the time the EN pin is asserted. The
regulator controls the PWM such that the voltage on the
FB pin tracks the rising voltage on the SREF pin. Once
Start-Up and Voltage-Step Operation for
ISL95870
When the voltage on the VCC pin has ramped above the
rising power-on reset voltage VVCC_THR, and the voltage
on the EN pin has increased above the rising enable
threshold voltage VENTHR, the SREF pin releases its
discharge clamp, and enables the reference amplifier
C
charges to the selected setpoint voltage, the I
SOFT
SS
current source comes out of the 17µA current limit and
decays to the static value set by V /R . The elapsed
SREF
T
time from when the EN pin is asserted to when V
has reached the voltage reference setpoint is the
SREF
V
. The soft-start current I is limited to 17µA and is
SET SS
soft-start delay t which is given by Equation 4:
SS
sourced out of the SREF pin and charges capacitor C
until V
SOFT
V
START-UP
equals V . The regulator controls the PWM
SREF
REF
-----------------------------
(EQ. 4)
t
= –(R ⋅ C ) ⋅ LN(1 –
SOFT
)
SS
T
I
⋅ R
T
such that the voltage on the FB pin tracks the rising
voltage on the SREF pin. The elapsed time from when the
SS
Where:
EN pin is asserted to when V
has charged C
to
SREF
SOFT
V
is called the soft-start delay t
SS
which is given by
- I
SS
is the soft-start current source at the 17µA
limit
REF
Equation 1:
V
⋅ C
SOFT
SREF
- V is the setpoint reference voltage
START-UP
-------------------------------------------
(EQ. 1)
t
=
SS
I
selected by the state of the VID inputs at the time
EN is asserted
SS
Where:
- R is the sum of the R
SET
programming resistors
T
- I
is the soft-start current source at the 17µA
SS
limit
The end of soft-start is detected by I tapering off when
SS
capacitor C
charges to the designated V voltage
SOFT
SET
- V
is the buffered V reference voltage
REF
SREF
reference setpoint. The SSOK flag is set, and the PGOOD
pin goes high.
The end of soft-start is detected by I tapering off when
SS
capacitor C
charges to V . The internal SSOK flag
SOFT
REF
The I
SS
current source changes over to the voltage-step
which has a current limit of ±85µA.
is set, the PGOOD pin goes high, and diode emulation
mode (DEM) is enabled.
current source I
VS
Whenever the VID inputs or the external setpoint
reference programs a different setpoint reference
Choosing the C
of a particular soft-start delay t
SS
capacitor to meet the requirements
is calculated using
Equation 2, which is written as follows:
SOFT
voltage, the I
current source charges or discharges
VS
capacitor C
to that new level at ±85µA. Once C
SOFT
SOFT
t
⋅ I
charges to the selected setpoint voltage, the I
current
SS SS
V
VS
----------------------
C
=
(EQ. 2)
SOFT
source comes out of the 85µA current limit and decays to
the static value set by V /R . The elapsed time to
SREF
SREF
T
charge C
step delay t
to the new voltage is called the voltage-
SOFT
and is given by Equation 5:
VS
(V
– V
)
OLD
NEW
-------------------------------------------
)
(EQ. 5)
t
= –(R ⋅ C ) ⋅ LN(1 –
SOFT
VS
T
I
⋅ R
T
VS
FN6899.0
December 22, 2009
15
ISL95870, ISL95870A, ISL95870B
Where:
V
R
FB
OUT
FB
V
V
- I
VS
is the ±85µA setpoint voltage-step current;
> V , negative when V
NEW
OLD
is the new setpoint voltage selected by the
COMP
−
+
positive when V
EA
NEW
OLD
< V
- V
VID inputs
NEW
REF
+
V
- V
from
is the setpoint voltage that V
NEW
is changing
SET
OLD
−
- R is the sum of the R
programming resistors
capacitor to meet the requirements
T
SET
Choosing the C
SOFT
of a particular soft-start delay t
Equation 6, which is written as:
SREF
is calculated with
SS
–t
SS
---------------------------------------------------------------------
C
=
(EQ. 6)
SOFT
V
⎛
⎜
⎝
⎞
START-UP
-----------------------------
)
R
⋅ LN(1 –
⎟
⎠
T
I
⋅ R
T
SS
FIGURE 9. ISL95870 VOLTAGE PROGRAMMING
CIRCUIT
Where:
Output Voltage Programming for ISL95870A
- t
- I
limit
is the soft-start delay
is the soft-start current source at the 17µA
SS
The ISL95870A allows the user to select four different
reference voltages, thus four different output voltages,
by voltage identification pins VID1 and VID0. The
maximum reference voltage cannot be designed higher
than 1.5V. The implementation scheme is shown in
Figure 10. The setpoint reference voltages are
SS
- V
is the setpoint reference voltage
START-UP
selected by the state of the VID inputs at the time
EN is asserted
- R is the sum of the R
programming resistors
capacitor to meet the requirements
T
SET
programmed with resistors that use the naming
convention R
where (x) is the first, second, or
Choosing the C
SOFT
of a particular voltage-step delay t
Equation 7, which is written as:
SET(x)
third programming resistor connected in series starting
at the SREF pin and ending at the GND pin. As shown in
Table 1, different combinations of VID1 and VID0 closes
different switches and leaves other switches open. For
example, for the case of VID1 = 1 and VID0 = 0, switch
SW1 closes and all the other three switches SW0, SW2
and SW3 are open. For one combination of VID1 and
VID0, the internal switch connects the inverting input of
is calculated with
VS
–t
VS
-----------------------------------------------------------------------------
C
=
(EQ. 7)
SOFT
V
– V
⎛
⎜
⎝
⎞
NEW
OLD
⋅ R
T
--------------------------------------
)
R
⋅ LN(1 –
⎟
⎠
T
I
VS
Where:
- t
VS
- V
- V
is the voltage-step delay
is the new setpoint voltage
the V
amplifier to a specific node among the string of
SET
programming resistors. All the resistors between
R
NEW
SET
that node and the SREF pin serve as the feedback
is the setpoint voltage that V is changing
OLD
NEW
impedance R of the V
amplifier. Likewise, all the
from
- I is the ±85µA setpoint voltage-step current;
F
SET
resistors between that node and the GND pin serve as
the input impedance R of the V amplifier.
VS
positive when V
IN SET
> V
, negative when V
NEW
OLD
NEW
Equation 9 gives the general form of the gain equation
for the V amplifier:
< V
OLD
- R is the sum of the R
SET
= V
programming resistors
SET
T
R
⎛
⎞
⎟
⎠
F
(EQ. 9)
---------
V
⋅ 1 +
⎜
SETX
REF
Output Voltage Programming for ISL95870
R
⎝
IN
The ISL95870 has a fixed 0.5V reference voltage
Where:
(V
). As shown in Figure 9, the output voltage is the
SREF
reference voltage if R is shorted and R
FB OFS
resistor divider consisting of R
is open. A
- V
- V
is the 0.5V internal reference of the IC
is the resulting setpoint reference voltage
REF
and R allows the
OFS FB
SETx
user to scale the output voltage between 0.5V and 5V.
The relation between the output voltage and the
reference voltage is given in Equation 8:
that appears at the SREF pin
TABLE 1. ISL95870A VID TRUTH TABLE
R
+ R
VID STATE
RESULT
FB
OFS
(EQ. 8)
---------------------------------
V
= V
⋅
OUT
SREF
R
OFS
VID1
VID0
CLOSE
SW0
V
V
SREF
OUT
OUT1
OUT2
OUT3
1
1
0
1
0
1
V
V
V
V
V
V
SET1
SET2
SET3
SW1
SW2
FN6899.0
December 22, 2009
16
ISL95870, ISL95870A, ISL95870B
TABLE 1. ISL95870A VID TRUTH TABLE (Continued)
VID STATE RESULT
V
R
FB
OUT
FB
V
COMP
−
+
EA
VID1
VID0
CLOSE
V
V
OUT
SREF
0
0
SW1, SW3
V
V
OUT4
SET4
V
REF
0.5V
+
SET
Equations 10, 11, 12 and 13 give the specific V
SET
equations for the ISL95870A setpoint reference voltages.
V
−
The ISL95870A V
setpoint is written as Equation 10:
(EQ. 10)
SET1
SW0
SW1
SW2
SW3
V
= V
SET1
REF
SREF
SET0
SET1
The ISL95870A V
setpoint is written as Equation 11:
SET2
R
⎛
⎞
⎟
⎠
SET1
+ R
SET3
(EQ. 11)
-------------------------------------------
V
= V
⋅ 1 +
⎜
SET2
REF
R
⎝
SET2
The ISL95870A V
setpoint is written as Equation 12:
SET3
R
+ R
⎛
⎞
⎟
⎠
SET1
SET2
(EQ. 12)
-------------------------------------------
V
= V
⋅ 1 +
⎜
SET3
REF
R
⎝
SET3
The ISL95870A V
setpoint is written as Equation 13:
SET4
R
⎛
⎞
⎟
⎠
SET1
------------------
(EQ. 13)
V
= V
⋅ 1 +
⎜
SET4
REF
R
⎝
SET2
The V
is fixed at 0.5V because it corresponds to the
SET1
FIGURE 10. ISL95870A VOLTAGE PROGRAMMING
CIRCUIT
closure of internal switch SW0 that configures the V
SET
amplifier as a unity-gain voltage follower for the 0.5V
voltage reference V . Theoretically, V can be
If the output voltage is in the range of 0.5V to 1.5V, the
external resistor-divider is not necessary. The output
voltage is equal to one of the reference voltages
REF SET3
higher or lower or equal to V
selection of R
recommended to design the four reference voltages in
the following order:
depending on the
SET4
and R
, R
. However, it is
SET1 SET2
SET3
depending on the status of VID1 and VID0. The external
resistor divider consisting of R and R
allows the
FB OFS
user to program the output voltage in the range of 1.5V
to 5V. The relation between the output voltage and the
reference voltage is given in Equation 18:
- V
- V
< V
< V
< V
< V
< V
< V
Thus,
SET1
SET2
SET3
SET4
OUT1
OUT2
OUT3
OUT4
For given four user selected reference voltages V
the following equation needs to be satisfied in order to
have non-zero solution for R
,
R
+ R
SETx
FB
OFS
(EQ. 18)
---------------------------------
V
= V
⋅
= V
⋅ k
SREF
OUT
SREF
R
OFS
.
SETx
–V
In this case, the four output voltages are equal to each of
the corresponding reference voltages multiplying the
factor k.
V
⋅ V
+ V
⋅ V
⋅ V
–V
⋅ V
= 0
SET4
SET1
SET2
SET4
SET2
SET3
SET2
SET3
(EQ. 14)
V
= V
⋅ k
SETx
(EQ. 19)
OUTx
The programmed resistors R
, R
and R are
SET3
SET1 SET2
designed in the following way. First, assign an initial
value to R of approximately 100kΩ then calculate
Output Voltage Programming for ISL95870B
SET3
and R
The ISL95870B allows the user to select four different
reference voltages, thus four different output voltages,
by voltage identification pins VID1 and VID0. The
maximum reference voltage cannot be designed higher
than 1.5V. The implementation scheme is shown in
Figure 11. The setpoint reference voltages are
R
using Equations 15 and 16 respectively.
SET1
SET2
⋅ (V
R
– V
) ⋅ (V
– V
)
REF
SET3
SET4
REF
SET2
---------------------------------------------------------------------------------------------------------------------
R
R
=
=
(EQ. 15)
(EQ. 16)
SET1
SET2
V
⋅ (V
– V
)
SET2
REF
SET4
R
⋅ (V
– V
)
REF
SET3
SET2
-------------------------------------------------------------------
– V
V
SET4
SET2
programmed with resistors that use the naming
convention R
where (x) is the first, second, third,
The sum of all the programming resistors should be
SET(x)
or fourth programming resistor connected in series
starting at the SREF pin and ending at the GND pin. As
shown in Table 2, different combinations of VID1 and
VID0 close different switches and leave other switches
open. For example, for the case of VID1 = 1 and
VID0 = 0, switch SW1 closes and all the other three
switches SW0, SW2 and SW3 are open. For one
combination of VID1 and VID0, the internal switch
approximately 300kΩ, as shown in Equation 17,
otherwise adjust the value of R
calculations.
and repeat the
SET3
R
+ R
+ R ≅ 300kΩ
SET3
(EQ. 17)
SET1
SET2
FN6899.0
December 22, 2009
17
ISL95870, ISL95870A, ISL95870B
connects the inverting input of the V
amplifier to a
programming
calculate R
26, and 27 respectively.
R
and R
using Equations 25,
SET
SET1, SET2
SET3
specific node among the string of R
resistors. All the resistors between that node and the
SET
R
⋅ V
⋅ (V
– V
REF
)
SET4
SET4
SET2
------------------------------------------------------------------------------------------
R
=
(EQ. 25)
(EQ. 26)
SET1
SREF pin serve as the feedback impedance R of the
V
⋅ V
SET2
F
REF
V
amplifier. Likewise, all the resistors between that
SET
node and the GND pin serve as the input impedance R
R
⋅ V
⋅ (V
– V
)
SET2
SET4
SET4
SET3
---------------------------------------------------------------------------------------------
R
=
IN
SET2
V
⋅ V
SET3
SET2
of the V
of the gain equation for the V
amplifier. Equation 20 gives the general form
SET
amplifier:
SET
R
⋅ (V
– V
)
SET3
SET4
SET4
----------------------------------------------------------------------
R
R
=
(EQ. 27)
⎛
⎞
⎟
⎠
F
SET3
V
---------
V
= V
⋅ 1 +
(EQ. 20)
⎜
SET3
SETX
REF
R
⎝
IN
The sum of all the programming resistors should be
approximately 300kΩ, as shown in Equation 28,
Where:
- V
otherwise adjust the value of R
calculations.
and repeat the
is the 0.5V internal reference of the IC
is the resulting setpoint reference voltage
SET4
REF
- V
SETx
R
+ R
+ R
+ R ≅ 300kΩ
SET4
that appears at the SREF pin
(EQ. 28)
SET1
SET2
SET3
TABLE 2. ISL95870B VID TRUTH TABLE
VID STATE
RESULT
V
R
FB
OUT
FB
VID1
VID0
CLOSE
SW0
V
V
V
COMP
SREF
OUT
OUT1
OUT2
OUT3
OUT4
−
EA
+
1
1
0
0
1
0
1
0
V
V
V
V
V
V
V
V
SET1
SET2
SET3
SET4
SW1
V
REF
0.5V
SW2
+
SET
V
SW3
−
Equations 21, 22, 23 and 24 give the specific V
SET
equations for the ISL95870B setpoint reference voltages.
SW0
SW1
SW2
SW3
SREF
SET0
SET1
SET2
The ISL95870B V
setpoint is written as Equation 21:
(EQ. 21)
SET1
V
= V
SET1
REF
The ISL95870B V
setpoint is written as Equation 22:
SET2
R
⎛
⎞
⎟
⎠
SET1
+ R
SET3 SET4
--------------------------------------------------------------------
V
= V
⋅ 1 +
(EQ. 22)
⎜
SET2
REF
R
+ R
⎝
SET2
The ISL95870B V
setpoint is written as Equation 23:
SET3
R
+ R
⎛
⎞
⎟
⎠
SET1
SET2
-------------------------------------------
V
= V
⋅ 1 +
(EQ. 23)
⎜
SET3
REF
R
+ R
SET4
⎝
SET3
The ISL95870B V
setpoint is written as Equation 24:
SET4
R
+ R
+ R
SET2
⎛
⎞
⎟
⎠
SET1
SET3
(EQ. 24)
--------------------------------------------------------------------
V
= V
⋅ 1 +
⎜
SET4
REF
R
⎝
SET4
FIGURE 11. ISL95870B VOLTAGE PROGRAMMING
CIRCUIT
The V
is fixed at 0.5V because it corresponds to the
SET1
If the output voltage is in the range of 0.5V to 1.5V, the
external resistor-divider is not necessary. The output
voltage is equal to one of the reference voltages
closure of internal switch SW0 that configures the V
SET
amplifier as a unity-gain voltage follower for the 0.5V
voltage reference V . The setpoint reference voltages
REF
use the naming convention V
depending on the status of VID1 and VID0. The external
where (x) is the first,
SET(x)
resistor divider consisting of R and R
allows the
FB OFS
second, third, or fourth setpoint reference voltage
where:
user to program the output voltage in the range of 1.5V
to 5V. The relation between the output voltage and the
reference is given in Equation 29:
- V
- V
< V
< V
< V
< V
< V
< V
Thus,
SET1
SET2
SET3
SET4
R
+ R
OUT1
OUT2
OUT3
OUT4
FB
OFS
(EQ. 29)
---------------------------------
V
= V
⋅
= V
⋅ k
SREF
OUT
SREF
For given four user selected reference voltages V
the programmed resistors R
,
R
SETx
OFS
, R
, R
and
are designed in the following way. First, assign an
SET1
SET2
SET3
R
SET4
initial value to R
In this case, the four output voltages are equal to each of
the corresponding reference voltages multiplying the
factor k.
of approximately 100kΩ then
SET4
(EQ. 30)
V
= V
⋅ k
SETx
OUTx
FN6899.0
December 22, 2009
18
ISL95870, ISL95870A, ISL95870B
High Output Voltage Programming
The ISL95870 has a fixed 0.5V reference voltage
(V ). For high output voltage application, the resistor
COMPENSATION TO COUNTER
INTEGRATOR POLE
INTEGRATOR
FOR HIGH DC GAIN
SREF
divider consisting of R and R
requires large ratio
FB OFS
(R :R
= 9:1 for 5V output). The FB pin with large
FB OFS
V
OUT
ratio resistor divider is noise sensitive and the PCB layout
should be carefully routed. It is recommended to use
V
V
COMP
small value resistor divider such as R =1kΩ.
FB
V
In general the ISL95870A and ISL95870B have much
better jitter performance than the ISL95870 when the
output voltage is in the range of 3.3V to 5V, particularly
DAC
FIGURE 12. INTEGRATOR ERROR-AMPLIFIER
CONFIGURATION
in DCM. This is because V
voltage can be set to 1.5V
SREF
and a smaller ratio resistor divider can be used. This
makes the singal to noise ratio at FB pin much better. So
for 3.3V to 5V output, the ISL95870A and ISL95870B are
R3 LOOP GAIN (dB)
INTEGRATOR POLE
recommended with V
set to 1.5V.
SREF
p1
L/C DOUBLE-POLE
R4 Modulator
The R modulator is an evolutionary step in R
technology. Like R , the R modulator allows variable
frequency in response to load transients and maintains
the benefits of current-mode hysteretic controllers.
4
3
3
4
p2
-20dB CROSSOVER
REQUIRED FOR STABILITY
p3
4
However, in addition, the R modulator reduces regulator
COMPENSATOR TO
ADD z2 IS NEEDED
CURRENT-MODE
ZERO
output impedance and uses accurate referencing to
eliminate the need for a high-gain voltage amplifier in
the compensation loop. The result is a topology that can
be tuned to voltage-mode hysteretic transient speed
while maintaining a linear control model and removes the
need for any compensation. This greatly simplifies the
regulator design for customers and reduces external
component cost.
z1
f (Hz)
FIGURE 13. UNCOMPENSATED INTEGRATOR
OPEN-LOOP RESPONSE
Stability
Figure 12 illustrates the classic integrator configuration
for a voltage loop error-amplifier. While the integrator
provides the high DC gain required for accurate
regulation in traditional technologies, it also introduces a
low-frequency pole into the control loop. Figure 13 shows
the open-loop response that results from the addition of
an integrating capacitor in the voltage loop. The
compensation components found in Figure 12 are
necessary to achieve stability.
4
The removal of compensation derives from the R
modulator’s lack of need for high DC gain. In traditional
architectures, high DC gain is achieved with an
integrator in the voltage loop. The integrator introduces
a pole in the open-loop transfer function at low
frequencies. That, combined with the double-pole from
the output L/C filter, creates a three pole system that
must be compensated to maintain stability.
Classic control theory requires a single-pole transition
through unity gain to ensure a stable system.
4
Because R does not require a high-gain voltage loop,
the integrator can be removed, reducing the number of
inherent poles in the loop to two. The current-mode zero
continues to cancel one of the poles, ensuring a
single-pole crossover for a wide range of output filter
choices. The result is a stable system with no need for
compensation components or complex equations to
properly tune the stability.
Current-mode architectures (includes peak, peak-valley,
3
4
current-mode hysteretic, R and R ) generate a zero at
or near the L/C resonant point, effectively canceling one
of the system’s poles. The system still contains two
poles, one of which must be canceled with a zero before
unity gain crossover to achieve stability. Compensation
components are added to introduce the necessary zero.
R2
V
OUT
V
COMP
R1
V
DAC
FIGURE 14. NON-INTEGRATED R4 ERROR-AMPLIFIER
CONFIGURATION
FN6899.0
December 22, 2009
19
ISL95870, ISL95870A, ISL95870B
4
Figure 14 shows the R error-amplifier that does not
require an integrator for high DC gain to achieve
accurate regulation. The result to the open loop response
can be seen in Figure 15.
current, can be either positive or negative. Should the
sum of the AC and DC components of the inductor
current remain positive for the entire switching period,
the converter is in continuous-conduction-mode (CCM).
However, if the inductor current becomes negative or
zero, the converter is in discontinuous-conduction-mode
(DCM).
R4 LOOP GAIN (dB)
L/C DOUBLE-POLE
Unlike the standard DC/DC buck regulator, the
synchronous rectifier can sink current from the output
filter inductor during DCM, reducing the light-load
efficiency with unnecessary conduction loss as the
low-side MOSFET sinks the inductor current. The
ISL95870, ISL95870A, ISL95870B controllers avoid the
DCM conduction loss by making the low-side MOSFET
emulate the current-blocking behavior of a diode. This
smart-diode operation called diode-emulation-mode
(DEM) is triggered when the negative inductor current
p1
SYSTEM HAS 2 POLES
p2
AND 1 ZERO
NO COMPENSATOR IS
NEEDED
CURRENT-MODE
ZERO
z1
produces a positive voltage drop across the r
of
DS(ON)
f (Hz)
the low-side MOSFET for eight consecutive PWM cycles
while the LGATE pin is high. The converter will exit DEM
on the next PWM pulse after detecting a negative voltage
FIGURE 15. UNCOMPENSATED R4 OPEN-LOOP
RESPONSE
across the r
of the low-side MOSFET.
DS(ON)
Transient Response
4
It is characteristic of the R architecture for the PWM
switching frequency to decrease while in DCM, increasing
efficiency by reducing unnecessary gate-driver switching
losses. The extent of the frequency reduction is
In addition to requiring a compensation zero, the
integrator in traditional architectures also slows system
response to transient conditions. The change in COMP
voltage is slow in response to a rapid change in output
voltage. If the integrating capacitor is removed, COMP
moves as quickly as VOUT, and the modulator
immediately increases or decreases switching frequency
to recover the output voltage.
proportional to the reduction of load current. Upon
entering DEM, the PWM frequency is forced to fall
approximately 30% by forcing a similar increase of the
window voltage V . This measure is taken to prevent
oscillating between modes at the boundary between CCM
W
and DCM. The 30% increase of V is removed upon exit
of DEM, forcing the PWM switching frequency to jump
back to the nominal CCM value.
W
I
OUT
t
t
R4
R3
Overcurrent
The overcurrent protection (OCP) setpoint is
V
COMP
programmed with resistor R
across the OCSET and PHASE pins. Resistor R is
, which is connected
OCSET
O
connected between the VO pin and the actual output
voltage of the converter. During normal operation, the
VO pin is a high impedance path, therefore there is no
V
OUT
voltage drop across R . The value of resistor R should
O
O
t
always match the value of resistor R
.
OCSET
FIGURE 16. R3 vs R4 IDEALIZED TRANSIENT
RESPONSE
L
DCR
V
I
O
L
PHASE
_
The dotted red and blue lines in Figure 16 represent the
V
+
DCR
C
time delayed behavior of V
a load transient when an integrator is used. The solid red
and V in response to
SEN
OUT
COMP
R
OCSET
C
O
4
_
and blue lines illustrate the increased response of R in
the absence of the integrator capacitor.
8.5µA
OCSET
V
+
ROCSET
R
O
Diode Emulation
VO
The polarity of the output inductor current is defined as
positive when conducting away from the phase node,
and defined as negative when conducting towards the
phase node. The DC component of the inductor current is
positive, but the AC component known as the ripple
FIGURE 17. OVERCURRENT PROGRAMMING CIRCUIT
FN6899.0
December 22, 2009
20
ISL95870, ISL95870A, ISL95870B
Figure 17 shows the overcurrent set circuit. The inductor
consists of inductance L and the DC resistance DCR. The
116% for more than 2µs in order to trip the OVP fault
latch. In numerical terms, that would be
inductor DC current I creates a voltage drop across
DCR, which is given by Equation 31:
116% x 1.0V = 1.16V. When an OVP fault is declared,
the converter will be latched off and the PGOOD pin will
be asserted low. The fault will remain latched until the EN
pin has been pulled below the falling EN threshold
L
(EQ. 31)
V
= I ⋅ DCR
DCR
L
The I
current source sinks 8.5µA into the OCSET
pin, creating a DC voltage drop across the resistor
voltage V
POR threshold voltage
or if VCC has decayed below the falling
OCSET
ENTHF
V
.
VCC_THF
R
, which is given by Equation 32:
OCSET
Although the converter has latched-off in response to an
OVP fault, the LGATE gate-driver output will retain the
ability to toggle the low-side MOSFET on and off, in
response to the output voltage transversing the V
and V
OVFTH
on the low-side MOSFET to discharge the output voltage,
protecting the load. The LGATE gate-driver will turn-off
the low-side MOSFET once the FB pin voltage is lower
than the falling overvoltage threshold V
than 2µs. The falling overvoltage threshold V
typically 102%. That means if the FB pin voltage falls
below 102% x 1.0V = 1.02V for more than 2µs, the
LGATE gate-driver will turn off the low-side MOSFET. If
the output voltage rises again, the LGATE driver will
again turn on the low-side MOSFET when the FB pin
voltage is above the rising overvoltage threshold
(EQ. 32)
V
= 8.5μA ⋅ R
ROCSET
OCSET
The DC voltage difference between the OCSET pin and
the VO pin, which is given by Equation 33:
OVRTH
thresholds. The LGATE gate-driver will turn-
V
– V
= V
– V
=I ⋅DCR – I
⋅ R
OCSET OCSET
OCSET
VO
DCR
ROCSET
L
(EQ. 33)
The IC monitors the voltage of the OCSET pin and the VO
pin. When the voltage of the OCSET pin is higher than
the voltage of the VO pin for more than 10µs, an OCP
fault latches the converter off.
for more
OVRTH
is
OVFTH
The value of R
OCSET
which is written as:
is calculated with Equation 34,
I
⋅ DCR
(EQ. 34)
OC
I
---------------------------
R
=
OCSET
OCSET
V
for more than 2µs. By doing so, the IC protects
OVRTH
the load when there is a consistent overvoltage
Where:
condition.
- R
(Ω) is the resistor used to program the
OCSET
Undervoltage
overcurrent setpoint
The UVP fault detection circuit triggers after the FB pin
- I
is the output DC load current that will activate
OC
voltage is below the undervoltage threshold V
for
the OCP fault detection circuit
UVTH
more than 2µs. For example if the converter is
programmed to regulate 1.0V at the FB pin, that voltage
would have to fall below the typical V threshold of
84% for more than 2µs in order to trip the UVP fault
latch. In numerical terms, that would be
- DCR is the inductor DC resistance
For example, if I
of R
OCSET
is 20A and DCR is 4.5mΩ, the choice
is equal to 20A x 4.5mΩ/8.5µA = 10.5kΩ.
OC
UVTH
Resistor R
OCSET
and capacitor C form an R-C
SEN
network to sense the inductor current. To sense the
inductor current correctly not only in DC operation, but
also during dynamic operation, the R-C network time
84% x 1.0V = 0.84V. When a UVP fault is declared, the
converter will be latched off and the PGOOD pin will be
asserted low. The fault will remain latched until the EN
pin has been pulled below the falling EN threshold
constant R
constant L/DCR. The value of C
Equation 35:
C
needs to match the inductor time
OCSET SEN
is then written as
voltage V
POR threshold voltage
or if VCC has decayed below the falling
SEN
ENTHF
V
.
VCC_THF
L
------------------------------------------
C
=
(EQ. 35)
is
SEN
Over-Temperature
R
⋅ DCR
OCSET
When the temperature of the IC increases above the
rising threshold temperature T , it will enter the OTP
For example, if L is 1.5µH, DCR is 4.5mΩ, and R
9kΩ, the choice of C
OCSET
OTRTH
= 1.5µH/(9kΩ x 4.5mΩ) = 0.037µF.
state that suspends the PWM, forcing the LGATE and
UGATE gate-driver outputs low. The status of the PGOOD
pin does not change nor does the converter latch-off. The
PWM remains suspended until the IC temperature falls
SEN
When an OCP fault is declared, the converter will be
latched off and the PGOOD pin will be asserted low. The
fault will remain latched until the EN pin has been pulled
below the hysteresis temperature T
at which time
OTHYS
below the falling EN threshold voltage V
or if VCC
ENTHF
normal PWM operation resumes. The OTP state can be
reset if the EN pin is pulled below the falling EN threshold
has decayed below the falling POR threshold voltage
V
.
VCC_THF
voltage V
POR threshold voltage
or if VCC has decayed below the falling
ENTHF
V
Overvoltage
. All other protection
VCC_THF
circuits remain functional while the IC is in the OTP state.
It is likely that the IC will detect an UVP fault because in
the absence of PWM, the output voltage decays below
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold V
for more than 2µs. For example, if the converter is
OVRTH
the undervoltage threshold V
.
UVTH
programmed to regulate 1.0V at the FB pin, that voltage
would have to rise above the typical V
threshold of
OVRTH
FN6899.0
December 22, 2009
21
ISL95870, ISL95870A, ISL95870B
PGOOD Monitor
The PGOOD pin indicates when the converter is capable
of supplying regulated voltage. The PGOOD pin is an
undefined impedance if the VCC pin has not reached the
rising POR threshold V
below the falling POR threshold V
VCC_THF
, or if the VCC pin is
. If there is a
VCC_THR
UGATE
fault condition of output overcurrent, overvoltage or
undervoltage, PGOOD is asserted low. The PGOOD
pull-down impedance is 50Ω.
1V
1V
1V
1V
Integrated MOSFET Gate-Drivers
The LGATE pin and UGATE pins are MOSFET driver
outputs. The LGATE pin drives the low-side MOSFET of
the converter while the UGATE pin drives the high-side
MOSFET of the converter.
LGATE
The LGATE driver is optimized for low duty-cycle
applications where the low-side MOSFET experiences
long conduction times. In this environment, the low-side
FIGURE 18. GATE DRIVE ADAPTIVE SHOOT-THROUGH
PROTECTION
MOSFETs require exceptionally low r
and tend to
DS(ON)
have large parasitic charges that conduct transient
currents within the devices in response to high dv/dt
switching present at the phase node. The drain-gate
charge in particular can conduct sufficient current
General Application Design
Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a single-
phase buck converter. It is assumed that the reader is
familiar with many of the basic skills and techniques
referenced in the following. In addition to this guide,
Intersil provides complete reference designs that
include schematics, bills of materials, and example
board layouts.
through the driver pull-down resistance that the V
GS(th)
of the device can be exceeded and turned on. For this
reason, the LGATE driver has been designed with low
pull-down resistance and high sink current capability to
ensure clamping the MOSFETs gate voltage below
V
.
GS(th)
Adaptive Shoot-Through Protection
Adaptive shoot-through protection prevents a gate-driver
output from turning on until the opposite gate-driver
output has fallen below approximately 1V. The dead-time
shown in Figure 18 is extended by the additional period
that the falling gate voltage remains above the 1V
threshold. The high-side gate-driver output voltage is
measured across the UGATE and PHASE pins while the
low-side gate-driver output voltage is measured across
the LGATE and PGND pins. The power for the LGATE
gate-driver is sourced directly from the PVCC pin.
The-power for the UGATE gate-driver is supplied by a
boot-strap capacitor connected across the BOOT and
PHASE pins. The capacitor is charged each time the
phase node voltage falls a diode drop below PVCC such
as when the low-side MOSFET is turned on.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of
the input and the output voltage. This relationship is
expressed in Equation 36:
V
O
(EQ. 36)
---------
D =
V
IN
The output inductor peak-to-peak ripple current is
expressed in Equation 37:
V
⋅ (1 – D)
O
F
(EQ. 37)
------------------------------
=
I
P-P
⋅ L
SW
A typical step-down DC/DC converter will have an I of
PP
20% to 40% of the maximum DC output load current.
The value of I
is selected based upon several criteria
P-P
such as MOSFET switching loss, inductor core loss, and
the resistive loss of the inductor winding. The DC copper
loss of the inductor can be estimated using Equation 38:
2
(EQ. 38)
P
= I
⋅ DCR
COPPER
LOAD
Where, I
is the converter output DC current.
LOAD
The copper loss can be significant so attention has to be
given to the DCR of the inductor. Another factor to
consider when choosing the inductor is its saturation
characteristics at elevated temperature. A saturated
inductor could cause destruction of circuit components,
as well as nuisance OCP faults.
FN6899.0
December 22, 2009
22
ISL95870, ISL95870A, ISL95870B
A DC/DC buck regulator must have output capacitance
C into which ripple current I can flow. Current I
drain of the high-side MOSFET and the source of the
low-side MOSFET.
O
P-P P-P
develops a corresponding ripple voltage V
across C
0.6
0.5
0.4
0.3
0.2
0.1
0
P-P O,
which is the sum of the voltage drop across the capacitor
ESR and of the voltage change stemming from charge
moved in and out of the capacitor. These two voltages
are expressed in Equations 39 and 40:
x = 0
x = 0.5
(EQ. 39)
ΔV
= I
⋅ ESR
ESR
P-P
I
P-P
x = 1
(EQ. 40)
---------------------------------
ΔV
=
C
8 ⋅ C ⋅ F
O
SW
If the output of the converter has to support a load with
high pulsating current, several capacitors will need to be
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DUTY CYCLE
paralleled to reduce the total ESR until the required V
is achieved. The inductance of the capacitor can
P-P
FIGURE 19. NORMALIZED INPUT RMS CURRENT FOR
EFF = 1
significantly impact the output voltage ripple and cause
a brief voltage spike if the load transient has an
extremely high slew rate. Low inductance capacitors
should be considered. A capacitor dissipates heat as a
Selecting the Bootstrap Capacitor
The integrated driver features an internal bootstrap
schottky diode. Simply adding an external capacitor
across the BOOT and PHASE pins completes the
bootstrap circuit. The bootstrap capacitor voltage rating
is selected to be at least 10V. Although the theoretical
function of RMS current and frequency. Be sure that I
is shared by a sufficient quantity of paralleled capacitors
P-P
so that they operate below the maximum rated RMS
current at F . Take into account that the rated value of
SW
a capacitor can fade as much as 50% as the DC voltage
across it increases.
maximum voltage of the capacitor is PVCC-V
DIODE
(voltage drop across the boot diode), large excursions
below ground by the phase node requires at least a 10V
rating for the bootstrap capacitor. The bootstrap
capacitor can be chosen from Equation 43:
Q
Selecting the Input Capacitor
The important parameters for the bulk input capacitors
are the voltage rating and the RMS current rating. For
reliable operation, select bulk capacitors with voltage and
current ratings above the maximum input voltage and
capable of supplying the RMS current required by the
switching circuit. Their voltage rating should be at least
1.25x greater than the maximum input voltage, while a
voltage rating of 1.5x is a preferred rating. Figure 19 is a
graph of the input RMS ripple current, normalized
relative to output load current, as a function of duty
cycle that is adjusted for converter efficiency. The ripple
current calculation is written as Equation 41:
GATE
(EQ. 43)
-----------------------
≥
C
BOOT
ΔV
BOOT
Where:
- Q
is the amount of gate charge required to
GATE
fully charge the gate of the upper MOSFET
- ΔV is the maximum decay across the BOOT
BOOT
capacitor
As an example, suppose the high-side MOSFET has a
total gate charge Q , of 25nC at V
ΔV
BOOT
= 5V, and a
of 200mV. The calculated bootstrap capacitance
g
GS
2
2
2
2
D
12
⎛
⎞
⎠
------
(I
⋅ (D – D )) + x ⋅ I
⋅
(EQ. 41)
MAX
MAX
⎝
--------------------------------------------------------------------------------------------------------
I
=
is 0.125µF; for a comfortable margin, select a capacitor
that is double the calculated capacitance. In this
example, 0.22µF will suffice. Use a low
IN_RMS
I
MAX
Where:
temperature-coefficient ceramic capacitor.
- I
converter
is the maximum continuous I of the
LOAD
MAX
Driver Power Dissipation
Switching power dissipation in the driver is mainly a
function of the switching frequency and total gate charge
of the selected MOSFETs. Calculating the power
dissipation in the driver for a desired application is critical
to ensuring safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond
the maximum recommended operating junction
temperature of +125°C. When designing the application,
it is recommended that the following calculation be
performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power
- x is a multiplier (0 to 1) corresponding to the
inductor peak-to-peak ripple amplitude expressed
as a percentage of I
(0% to 100%)
MAX
- D is the duty cycle that is adjusted to take into
account the efficiency of the converter
Duty cycle is written as Equation 42:
V
O
(EQ. 42)
--------------------------
D =
V
⋅ EFF
IN
In addition to the bulk capacitors, some low ESL ceramic
capacitors are recommended to decouple between the
FN6899.0
December 22, 2009
23
ISL95870, ISL95870A, ISL95870B
dissipated by the drivers is approximated as
Equation 44:
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as
Equation 45:
(EQ. 44)
P = F (1.5V
Q + V Q ) + P + P
L L U
U L
sw
U
2
(EQ. 45)
P
≈ I
⋅ r
⋅ (1 – D)
DS(ON)_LS
CON_LS
LOAD
Where:
For the high-side MOSFET, (HS), its conduction loss is
written as Equation 46:
- F
sw
is the switching frequency of the PWM signal
- V is the upper gate driver bias supply voltage
U
2
(EQ. 46)
- V is the lower gate driver bias supply voltage
L
P
= I
⋅ r
⋅ D
DS(ON)_HS
CON_HS
LOAD
- Q is the charge to be delivered by the upper
U
driver into the gate of the MOSFET and discrete
capacitors
For the high-side MOSFET, its switching loss is written as
Equation 47:
- Q is the charge to be delivered by the lower driver
L
into the gate of the MOSFET and discrete
capacitors
V
⋅ I
⋅ t
⋅ F
V
⋅ I
⋅ t
⋅ F
IN PEAK OFF
SW
IN VALLEY ON
SW
--------------------------------------------------------------------- -----------------------------------------------------------------
P
=
+
SW_HS
2
2
- P is the quiescent power consumption of the lower
L
(EQ. 47)
driver
- P is the quiescent power consumption of the
upper driver
Where:
U
- I
is the difference of the DC component of
VALLEY
the inductor current minus 1/2 of the inductor
ripple current
1000
Q =100nC
U
Q =50nC
U
Q =50nC
U
Q =100nC
L
Q =200nC
900
800
700
600
500
400
300
200
100
0
L
- I
is the sum of the DC component of the
Q =50nC
L
PEAK
inductor current plus 1/2 of the inductor ripple
current
- t
is the time required to drive the device into
saturation
ON
Q =20nC
U
Q =50nC
L
- t
cut-off
is the time required to drive the device into
OFF
Layout Considerations
As a general rule, power layers should be close together,
either on the top or bottom of the board, with the weak
analog or logic signal layers on the opposite side of the
board. The ground-plane layer should be adjacent to the
signal layer to provide shielding. The ground plane layer
should have an island located under the IC, the
components connected to analog or logic signals. The
island should be connected to the rest of the ground
plane layer at one quiet point.
0
200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
FREQUENCY (Hz)
FIGURE 20. POWER DISSIPATION vs FREQUENCY
MOSFET Selection and Considerations
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching
frequency, the capability of the MOSFETs to dissipate
heat, and the availability and nature of heat sinking and
air flow.
There are two sets of components in a DC/DC converter,
the power components and the small signal components.
The power components are the most critical because
they switch large amount of energy. The small signal
components connect to sensitive nodes or supply critical
bypassing current and signal coupling.
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating.
The MOSFETs used in the power stage of the converter
The power components should be placed first and these
include MOSFETs, input and output capacitors, and the
inductor. Keeping the distance between the power train
and the control IC short helps keep the gate drive traces
short. These drive signals include the LGATE, UGATE,
PGND, PHASE and BOOT.
should have a maximum V
rating that exceeds the
DS
sum of the upper voltage tolerance of the input power
source and the voltage spike that occurs when the
MOSFETs switch.
There are several power MOSFETs readily available that
are optimized for DC/DC converter applications. The
preferred high-side MOSFET emphasizes low gate charge
so that the device spends the least amount of time
dissipating power in the linear region. The preferred low-
When placing MOSFETs, try to keep the source of the
upper MOSFETs and the drain of the lower MOSFETs as
close as thermally possible. See Figure 21. Input high
frequency capacitors should be placed close to the drain
of the upper MOSFETs and the source of the lower
MOSFETs. Place the output inductor and output
side MOSFET emphasizes low r
saturated to minimize conduction loss.
when fully
DS(on)
FN6899.0
December 22, 2009
24
ISL95870, ISL95870A, ISL95870B
OCSET AND VO PINS
GND
VIAS TO
GROUND
PLANE
The current-sensing network consisting of R
, R ,
O
OCSET
OUTPUT
CAPACITORS
and C
SEN
needs to be connected to the inductor pads for
accurate measurement of the DCR voltage drop. These
components however, should be located physically close
to the OCSET and VO pins with traces leading back to the
inductor. It is critical that the traces are shielded by the
ground plane layer all the way to the inductor pads. The
procedure is the same for resistive current sense.
SCHOTTKY
DIODE
VOU
PHASE
LOW-SIDE
MOSFETS
INDUCTOR
NODE
HIGH-SIDE
MOSFETS
INPUT
CAPACITORS
VIN
FB, SREF, SET0, SET1, SET2, AND RTN PINS
FIGURE 21. TYPICAL POWER COMPONENT PLACEMENT
The input impedance of these pins is high, making it
critical to place the components connected to these pins
as close as possible to the IC.
capacitors between the MOSFETs and the load. High
frequency output decoupling capacitors (ceramic) should
be placed as close as possible to the decoupling target,
making use of the shortest connection paths to any
internal planes. Place the components in such a way that
the area under the IC has less noise traces with high
dV/dt and di/dt, such as gate signals and phase node
signals.
LGATE, PGND, UGATE, BOOT, AND PHASE PINS
The signals going through these traces are high dv/dt
and high di/dt, with high peak charging and discharging
current. The PGND pin can only flow current from the
gate-source charge of the low-side MOSFETs when
LGATE goes low. Ideally, route the trace from the LGATE
pin in parallel with the trace from the PGND pin, route
the trace from the UGATE pin in parallel with the trace
from the PHASE pin. In order to have more accurate
zero-crossing detection of inductor current, it is
recommended to connect Phase pin to the drain of the
low-side MOSFETs with Kelvin connection. These pairs of
traces should be short, wide, and away from other traces
with high input impedance; weak signal traces should not
be in proximity with these traces on any layer.
VCC AND PVCC PINS
Place the decoupling capacitors as close as practical to
the IC. In particular, the PVCC decoupling capacitor
should have a very short and wide connection to the
PGND pin. The VCC decoupling capacitor should be
referenced to GND pin.
EN, PGOOD, VID0, VID1, AND FSEL PINS
These are logic signals that are referenced to the GND
pin. Treat as a typical logic signal.
FN6899.0
December 22, 2009
25
ISL95870, ISL95870A, ISL95870B
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
December 22, 2009
FN6899.0 Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL95870, ISL95870A, ISL95870B
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6899.0
December 22, 2009
26
ISL95870, ISL95870A, ISL95870B
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
L16.2.6x1.8A
D
A
B
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
6
INDEX AREA
SYMBOL
MIN
0.45
NOMINAL
MAX
0.55
NOTES
N
E
A
A1
A3
b
0.50
-
2X
0.10 C
1 2
-
-
0.05
-
2X
0.10 C
0.127 REF
-
TOP VIEW
0.15
2.55
1.75
0.20
0.25
2.65
1.85
5
D
2.60
-
0.10 C
E
1.80
-
C
A
0.05 C
SEATING PLANE
e
0.40 BSC
-
K
0.15
0.35
0.45
-
0.40
0.50
16
4
-
0.45
0.55
-
A1
L
-
SIDE VIEW
L1
N
-
2
e
Nd
Ne
θ
3
PIN #1 ID
L1
K
1 2
4
3
NX L
0
-
12
4
5
NX b
16X
Rev. 5 2/09
(DATUM B)
(DATUM A)
NOTES:
0.10 M C A B
0.05 M C
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
BOTTOM VIEW
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
C
L
(A1)
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX (b)
5
L
e
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
SECTION "C-C"
TERMINAL TIP
C C
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
3.00
1.80
1.40
0.90
1.40
2.20
0.40
0.20
0.20
0.40
0.50
10
LAND PATTERN
FN6899.0
December 22, 2009
27
ISL95870, ISL95870A, ISL95870B
Package Outline Drawing
L20.3.2x1.8
20 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (UTQFN)
Rev 0, 5/08
6
1.80
A
0.40
16X
PIN #1 ID
B
20
1
6
19
2
PIN 1 ID#
0.50±0.10
(4X)
0.10
9
12
10
11
VIEW “A-A”
TOP VIEW
0.10 M C A B
C
0.05 M
4
20X 0.20
19X 0.40 ± 0.10
BOTTOM VIEW
( 1.0 )
(1 x 0.70)
SEE DETAIL "X"
C
C
0.10
MAX 0.55
BASE PLANE
SEATING PLANE
0.05
C
SIDE VIEW
( 2. 30 )
( 16 X 0 . 40 )
5
C
0 . 2 REF
( 20X 0 . 20 )
( 19X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6899.0
December 22, 2009
28
ISL95870, ISL95870A, ISL95870B
Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 6/07
0.10 M
C
C
A
B
3.00
A
M
0.05
0.50
16X
20X 0.25 +0.05
B
4
-0.07
PIN 1 INDEX AREA
(C 0.40)
17
20
A
16
1
PIN 1
INDEX AREA
4.00
+0.10
2.65
-0.15
11
6
0.15 (4X)
A
10
7
VIEW "A-A"
1.65 +0.10
-0.15
TOP VIEW
20x 0.40±0.10
BOTTOM VIEW
SEE DETAIL "X"
C
C
0.10
0.9± 0.10
SEATING PLANE
0.08
C
SIDE VIEW
(16 x 0.50)
(2.65)
(3.80)
(20 x 0.25)
5
0.2 REF
C
(20 x 0.60)
0.00 MIN.
0.05 MAX.
(1.65)
(2.80)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6899.0
December 22, 2009
29
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