ISL95871C_11_技术文档

SMBus Interfaced Battery Charger with Internal FETs

ISL95871C

Features

The ISL95871C is a highly integrated Lithium-ion battery charger

controller, programmable over the System Management Bus

(SMBus) with internal switching FETs. High efficiency is achieved

with a DC/DC synchronous-rectifier buck converter, equipped with

diode emulation for enhanced light load efficiency and system bus

boosting prevention. The ISL95871C charges one to four

Lithium-ion series cells, and delivers up to 8A charge current.

Integrated MOSFETs and bootstrap diode result in fewer

components and smaller implementation area. Low offset

current-sense amplifiers provide high accuracy with 10mΩ sense

resistors. The ISL95871C provides 0.5% battery voltage accuracy.

• Internal Synchronous Buck Output Stage Power FETs

• 0.5% Battery Voltage Accuracy

• 3% Adapter Current Limit Accuracy

• 3% Charge Current Accuracy

• SMBus 2-Wire Serial Interface

• Battery Short Circuit Protection

• Fast Response for Pulse-Charging

• Fast System-Load Transient Response

• Monitor Outputs

The ISL95871C also provides a digital output that indicates the

presence of the AC-adapter as well as an analog output which

indicates the adapter current within 4% accuracy.

- Adapter Current (3% Accuracy)

- AC-Adapter Detection

• 11-Bit Battery Voltage Setting

Applications

• 6 Bit Charge Current/Adapter Current Setting

• 8A Maximum Battery Charger Current

• 11A Maximum Adapter Current

• +8V to +22V Adapter Voltage Range

• Pb-Free (RoHS Compliant)

• Notebook Computers

• Tablet PCs

• Portable Equipment with Rechargeable Batteries

Related Literature

• See AN1590, ISL95871C Evaluation Board User Guide

9

8

7

100

95

90

1 CELL

6

85

4 CELL

3 CELL

4 CELL

5

2 CELL

80

75

70

65

60

3 CELL

2 CELL

4

3

2

1

0

1 CELL

0

1

2

3

4

5

6

7

8

0

25

50

75

100

125

150

AMBIENT TEMPERATURE (°C)

CHARGE CURRENT (A)

FIGURE 1. EFFICIENCY vs CHARGE CURRENT AND BATTERY

VOLTAGE (EFFICIENCY DCIN = 20V)

FIGURE 2. DERATING CURVE WITH NATURAL AIR FLOW

(MEASURED ON 10cm x 10cm EVALUATION BOARD)

June 8, 2011

FN6856.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ISL95871C

Pin Configuration

ISL95871C

(50 LD 5x7 QFN)

TOP VIEW

42

50 49 48 47 46 45 44 43

AGND

ACIN

NC

1

2

41

40

39

38

37

36

35

34

33

32

31

AGND

ACOK

VFB

3

AGND

51

CSIP

AGND

CSIN

VDD

4

CSON

CSOP

DCIN

NC

5

6

7

BOOT

UGATE

VIN

AGND

VDDP

8

9

VDDP

52

DCIN3

UGATE

49

53

10

PHASE 11

PGND 12

PGND 13

PGND 14

PGND 15

30 VIN

29 VIN

28 VIN

27 VIN

26 VIN

PHASE

54

VIN

55

PHASE7

PGND 16

22

25

17 18 19 20 21

23 24

Pin Descriptions

PIN NUMBER

SYMBOL

DESCRIPTION

1, 8, 37, 51

AGND

Analog Ground. Connect directly to the backside paddle. Connect to PGND and the system ground plane under

the IC.

2

ACOK

AC-Adapter Detection Output. This open drain output is high impedance when ACIN is greater than 3.2V. The

ACOK output remains low when the ISL95871C is powered down. Connect a 10k pull-up resistor from ACOK

to VDDSMB. Range: 0V to 5V.

3

VFB

CSON

CSOP

DCIN

NC

Battery Voltage Remote Sense. Connect to the battery pack positive terminal.

Charge Current-Sense Negative Input. Range: zero to battery voltage.

4

5

6

Charge Current-Sense Positive Input. Range: zero to battery voltage.

Charger Bias Supply Input. Bypass DCIN with a 0.1µF capacitor to AGND. Range: zero to adapter voltage.

No Connection. Pins 7, 21, 39, 45 and 50 are not connected.

7, 21, 39, 45, 50

9, 10, 52

VDDP

Linear Regulator Output. VDDP is the output of the 5.2V linear regulator supplied from DCIN. VDDP also

directly supplies the LFET gate driver and the BOOT strap diode. Bypass with a 1µF ceramic capacitor from

VDDP to PGND. Range: zero to 5.3V.

11, 17, 18, 19, 20, 54

12, 13, 14, 15, 16

PHASE

PGND

Output inductor connection. Connected to the source of the internal high-side N-Channel MOSFET Source and

low-side N-Channel MOSFET Drain. Range: 1 diode drop below ground to 1 diode drop above adapter voltage.

Power Ground. Connect PGND to the source of the low side MOSFET and to the system ground plane.

FN6856.2

June 8, 2011

2

ISL95871C

Pin Descriptions(Continued)

PIN NUMBER

SYMBOL

DESCRIPTION

22, 23, 24, 25, 26, 27,

28, 29, 30, 55

VIN

Power input to the switching FETs connected to the drain of internal upper FET. A very low ESR capacitor should

be place from the VIN pins to the PGND pins. Range: Min battery voltage to adapter voltage.

32, 33, 53

UGATE

BOOT

VDD

Upper Gate of the internal power FET. A 4700pF cap must be placed between UGATE and PHASE. Range: 1

diode drop below ground to 5.3V above adapter voltage.

34

35

High-Side Power MOSFET Driver Power-Supply Connection. Connect a 0.1µF capacitor from BOOT to PHASE.

Range: 1 diode drop below ground to 5.3V above adapter voltage.

Power input for internal analog circuits. Connect a 4.7Ω resistor from VDD to VDDP and a 1µF ceramic

capacitor from VDD to AGND. Range: 0V to 5.3V.

36

38

40

CSIN

CSIP

ACIN

Input Current-Sense Negative Input. Range: battery voltage to adapter voltage.

Input Current-Sense Positive Input. Range: battery voltage to adapter voltage.

AC-Adapter Detection Input. Connect to a resistor divider from the AC-adapter output. Output switching is

disabled when ACIN is below it threshold. The divider should be designed to pull ACIN above its threshold when

the adapter voltage is above battery voltage. Range: 0V to 5V.

42

43

VREF

3.2V internal reference voltage. Place a 0.1µF ceramic capacitor from VREF to AGND pin close to the IC.

ICOMP

Compensation Point for the charging current and adapter current regulation Loop. Connect 0.01µF to AGND.

See the “Charge Current Control Loop” on page 21 for details of selecting the ICOMP capacitor. Range: 0V to

5.3V.

44

VCOMP

Compensation Point for the voltage regulation loop. Connect a resistor in series with a small ceramic capacitor

to AGND, typically 4.7kΩ in series with 0.01µF. See “Voltage Control Loop” on page 22 for details on selecting

VCOMP components. Range: 0V to 5V.

46

47

ICM

SDA

Input Current Monitor Output. ICM voltage equals 20 x (V ). Range: 0V to 5V.

- V

CSIP CSIN

SMBus Data I/O. Open-drain Output. Connect an external pull-up resistor according to SMBus specifications.

Range: 0V to 5V.

48

49

SCL

SMBus Clock Input. Connect an external pull-up resistor according to SMBus specifications. Range: 0V to 5V.

SMBus interface Supply Voltage Input. Bypass with a 0.1µF capacitor to AGND. Range: 0V to 5V.

VDDSMB

51, 52, 53, 54, 55 Back Side Paddles 5 terminals on the back side of the package provide additional electrical and thermal connection to

ISL95871C AGND, VDDP, UGATE, PHASE and VIN. PHASE and VIN paddles are the lowest thermal resistance

from the switching MOSFETs and should relatively large areas of copper to have low thermal resistance from

the FETs to the PCB and the ambient air. The AGND paddle is the lowest thermal resistance from the control

IC and should be connected to a relatively large area of copper to have low thermal resistance from the FETs

to the PCB and the ambient air.

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

TEMP RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

ISL95871CHRZ

NOTES:

1. Add “-T*” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications.

ISL 95871CHRZ

-10 to +100

50 Ld 5x7 QFN

L50.5x7

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate

plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95871C. For more information on MSL please see techbrief TB363.

FN6856.2

June 8, 2011

3

ISL95871C

DCIN

11

DACV

DACI

DACS

EN

VDDSMB

SDA

6

VDDP

VDDP REG

SMBUS

SCL

VDDP

ICM

VREF

REFERENCE

ACOK

+

-

VREF

CSIP

CSIN

-

20X

-

+

GMS

DACS

DACI

+

ACIN

MIN

CURRENT

BUFFER

VDDP

ACOK

EN

-

CSOP

CSON

BOOT

VIN

-

GMI

+

ICOMP

FEED

FORWARD

PULSE

UGATE

PHASE

MIN

VOLTAGE

BUFFER

WIDTH

VDDP

MODULATOR

VCOMP

VFB

500k

100k

-

PGND

GND

GMV

DACV

+

FIGURE 3. FUNCTIONAL BLOCK DIAGRAM

AC-ADAPTER

TO SYSTEM

R

S1

CSIP

CSIN

VIN

R

ACIN

DCIN

S2

AGND

PHASE

IN-RUSH

LIMIT

ISL95871C

BOOT

SMART

BATTERY

CIRCUIT

UGATE

PGND

CSOP

CSON

VFB

AGND

ICOMP

VCOMP

VDDP

PGND

SDA

SCL

VREF

ACOK

ICM

R

VCOMP

SDA

SCL

VDDSMB

VDD

AGND

C

VCOMP

ICOMP

AGND

PGND

FIGURE 4. TYPICAL APPLICATION CIRCUIT

FN6856.2

June 8, 2011

4

ISL95871C

Application Information...................................................................19

Table of Contents

Inductor Selection ...................................................................... 19

Output Capacitor Selection....................................................... 19

Snubber Design .......................................................................... 20

Input Capacitor Selection.......................................................... 20

Loop Compensation Design...................................................... 20

Transconductance Amplifiers GMV, GMI and GMS ............... 20

PWM Gain Fm............................................................................. 20

Charge Current Control Loop .................................................... 21

Adapter Current Limit Control Loop......................................... 21

Voltage Control Loop.................................................................. 22

Output LC Filter Transfer Functions......................................... 22

Compensation Break Frequency Equations ........................... 23

Absolute Maximum Ratings.............................................................. 6

Thermal Information.......................................................................... 6

Recommended Operating Conditions............................................. 6

SMBus Timing Specification............................................................. 8

Typical Operating Performance.........................................................9

Theory of Operation ......................................................................... 12

Introduction ................................................................................. 12

PWM Control................................................................................ 12

AC-Adapter Detection................................................................. 12

Current Measurement................................................................ 12

VDDP Regulator .......................................................................... 12

VDDSMB Supply.......................................................................... 12

Short Circuit Protection and 0V Battery Charging ................. 12

Undervoltage Detect and Battery Trickle Charging ............... 12

Over-Temperature Protection ................................................... 12

Overvoltage Protection .............................................................. 12

The System Management Bus.................................................. 13

General SMBus Architecture..................................................... 13

Data Validity ................................................................................ 13

START and STOP Conditions............................................................. 13

Acknowledge........................................................................................ 13

SMBus Transactions........................................................................... 14

Byte Format................................................................................. 14

ISL95871C and SMBus.............................................................. 14

Battery Charger Registers ......................................................... 14

Enabling and Disabling Charging ............................................. 14

Setting Charge Voltage .............................................................. 15

Setting Charge Current .............................................................. 17

Setting Input-Current Limit........................................................ 18

Charger Timeout ......................................................................... 19

ISL95871C Data Byte Order ..................................................... 19

Writing to the Internal Registers.............................................. 19

Reading from the Internal Registers ....................................... 19

PCB Layout Considerations.............................................................23

Power and Signal Layers Placement on the PCB........................ 23

Component Placement.............................................................. 23

Signal Ground and Power Ground Connection....................... 23

AGND and VDD Pin..................................................................... 24

PGND Pins ................................................................................... 24

PHASE Pins.................................................................................. 24

BOOT Pin...................................................................................... 24

CSOP, CSON, CSIP and CSIN Pins............................................ 24

DCIN Pin....................................................................................... 24

Copper Size for the Phase Node .............................................. 24

Identify the Power and Signal Ground .................................... 24

Clamping Capacitor for Switching MOSFET............................ 24

Revision History ................................................................................25

Products.............................................................................................25

Package Outline Drawing ...............................................................26

FN6856.2

June 8, 2011

5

ISL95871C

Absolute Maximum Ratings

Thermal Information

DCIN, CSIP, CSIN, CSOP, CSON, VIN to PGND . . . . . . . . . . . . . . . -0.3V to +28V

DCIN, CSIP, CSIN, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V

CSOP, CSON, VFB to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +28V

CSIP-CSIN, CSOP-CSON, PGND-AGND . . . . . . . . . . . . . . . . . . -0.3V to +0.3V

PHASE-PGND and VIN-PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +28V

UGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHASE - 0.3V to BOOT + 0.3V

BOOT to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V

BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V

ICOMP, VCOMP, VREF, to AGND. . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V

VDDSMB, SCL, SDA, ACIN, ACOK to AGND . . . . . . . . . . . . . . . . -0.3V to +6V

VDD to AGND, VDDP to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V

Thermal Resistance (Typical)

50 Ld 5x7 QFN Package (Notes 4, 5) . . . . . .

Operating Junction Temperature Range . . . . . . . . . . . . . .-10°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

θ

_JA(°C/W)

32

θ

_JC(°C/W)

2

Recommended Operating Conditions

Ambient Temperature (see Figure 11). . . . . . . . . . . . . . . .-10°C to +100°C

Supply Voltage DCIN and VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 22V

VDDSMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θ_JAis measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications VIN = DCIN = V

= V

CSIN

= 19V, V

CSOP

= V

CSON

= 12V, VDDP = 5.1V, V

- V = 5V,

BOOT PHASE

CSIP

AGND = PGND = 0V, VDDSMB = 5V. All typical specifications T = +25°C. Boldface limits apply over the junction temperature range, -10°C to

A

+125°C.

MIN

MAX

PARAMETER

CHARGE VOLTAGE REGULATION

Battery Full Charge Voltage and Accuracy

CONDITIONS

(Note 6)

TYP

(Note 6) UNITS

ChargeVoltage = 0x41A0

16.716

-0.5

16.8

16.884

0.5

V

%

V

ChargeVoltage = 0x3130

ChargeVoltage = 0x20D0

ChargeVoltage = 0x1060

VFB rising

12.529 12.592 12.655

-0.5

8.358

-0.5

0.5

8.442

0.5

%

V

8.4

%

V

4.163

-0.7

4.192

4.221

0.7

%

V

Battery Trickle Charge Threshold

2.55

100

2.7

2.85

400

Battery Trickle Charge Threshold Hysteresis

CHARGE CURRENT REGULATION

CSOP to CSON Full-Scale Current-Sense Voltage

Charge Current and Accuracy

200

mV

78.22

7.822

-3

80.64

8.064

83.06

8.306

3

mV

A

RS2 = 10mΩ (see Figure 4)

ChargeCurrent = 0x1F80

CSON from 0V to 19.2V

%

RS2 = 10mΩ (see Figure 4)

ChargeCurrent = 0x0F80

CSON from 0V to 19.2V

3.849

-3

3.968

128

4.087

3

A

%

RS2 = 10mΩ (see Figure 4)

ChargeCurrent = 0x0080

CSON from 0V to 19.2V

64

220

mA

%

Charge Current Gain Error

Based on charge current = 128mA and 8.064A

-1.6

1.4

FN6856.2

June 8, 2011

6

ISL95871C

Electrical Specifications VIN = DCIN = V

= V

CSIN

= 19V, V

CSOP

= V

CSON

= 12V, VDDP = 5.1V, V

- V = 5V,

BOOT PHASE

CSIP

AGND = PGND = 0V, VDDSMB = 5V. All typical specifications T = +25°C. Boldface limits apply over the junction temperature range, -10°C to

A

+125°C. (Continued)

MIN

MAX

PARAMETER

Battery Quiescent Current

CONDITIONS

Adapter present, not charging,

(Note 6)

TYP

0.1

(Note 6) UNITS

2

µA

I

V

+ I + I + I

CSOP CSON PHASE FB

= V = V = V

DCIN

= 19V, V = 5V

ACIN

PHASE

CSON CSOP

Adapter Absent

+ I + I

0.1

2

µA

I

+ I

CSOP CSON PHASE CSIP CSIN FB

= V = V = 19V, V = 0V

V

PHASE

+ I

CSON

CSOP

DCIN

Adapter Quiescent Current

I

+ I

2.5

0.3

5

mA

µA

DCIN CSIP CSIN

V

= 8V to 22V

adapter

VIN Leakage Current

PHASE = 0V, VIN = 22V

1.5

INPUT CURRENT REGULATION

CSIP to CSIN Full-Scale Current-Sense Voltage

Input Current Accuracy

V

= 19V

106.7 110.08 113.3

mV

%

CSIP

RS1 = 10mΩ (see Figure 4)

-3

3

Adapter Current = 11008mA or 3584mA

RS1 = 10mΩ (see Figure 4)

-5

5

%

Adapter Current = 2048mA

Input Current Limit Gain Error

Input Current Limit Offset

ICM Gain

Based on InputCurrent = 1024mA and 11008mA

-2

-1

2

1

%

mV

V/V

%

V

= 110mV

= 55mV or 35mV

= 20mV

19.9

CSIP- CSIN

ICM Accuracy

V

-2.5

-4

2.5

4

CSIP- CSIN

V

%

CSIP- CSIN

V

-8

8

%

CSIP- CSIN

ICM Load regulation

V

= 0.1V,

10

mV

CSIP- CSIN

ICM load from zero to 500µA

SUPPLY AND LINEAR REGULATOR

VDDP Output Voltage

VDDP Load Regulation

VDDSMB UVLO Rising

VDDSMB UVLO Falling

VDDSMB UVLO Hysteresis

VDD UVLO Rising

8.0V < V

< 22V, no load

4.95

5.1

35

5.23

100

2.61

2.5

V

mV

V

DCIN

0 < I

< 30mA

VDDP

2.3

2.2

2.5

2.4

100

4.5

280

20

V

mV

V

4.25

150

4.65

400

27

VDD UVLO Hysteresis

VDDSMB Quiescent Current

VOLTAGE REFERENCE

VREF Output Voltage

ACOK

mV

µA

VDDP = SCL = SDA = 5.5V

0 < I

VREF

< 300µA

3.168

2

3.2

8

3.232

V

ACOK Sink Current

V

= 0.4V, ACIN = 1.5V

= 5.5V, ACIN = 2.5V

mA

µA

ACOK

ACOK Leakage Current

ACIN

V

1

ACOK

ACIN Rising Threshold

ACIN Threshold Hysteresis

ACIN Input Leakage Current

3.15

40

3.2

60

3.28

90

1

V

mV

µA

ACIN = 3.7V

FN6856.2

June 8, 2011

7

ISL95871C

Electrical Specifications VIN = DCIN = V

= V

CSIN

= 19V, V

CSOP

= V

CSON

= 12V, VDDP = 5.1V, V

- V = 5V,

BOOT PHASE

CSIP

AGND = PGND = 0V, VDDSMB = 5V. All typical specifications T = +25°C. Boldface limits apply over the junction temperature range, -10°C to

A

+125°C. (Continued)

MIN

MAX

PARAMETER

SWITCHING REGULATOR

CONDITIONS

(Note 6)

TYP

(Note 6) UNITS

Frequency

330

400

50

440

kHz

ns

Dead Time

ERROR AMPLIFIERS

GMV Amplifier Transconductance

GMI Amplifier Transconductance

GMS Amplifier Transconductance

GMI/GMS Saturation Current

GMV Saturation Current

ICOMP, VCOMP Clamp Voltage

LOGIC LEVELS

200

40

250

50

300

60

µA/V

µA

40

50

60

15

20

25

10

17

30

µA

0.25V < V

V

< 3.5V

200

300

400

mV

ICOMP, VCOMP

SDA/SCL Input Low Voltage

SDA/SCL Input High Voltage

SDA/SCL Input Bias Current

SDA, Output Sink Current

NOTE:

VDDSMB = 2.7V to 5.5V

0.8

1

V

2

7

µA

mA

V

= 0.4V

15

SDA

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

SMBus Timing Specification VDDSMB = 2.7V to 5.5V

PARAMETERS

SYMBOL

CONDITIONS

MIN

10

TYP

MAX

100

UNITS

kHz

µs

SMBus Frequency

Bus Free Time

FSMB

t

4.7

4

BUF

Start Condition Hold Time from SCL

Start Condition Setup Time from SCL

Stop Condition Setup Time from SCL

SDA Hold Time from SCL

SDA Setup Time from SCL

SCL Low Timeout (Note 7)

SCL Low Period

THD:STA

TSU:STA

TSU:STO

THD:DAT

TSU:DAT

µs

4.7

4

µs

300

250

22

4.7

4

ns

t

25

30

ms

µs

TIMEOUT

t

LOW

SCL High Period

t

µs

HIGH

Maximum Charging Period Without a SMBus Write to

ChargeVoltage or ChargeCurrent Register

140

175

220

s

NOTES:

7. If SCL is low for longer than the specified time, the charger is disabled.

8. Limits established by characterization and are not production tested.

FN6856.2

June 8, 2011

8

ISL95871C

Typical Operating Performance DCIN = 19V, 3S2P Li-Battery, T = +25°C, unless otherwise noted.

A

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

5.15

5.10

5.05

5.00

4.95

4.90

13.0

12.5

12.0

11.5

11.0

10.5

10.0

BATTERY VOLTAGE (V)

CHARGE CURRENT

0

20

40

60

80

100

120

140

160

0

10

20

30

40

50

60

70

80

90 100

VDDP LOAD CURRENT (mA)

TIME (MINUTES)

FIGURE 5. VDDP LOAD REGULATION

FIGURE 6. TYPICAL CHARGING VOLTAGE AND CURRENT

100

95

15

10

5

90

85

4 CELL

3 CELL

2 CELL

80

75

70

65

60

0

-5

1 CELL

-10

-15

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

CHARGE CURRENT (A)

ADAPTER CURRENT (A)

FIGURE 8. EFFICIENCY vs CHARGE CURRENT AND BATTERY

VOLTAGE (EFFICIENCY DCIN = 20V)

FIGURE 7. ICM ACCURACY vs AC-ADAPTER CURRENT

4

3

0.5

0.4

0.3

0.2

0.1

CHARGE CURRENT = 2.048A

2

1

CHARGE CURRENT = 4.096A

0

2 CELL

0

1 CELL

-0.1

-0.2

-0.3

-0.4

-0.5

CHARGE CURRENT = 8.064A

-1

4 CELL

3 CELL

CHARGE CURRENT = 6.016A

-2

-3

-4

0

1

2

3

4

5

6

7

8

2

4

6

8

10

12

14

16

18

CHARGE CURRENT (A)

BATTERY VOLTAGE (V)

FIGURE 10. CHARGE VOLTAGE ACCURACY

FIGURE 9. CHARGE CURRENT ACCURACY

FN6856.2

June 8, 2011

9

ISL95871C

Typical Operating Performance DCIN = 19V, 3S2P Li-Battery, T = +25°C, unless otherwise noted. (Continued)

A

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

1 CELL

4 CELL

3 CELL

2 CELL

3 CELL

1 CELL

2 CELL

75

0

25

50

100

125

150

0

25

50

75

100

125

150

AMBIENT TEMPERATURE (°C)

FIGURE 11. DERATING CURVE WITH NATURAL AIR FLOW

FIGURE 12. DERATING CURVE WITH 200LFM AIR FLOW

(MEASURED ON 10cm x 10cm EVALUATION BOARD)

PHASE

UGATE-PHASE

INDUCTOR CURRENT

FIGURE 13. SWITCHING WAVEFORMS IN DIODE EMULATION MODE

FIGURE 14. SWITCHING WAVEFORMS IN CC MODE

VCOMP

ICOMP

VCOMP

ICOMP

SDA

CHARGE CURRENT

FIGURE 15. CHARGE ENABLE: WRITE 1F80 (8.064A) TO

CHARGECURRENT REGISTER

FIGURE 16. CHARGE DISABLE: WRITE 0000 (0A) TO

CHARGECURRENT REGISTER

FN6856.2

June 8, 2011

10

ISL95871C

Typical Operating Performance DCIN = 19V, 3S2P Li-Battery, T = +25°C, unless otherwise noted. (Continued)

A

VCOMP

ICOMP

VCOMP

CSON

CHARGE CURRENT

FIGURE 18. BATTERY INSERTION

FIGURE 17. BATTERY REMOVAL

ADAPTER CURRENT

SYSTEM CURRENT

CHARGE CURRENT

CSON VOLTAGE

FIGURE 19. SYSTEM LOAD TRANSIENT RESPONSE

FN6856.2

June 8, 2011

11

ISL95871C

AC-Adapter Detection

Theory of Operation

Connect the AC-adapter voltage through a resistor divider to ACIN

to detect when AC power is available, as shown in Figure 4. ACOK

is an open-drain output and is active low when ACIN is less than

ACIN falling threshold, and high when ACIN is above ACIN rising

threshold. The ACIN rising threshold is 3.2V (typ) with 57mV

hysteresis.

Introduction

The ISL95871C includes all of the functions necessary to charge

1- to 4-cell Li-ion and Li-polymer batteries. A high efficiency

synchronous buck converter is used to control the charging

voltage up to 19.2V and charging current up to 8A. The

ISL95871C also has input current limiting up to 11A. The Input

current limit, charge current limit and charge voltage limit are set

by internal registers written with SMBus. The ISL95871C “Typical

Application Circuit” is shown in Figure 4.

Current Measurement

Use ICM to monitor the adapter current being sensed across CSIP

and CSIN. The output voltage range is 0V to 2.5V. The voltage of

ICM is proportional to the voltage drop across CSIP and CSIN, and

is given by Equation 1:

The ISL95871C charges the battery with constant charge current,

set by the ChargeCurrent register, until the battery voltage rises to

a voltage set by the ChargeVoltage register. The charger will then

operate at a constant voltage. The adapter current is monitored

and if the adapter current rises to the limit set by the InputCurrent

register, battery charge current is reduced so the charger does not

reduce the adapter current available to the system.

V

= 20 ⋅ I

⋅ R = 20 × (V

– V

)

CSIN

(EQ. 1)

ICM

INPUT

S1

CSIP

where I

is the DC current drawn from the AC-adapter. It is

INPUT

recommended to have an RC filter at the ICM output for

minimizing the switching noise.

The ISL95871C features a voltage regulation loop (VCOMP) and 2

current regulation loops (ICOMP). The VCOMP voltage regulation

loop monitors VFB to limit the battery charge voltage. The ICOMP

current regulation loop limits the battery charging current

delivered to the battery to ensure that it never exceeds the

current set by the ChargeCurrent register. The ICOMP current

regulation loop also limits the input current drawn from the

AC-adapter to ensure that it never exceeds the limit set by the

InputCurrent register, and to prevent a system crash and

AC-adapter overload.

VDDP Regulator

VDDP provides a 5.2V supply voltage from the internal LDO

regulator from DCIN and can deliver up to 30mA of continuous

current. The MOSFET drivers are powered by VDDP. VDDP also

supplies power to VDD through a low pass filter as shown in

Figure 4 on page 4. Bypass VDDP and VDD with a 1µF capacitor.

VDDSMB Supply

The VDDSMB input provides power to the SMBus interface. Connect

VDDSMB to VDD, or apply an external supply to VDDSMB to keep the

SMBus interface active while the supply to DCIN is removed. When

VDDSMB is biased, the internal registers are maintained. Bypass

VDDSMB to AGND with a 0.1µF or greater ceramic capacitor.

PWM Control

The ISL95871C employs a fixed frequency PWM control

architecture with a feed-forward function. The feed-forward

function maintains a constant modulator gain of 11 to achieve fast

line regulation as the input voltage changes.

Short Circuit Protection and 0V Battery

Charging

Since the battery charger will regulate the charge current to the

limit set by the ChargeCurrent register, it automatically has short

circuit protection and is able to provide the charge current to

wake up an extremely discharged battery. Undervoltage trickle

charge folds back current if there is a short circuit on the output.

The duty cycle of the buck regulator is controlled by the lower of the

voltages on ICOMP and VCOMP. The voltage on ICOMP and VCOMP

are inputs to a Lower Voltage Buffer (LVB) whose output is the lower

of the 2 inputs. The output of the LVB is compared to an internal

400kHz ramp to produce the Pulse Width Modulated signal that

controls the UFET and LFET gate drivers. An internal clamp holds the

higher of the 2 voltages (0.3V) above the lower voltage. This speeds

the transition from voltage loop control to current loop control or vice

versa.

Undervoltage Detect and Battery Trickle

Charging

The ISL95871C can operate up to 99.6% duty cycle if the input

voltage drops close to or below the battery charge voltage (drop

out mode). The DC/DC converter has a timer to prevent the

frequency from dropping into the audible frequency range.

If the voltage at VFB falls below 2.5V, ISL95871C reduces the

charge current limit to 128mA to trickle charge the battery.

When the voltage rises above 2.7V, the charge current reverts to

the programmed value in the ChargeCurrent register.

To prevent boosting of the system bus voltage, the battery

charger drives the lower FET in a way that prevents negative

inductor current.

Over-Temperature Protection

If the die temperature exceeds +150°C, it stops charging. Once

the die temperature drops below +125°C, charging will start-up

again.

An adaptive gate drive scheme is used to control the dead time

between two switches. The dead time control circuit monitors the

LFET gate driver output and prevents the upper side MOSFET

from turning on until 20ns after the LFET gate driver falls below

Overvoltage Protection

ISL95871C has an Overvoltage Protection circuit that limits the

output voltage when the battery is removed or disconnected by a

pulse charging circuit. If CSON exceeds the output voltage set

1V V , preventing cross-conduction and shoot-through. The

GS

same occurs for LFET turn on.

FN6856.2

June 8, 2011

12

ISL95871C

point in the charge voltage register by more than 300mV, an

internal comparator pulls VCOMP down and turns off both upper

and lower FETs of the buck as in Figure 20. There is a delay of

Data Validity

The data on the SDA line must be stable during the HIGH period

of the SCL, unless generating a START or STOP condition. The

HIGH or LOW state of the data line can only change when the

clock signal on the SCL line is LOW. Refer to Figure 22.

approximately 1µs between V

exceeding the OVP trip point

OUT

and pulling VCOMP, LGATE and UGATE low. After UGATE and

LGATE are turned OFF, inductor current continues to flow through

the body diode of the lower FET and V

inductor current reaches zero.

continues to rise until

OUT

SDA

SCL

V

OUT

INDUCTOR CURRENT

DATA LINE CHANGE

STABLE

OF DATA

DATA VALID ALLOWED

FIGURE 22. DATA VALIDITY

START and STOP Conditions

As shown in Figure 23, START condition is a HIGH-to-LOW transition

of the SDA line while SCL is HIGH.

PHASE

The STOP condition is a LOW-to-HIGH transition on the SDA line

while SCL is HIGH. A STOP condition must be sent before each

START condition.

BATTERY CURRENT

SDA

SCL

FIGURE 20. OVERVOLTAGE PROTECTION IN ISL88731C

The System Management Bus

S

P

START

CONDITION

STOP

CONDITION

The System Management Bus (SMBus) is a 2-wire bus that

supports bidirectional communications. The protocol is described

briefly here. More detail is available from www.smbus.org.

FIGURE 23. START AND STOP WAVEFORMS

General SMBus Architecture

Acknowledge

Each address and data transmission uses 9-clock pulses. The ninth

pulse is the acknowledge bit (ACK). After the start condition, the

master sends 7-slave address bits and a R/W bit during the next 8-

clock pulses. During the ninth clock pulse, the device that recognizes

its own address holds the data line low to acknowledge. The

acknowledge bit is also used by both the master and the slave to

acknowledge receipt of register addresses and data (see Figure 24).

VDDSMB

SMBUS SLAVE

INPUT

STATE

SCL

MACHINE,

REGISTERS,

MEMORY,

ETC

OUTPUT

INPUT

CONTROL

SMBUS MASTER

INPUT

SDA

SCL

OUTPUT

INPUT

OUTPUT CONTROL

CONTROL

CPU

SCL

SDA

CONTROL OUTPUT

SMBUS SLAVE

2

8

1

9

INPUT

STATE

MACHINE,

REGISTERS,

MEMORY,

ETC

SCL

SDA

OUTPUT

INPUT

CONTROL

MSB

SDA

OUTPUT

CONTROL

START

ACKNOWLEDGE

FROM SLAVE

2

FIGURE 24. ACKNOWLEDGE ON THE I C BUS

TO OTHER

SLAVE DEVICES

FIGURE 21.

FN6856.2

June 8, 2011

13

ISL95871C

Read address = 0b00010011 (0X13) and

SMBus Transactions

All transactions start with a control byte sent from the SMBus

master device. The control byte begins with a Start condition,

followed by 7-bits of slave address (0001001 for the ISL95871C)

followed by the R/W bit. The R/W bit is 0 for a write or 1 for a read. If

any slave devices on the SMBus bus recognize their address, they

will Acknowledge by pulling the serial data (SDA) line low for the last

clock cycle in the control byte. If no slaves exist at that address or

are not ready to communicate, the data line will be 1, indicating a

Not Acknowledge condition.

Write address = 0b00010010 (0X12).

In addition, the ISL95871C has two identification (ID) registers: a

16-bit device ID register and a 16-bit manufacturer ID register.

The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs

that can accommodate slow edges. Choose pull-up resistors for

SDA and SCL to achieve rise times according to the SMBus

specifications. The ISL95871C is controlled by the data written to

the registers described in Table 1.

Once the control byte is sent, and the ISL95871C acknowledges

it, the 2nd byte sent by the master must be a register address

byte such as 0x14 for the ChargeCurrent register. The register

address byte tells the ISL95871C which register the master will

write or read. See Table 1 for details of the registers. Once the

ISL95871C receives a register address byte it responds with an

acknowledge.

Battery Charger Registers

The ISL95871C supports five battery-charger registers that use

either Write-Word or Read-Word protocols, as summarized in

Table 1. ManufacturerID and DeviceID are “read only” registers

and can be used to identify the ISL95871C. On the ISL95871C,

ManufacturerID always returns 0x0049 (ASCII code for “I” for

Intersil) and DeviceID always returns 0x0001.

Byte Format

Enabling and Disabling Charging

Every byte put on the SDA line must be eight bits long and must

be followed by an acknowledge bit. Data is transferred with the

most significant bit first (MSB) and the least significant bit last

(LSB).

After applying power to ISL95871C, the internal registers contain

their POR values (see Table 1). The POR values for charge current

and charge voltage are 0x0000. These values disable charging.

To enable charging, the ChargeCurrent register must be written

with a number >0x007F and the ChargeVoltage register must be

written with a number >0x000F. Charging can be disabled by

writing 0x0000 to either of these registers.

ISL95871C and SMBus

The ISL95871C receives control inputs from the SMBus interface.

The serial interface complies with the SMBus protocols as

documented in the System Management Bus Specification V1.1,

which can be downloaded from www.smbus.org. The ISL95871C

uses the SMBus Read-Word and Write-Word protocols (see Figure

25) to communicate with the smart battery. The ISL95871C is an

SMBus slave device and does not initiate communication on the

bus. It responds to the addresses in the following.

TABLE 1. BATTERY CHARGER REGISTER SUMMARY

REGISTER

ADDRESS

REGISTER NAME

ChargeCurrent

READ/WRITE

Read or Write

DESCRIPTION

6-bit Charge Current Setting

POR STATE

0x0000

0x0080

0x0049

0x0001

0x14

0x15

0x3F

0xFE

0xFF

ChargeVoltage

InputCurrent

ManufacturerID

DeviceID

Read or Write

Read Only

11-bit Charge Voltage Setting

6-bit Charge Current Setting

Manufacturer ID

Read Only

Device ID

FN6856.2

June 8, 2011

14

ISL95871C

Write To A Register

SLAVE

ADDR + W

REGISTER

ADDR

LO BYTE

DATA

HI BYTE

DATA

S

A

P

Read From A Register

SLAVE

ADDR + W

REGISTER

ADDR

SLAVE

LO BYTE

DATA

HI BYTE

DATA

A

P

S

A

N

P

ADDR + R

S

P

START

STOP

A

N

ACKNOWLEDGE

DRIVEN BY THE MASTER

DRIVEN BY ISL95871C

NO ACKNOWLEDGE

FIGURE 25. SMBus/ISL95871C READ AND WRITE PROTOCOL

Setting Charge Voltage

Charge voltage is set by writing a valid 16-bit number to the

ChargeVoltage register. This 16-bit number translates to a

65.535V full-scale voltage. The ISL95871C ignores the first 4

LSBs and uses the next 11 bits to set the voltage DAC. The

charge voltage range of the ISL95871C is 1.024V to 19.200V.

Numbers requesting charge voltage greater than 19.200V result

in a ChargeVoltage of 19.200V. All numbers requesting charge

voltage below 1.024V result in a voltage set point of zero, which

terminates charging. Upon initial power-up or reset, the

ChargeVoltage and ChargeCurrent registers are reset to 0 and

the charger remains shut down until valid numbers are sent to

the ChargeVoltage and ChargeCurrent registers. Use the

Write-Word protocol (see Figure 25) to write to the ChargeVoltage

register. The register address for ChargeVoltage is 0x15. The

16-bit binary number formed by D15–D0 represents the charge

voltage set point in mV. However, the resolution of the

ISL95871C is 16mV because the D0–D3 bits are ignored as

shown in Table 2. The D15 bit is also ignored because it is not

needed to span the 1.024V to 19.2V range. Table 2 shows the

mapping between the charge-voltage set point and the 16-bit

number written to the ChargeVoltage register. The ChargeVoltage

register can be read back to verify its contents.

FN6856.2

June 8, 2011

15

ISL95871C

TABLE 2. CHARGEVOLTAGE (REGISTER 0x15)

BIT

0

BIT NAME

DESCRIPTION

Not used.

1

2

3

4

Charge Voltage, DACV 0

Charge Voltage, DACV 1

Charge Voltage, DACV 2

Charge Voltage, DACV 3

Charge Voltage, DACV 4

Charge Voltage, DACV 5

Charge Voltage, DACV 6

Charge Voltage, DACV 7

Charge Voltage, DACV 8

Charge Voltage, DACV 9

Charge Voltage, DACV 10

0 = Adds 0mV of charger voltage, 1024mV min.

1 = Adds 16mV of charger voltage.

5

6

0 = Adds 0mV of charger voltage, 1024mV min.

1 = Adds 32mV of charger voltage.

0 = Adds 0mV of charger voltage, 1024mV min.

1 = Adds 64mV of charger voltage.

7

0 = Adds 0mV of charger voltage, 1024mV min.

1 = Adds 128mV of charger voltage.

8

0 = Adds 0mV of charger voltage, 1024mV min.

1 = Adds 256mV of charger voltage.

9

0 = Adds 0mV of charger voltage, 1024mV min.

1 = Adds 512mV of charger voltage.

10

11

12

13

14

15

0 = Adds 0mA of charger voltage.

1 = Adds 1024mV of charger voltage.

0 = Adds 0mV of charger voltage.

1 = Adds 2048mV of charger voltage.

0 = Adds 0mV of charger voltage.

1 = Adds 4096mV of charger voltage.

0 = Adds 0mV of charger voltage.

1 = Adds 8192mV of charger voltage.

0 = Adds 0mV of charger voltage.

1 = Adds 16384mV of charger voltage, 19200mV max.

Not used. Normally a 32768mV weight.

FN6856.2

June 8, 2011

16

ISL95871C

ChargeCurrent registers are reset to 0 and the charger is

Setting Charge Current

disabled. To start the charger, write valid numbers to the

ChargeVoltage and ChargeCurrent registers. The ChargeCurrent

register uses the Write-Word protocol (see Figure 25). The

register code for ChargeCurrent is 0x14 (0b00010100). Table 3

shows the mapping between the charge current set point and the

ChargeCurrent number. The ChargeCurrent register can be read

back to verify its contents.

ISL95871C has a 16-bit ChargeCurrent register that sets the

battery charging current. ISL95871C controls the charge current

by controlling the CSOP-CSON voltage. The register’s LSB

translates to 10µV at CSON-CSOP. With a 10mΩ charge current

sensing resistor (R in Figure 4 on page 4), the LSB translates to

S2

1mA charge current. The ISL95871C ignores the first 7 LSBs and

uses the next 6 bits to control the current DAC. The

charge-current range of the ISL95871C is 0A to 8.064A (using a

10mΩ current-sense resistor). All numbers requesting charge

current above 8.064A result in a current setting of 8.064A. All

numbers requesting charge current between 0mA to 128mA

result in a current setting of 0mA. The default charge current

setting at Power-On Reset (POR) is 0mA. To stop charging, set

ChargeCurrent to 0. Upon initial power-up, the ChargeVoltage and

The ISL95871C includes a fault limiter for low battery conditions.

If the battery voltage is less than 2.5V, the charge current is

temporarily set to 128mA. The ChargeCurrent register is

preserved and becomes active again when the battery voltage is

higher than 2.7V. This function effectively provides a foldback

current limit, which protects the charger during short circuit and

overload.

TABLE 3. CHARGECURRENT (REGISTER 0x14) (10mΩ SENSE RESISTOR, RS2)

BIT

0

BIT NAME

DESCRIPTION

Not used.

1

2

3

4

5

6

7

Charge Current, DACI 0

Charge Current, DACI 1

Charge Current, DACI 2

Charge Current, DACI 3

Charge Current, DACI 4

Charge Current, DACI 5

0 = Adds 0mA of charger current.

1 = Adds 128mA of charger current.

8

0 = Adds 0mA of charger current.

1 = Adds 256mA of charger current.

9

0 = Adds 0mA of charger current.

1 = Adds 512mA of charger current.

10

11

12

0 = Adds 0mA of charger current.

1 = Adds 1024mA of charger current.

0 = Adds 0mA of charger current.

1 = Adds 2048mA of charger current.

0 = Adds 0mA of charger current.

1 = Adds 4096mA of charger current, 8064mA max.

13

14

15

Not used.

FN6856.2

June 8, 2011

17

ISL95871C

limit use the SMBus to write a 16-bit InputCurrent register using

Setting Input-Current Limit

the data format listed in Table 4. The InputCurrent register uses

the Write-Word protocol (see Figure 25). The register code for

InputCurrent is 0x3F (0b00111111). The InputCurrent register

can be read back to verify its contents.

The total power from an AC-adapter is the sum of the power

supplied to the system and the power into the charger and battery.

When the input current exceeds the set input current limit, the

ISL95871C decreases the charge current to provide priority to

system load current. As the system load rises, the available charge

current drops linearly to zero. Thereafter, the total input current

can increase to the limit of the AC-adapter.

The ISL95871C ignores the first 7 LSBs and uses the next 6 bits to

control the input-current DAC. The input-current range of the

ISL95871C is from 256mA to 11.004A. All 16-bit numbers

requesting input current above 11.004A result in an input-current

setting of 11.004A. All 16-bit numbers requesting input current

between 0mA to 256mA result in an input-current setting of 0mA.

The default input-current-limit setting at POR is 256mA. When

choosing the current-sense resistor RS1, carefully calculate its

power rating. Take into account variations in the system’s load

current and the overall accuracy of the sense amplifier. Note that

the voltage drop across RS1 contributes additional power loss,

which reduces efficiency. System currents normally fluctuate as

portions of the system are powered up or put to sleep. Without

input current regulation, the input source must be able to deliver

the maximum system current and the maximum charger-input

current. By using the input-current-limit circuit, the output-current

capability of the AC wall adapter can be lowered, reducing system

cost.

The internal amplifier compares the differential voltage between

CSIP and CSIN to a scaled voltage set by the InputCurrent

register. The total input current is the sum of the device supply

current, the charger input current, and the system load current.

The total input current can be estimated as shown in Equation 2.

I

= I

+ [(I

× V

) ⁄ (V × η)]

BATTERY IN

INPUT

SYSTEM

CHARGE

(EQ. 2)

Where η is the efficiency of the DC/DC converter (typically 85%

to 95%).

The ISL95871C has a 16-bit InputCurrent register that translates

to a 2mA LSB and a 131.071A full scale current using a 10mΩ

current-sense resistor (RS1 in Figure 4 on page 4). Equivalently,

the 16-bit InputCurrent number sets the voltage across CSIP and

CSIN inputs in 20µV per LSB increments. To set the input current

TABLE 4. INPUTCURRENT (REGISTER 0x3F) (10mΩ SENSE RESISTOR, RS1)

BIT NAME DESCRIPTION

BIT

0

Not used.

1

2

3

4

5

6

7

Input Current, DACS 0

0 = Adds 0mA of input current.

1 = Adds 256mA of input current.

8

Input Current, DACS 1

Input Current, DACS 2

Input Current, DACS 3

Input Current, DACS 4

Input Current, DACS 5

0 = Adds 0mA of input current.

1 = Adds 512mA of input current.

9

0 = Adds 0mA of input current.

1 = Adds 1024mA of input current.

10

11

12

0 = Adds 0mA of input current.

1 = Adds 2048mA of input current.

0 = Adds 0mA of input current.

1 = Adds 4096mA of input current.

0 = Adds 0mA of input current.

1 = Adds 8192mA of input current, 11004mA max.

13

14

15

Not used.

FN6856.2

June 8, 2011

18

ISL95871C

The ISL95871C does not support reading more than 1 register

per transaction.

Charger Timeout

The ISL95871C includes 2 timers to insure the SMBus master is

active and to prevent overcharging the battery. ISL95871C will

terminate charging if the charger has not received a write to the

ChargeVoltage or ChargeCurrent register within 175s or if the

SCL line is low for more than 25ms. If a time-out occurs, either

ChargeVoltage or ChargeCurrent registers must be written to

re-enable charging.

Application Information

The following battery charger design refers to the “Typical

Application Circuit” (see Figure 4 on page 4), where typical

battery configuration of 3S2P is used. This section describes how

to select the external components including the inductor, input

and output capacitors, switching MOSFETs and current sensing

resistors.

ISL95871C Data Byte Order

Each register in ISL95871C contains 16-bits or 2-, 8-bit bytes. All

data sent on the SMBus is in 8 bit bytes and 2 bytes must be

written or read from each register in ISL95871C. The order in

which these bytes are transmitted appears reversed from the

way they are normally written. The LOW byte is sent first and the

HI byte is sent second. For example, When writing 0x41A0, 0xA0

is written first and 0x41 is sent second.

Inductor Selection

The inductor selection has trade-offs between cost, size,

crossover frequency and efficiency. For example, the lower the

inductance, the smaller the size, but ripple current is higher. This

also results in higher AC losses in the magnetic core and the

windings, which decreases the system efficiency. On the other

hand, the higher inductance results in lower ripple current and

smaller output filter capacitors, but it has higher DCR (DC

resistance of the inductor) loss, lower saturation current and has

slower transient response. Thus, the practical inductor design is

based on the inductor ripple current being ±15% to ±20% of the

maximum operating DC current at maximum input voltage.

Writing to the Internal Registers

In order to set the charge current, charge voltage or input current,

valid 16-bit numbers must be written to ISL95871C’s internal

registers via the SMBus.

To write to a register in the ISL95871C, the master sends a

control byte with the R/W bit set to 0, indicating a write. If it

receives an Acknowledge from the ISL95871C it sends a register

address byte setting the register to be written (i.e., 0x14 for the

ChargeCurrent register). The ISL95871C will respond with an

Acknowledge. The master then sends the lower data byte to be

written into the desired register. The ISL95871C will respond with

an Acknowledge. The master then sends the higher data byte to

be written into the desired register. The ISL95871C will respond

with an Acknowledge. The master then issues a Stop condition,

indicating to the ISL95871C that the current transaction is

complete. Once this transaction completes the ISL95871C will

begin operating at the new current or voltage.

Maximum ripple is at 50% duty cycle or V

required inductance for ±15% ripple current can be calculated

from Equation 3:

= V /2. The

BAT

IN,MAX

V

IN, MAX

⋅ 0.3 ⋅ I

L, MAX

------------------------------------------------------

L =

(EQ. 3)

4 ⋅ F

SW

Where V

switching frequency and I

inductor.

is the maximum input voltage, F

is the

is the max DC current in the

IN,MAX

SW

L,MAX

For V

= 20V, V

BAT

= 12.6V, I

= 4.5A, and

BAT,MAX

IN,MAX

f = 400kHz, the calculated inductance is 9.3µH. Choosing the

s

closest standard value gives L = 10µH. Ferrite cores are often the

best choice since they are optimized at 400kHz to 600kHz

operation with low core loss. The core must be large enough not

The ISL95871C does not support writing more than one register

per transaction.

to saturate at the peak inductor current I

in Equation 4:

Peak

Reading from the Internal Registers

1

2

--

⋅ I

RIPPLE

I

= I

+

PEAK

L, MAX

(EQ. 4)

The ISL95871C has the ability to read from 5 internal registers.

Prior to reading from an internal register, the master must first

select the desired register by writing to it and sending the registers

address byte. This process begins by the master sending a control

byte with the R/W bit set to 0, indicating a write. Once it receives

an Acknowledge from the ISL95871C it sends a register address

byte representing the internal register it wants to read. The

ISL95871C will respond with an Acknowledge. The master must

then respond with a Stop condition. After the Stop condition, the

master follows with a new Start condition then sends a new

control byte with the ISL95871C slave address and the R/W bit set

to 1, indicating a read. The ISL95871C will Acknowledge then send

the lower byte stored in that register. After receiving the byte, the

master Acknowledges by holding SDA low during the 9th clock

pulse. ISL95871C then sends the higher byte stored in the register.

After the second byte neither device holds SDA low (No

Inductor saturation can lead to cascade failures due to very high

currents. Conservative design limits the peak and RMS current in

the inductor to less than 90% of the rated saturation current.

Crossover frequency is heavily dependent on the inductor value.

F

should be less than 20% of the switching frequency and a

CO

conservative design has F less than 10% of the switching

CO

frequency. The highest F is in voltage control mode with the

CO

battery removed and may be calculated (approximately) from

Equation 5:

5 ⋅ 11 ⋅ R

S2

-----------------------------

=

F

CO

2π ⋅ L

(EQ. 5)

Output Capacitor Selection

Acknowledge). The master will then produce a Stop condition to

end the read transaction.

The output capacitor in parallel with the battery is used to absorb

the high frequency switching ripple current and smooth the

FN6856.2

June 8, 2011

19

ISL95871C

output voltage. The RMS value of the output ripple current I

is given by Equation 6:

RMS

(EQ. 10)

V

(V – V

)

OUT

OUT IN

--------------------------------------------------

I

= I

⋅

RMS2

BAT

V

IN

IN, MAX

---------------------------------

I

=

⋅ D ⋅ (1 – D)

RMS1

where I

is the battery charging current. This RMS ripple

BAT

12 ⋅ L ⋅ F

(EQ. 6)

SW

current must be smaller than the rated RMS current in the

capacitor datasheet. Non-tantalum chemistries (ceramic,

aluminum, or OSCON) are preferred due to their resistance to

power-up surge currents when the AC-adapter is plugged into the

battery charger. For Notebook battery charger applications, it is

recommended that ceramic capacitors or polymer capacitors

from Sanyo be used due to their small size and reasonable cost.

Where the duty cycle D is the ratio of the output voltage (battery

voltage) over the input voltage for continuous conduction mode

which is typical operation for the battery charger. During the

battery charge period, the output voltage varies from its initial

battery voltage to the rated battery voltage. Thus, the duty cycle

varies from 0.53 for the minimum battery voltage of 7.5V

(2.5V/Cell) to 0.88 for the maximum battery voltage of 12.6V.

The maximum RMS value of the output ripple current occurs at

the duty cycle of 0.5 and is expressed as Equation 7:

Loop Compensation Design

ISL95871C has three closed loop control modes. One, controls

the output voltage when the battery is fully charged or absent. A

second, controls the current into the battery when charging and

the third, limits current drawn from the adapter. The charge

current and input current control loops are compensated by a

single capacitor on the ICOMP pin. The voltage control loop is

compensated by a network on the VCOMP pin. Descriptions of

these control loops and guidelines for selecting compensation

components will be given in the following sections. Which loop

controls the output is determined by the minimum current buffer

and the minimum voltage buffer shown in the “Functional Block

Diagram” on page 4. These three loops will be described

separately.

V

IN, MAX

-----------------------------------------

I

=

RMS1(max)

4 ⋅ 12 ⋅ L ⋅ F

(EQ. 7)

SW

For V

IN,MAX

= 19V, V

= 16.8V, L = 10µH, and f = 400kHz, the

BAT s

maximum RMS current is 0.19A. A typical 20µF ceramic

capacitor is a good choice to absorb this current and also has

very small size. Organic polymer capacitors have high

capacitance with small size and have a significant equivalent

series resistance (ESR). Although ESR adds to ripple voltage, it

also creates a high frequency zero that helps the closed loop

operation of the buck regulator.

EMI considerations usually make it desirable to minimize ripple

current in the battery leads. Beads may be added in series with

the battery pack to increase the battery impedance at 400kHz

switching frequency. Switching ripple current splits between the

battery and the output capacitor depending on the ESR of the

output capacitor and battery impedance. If the ESR of the output

capacitor is 10mΩ and battery impedance is raised to 2Ω with a

bead, then only 0.5% of the ripple current will flow in the battery.

Transconductance Amplifiers GMV, GMI and

GMS

ISL95871C uses several transconductance amplifiers (also

known as gm amps). Most commercially available op amps are

voltage controlled voltage sources with gain expressed as

A = V

/V . gm amps are voltage controlled current sources

/V . gm will appear in some of

the equations for poles and zeros in the compensation.

OUT IN

with gain expressed as gm = I

OUT IN

Snubber Design

PWM Gain F

The Pulse Width Modulator in the ISL95871C converts voltage at

VCOMP to a duty cycle by comparing VCOMP to a triangle wave

m

ISL95871C's buck regulator operates in discontinuous current

mode (DCM) when the load current is less than half the

peak-to-peak current in the inductor. After the low-side FET turns

off, the phase voltage rings due to the high impedance with both

FETs off. This can be seen in Figure 15 on page 10. Adding a

snubber (resistor in series with a capacitor) from the phase node

to ground can greatly reduce the ringing. In some situations a

snubber can improve output ripple and regulation.

(duty = VCOMP/V

). The low-pass filter formed by L and

convert the duty cycle to a DC output voltage

P-P RAMP

C

O

(Vo = V

*duty). In ISL95871C, the triangle wave amplitude is

proportional to V . Making the ramp amplitude proportional

DCIN

to DCIN makes the gain from VCOMP to the PHASE output a

constant 11 and is independent of DCIN. For small signal AC

analysis, the battery is modeled by its internal resistance. The

total output resistance is the sum of the sense resistor and the

internal resistance of the MOSFETs, inductor and capacitor.

Figure 26 shows the small signal model of the pulse width

modulator (PWM), power stage, output filter and battery.

The snubber capacitor should be approximately twice the

parasitic capacitance on the phase node. This can be estimated

by operating at very low load current (100mA) and measuring the

ringing frequency.

C

and R

can be calculated from Equations 8 and 9:

SNUB

2

-----------------------------------

(2πF

C

=

SNUB

(EQ. 8)

(EQ. 9)

2

) ⋅ L

ring

2 ⋅ L

R

-----------------

SNUB

C

SNUB

Input Capacitor Selection

The input capacitor absorbs the ripple current from the

synchronous buck converter, which is given by Equation 10:

FN6856.2

June 8, 2011

20

ISL95871C

L

PHASE

V_IN

11

RAMP GEN

R_{FET_RDSON}

R_{L_DCR}

V_RAMP= V_IN/11

L

-

CA2

R_F2

+

CSOP

CSON

Σ

0.25

S

+

20X

-

Σ

+

-

C_O

C_F2

R_S2

PWM

ICOMP

-

INPUT

GMI

+

R_BAT

C_O

R_ESR

DACI

C_ICOMP

PWM

GAIN=11

FIGURE 27. CHARGE CURRENT LIMIT LOOP

L

R_S2

11

1.5 ⋅ 4 ⋅ (50μA ⁄ V) ⋅ L

-----------------------------------------------------------------------------------

=

C

(EQ. 14)

R_{FET_RDSON}

R_{L_DCR}

ICOMP

(R + r

+ R

)

BAT

S2

DS(ON)

DCR

C_O

R_ESR

R_BAT

PWM

INPUT

A filter should be added between R_S2and CSOP and CSON to

reduce switching noise. The filter roll-off frequency should be

between the crossover frequency and the switching frequency

(~100kHz). R_F2should be small (<10Ω) to minimize offsets due

to leakage current into CSOP. The filter cutoff frequency is

calculated using Equation 15:

FIGURE 26. SMALL SIGNAL AC MODEL

In most cases, the battery resistance is very small (<200mΩ)

resulting in a very low Q in the output filter. This results in a

frequency response from the input of the PWM to the inductor

current with a single pole at the frequency calculated in

Equation 11:

1

----------------------------------------

F

=

(EQ. 15)

FILTER

(2π ⋅ C ⋅ R

)

F2

The crossover frequency is determined by the DC gain of the

modulator and output filter and the pole in Equation 12. The DC

gain is calculated in Equation 16 and the crossover frequency is

calculated with Equation 17. The Bode plot of the loop gain, the

compensator gain and the power stage gain is shown in

Figure 28.

(R + r

+ R

)

S2

DS(ON)

DCR

BAT

(EQ. 11)

-----------------------------------------------------------------------------------

=

F

POLE1

2π ⋅ L

The output capacitor creates a pole at a very high frequency due

to the small resistance in parallel with it. The frequency of this

pole is calculated in Equation 12:

1

-----------------------------------

F

=

11 ⋅ R

(EQ. 12)

POLE2

S2

2π ⋅ C ⋅ R

-----------------------------------------------------------------------------------

=

A

o

BAT

(EQ. 16)

(EQ. 17)

DC

(R + r

+ R

)

BAT

S2

DS(ON)

DCR

Charge Current Control Loop

11 ⋅ R

S2

---------------------

F

= A ⋅ F

=

When the battery is less than fully charged, the voltage error

amplifier goes to its maximum output (limited to 0.3V above

ICOMP) and the ICOMP voltage controls the loop through the

minimum voltage buffer. Figure 28 shows the charge current

control loop.

CO

DC POLE

2π ⋅ L

Adapter Current Limit Control Loop

If the combined battery charge current and system load current

draws current that equals the adapter current limit set by the

InputCurrent register, ISL95871C will reduce the current to the

battery and/or reduce the output voltage to hold the adapter

current at the limit. Above the adapter current limit, the

minimum current buffer equals the output of GMS and ICOMP

controls the charger output. Figure 29 shows the adapter current

limit control loop.

The compensation capacitor (C

) gives the error amplifier

ICOMP

(GMI) a pole at a very low frequency (<<1Hz) and a zero at F

.

Z1

F

is created by the 0.25*CA2 output added to ICOMP. The

Z1

frequency can be calculated from Equation 13:

4 ⋅ gm2

------------------------------------

=

F

(EQ. 13)

gm2 = 50μA ⁄ V

ZERO

(2π ⋅ C

)

ICOMP

Placing this zero at a frequency equal to the pole calculated in

Equation 12 will result in maximum gain at low frequencies and

phase margin near 90°. If the zero is at a higher frequency

(smaller C

), the DC gain will be higher but the phase

ICOMP

margin will be lower. Use a capacitor on ICOMP that is equal to or

greater than the value calculated in Equation 14. The factor of

1.5 is to ensure the zero is at a frequency lower than the pole

including tolerance variations.

FN6856.2

June 8, 2011

21

ISL95871C

across the internal battery resistance decreases. As battery

60

40

20

0

current decreases, the 2 current error amplifiers (GMI and GMS)

output their maximum current and charge the capacitor on

ICOMP to its maximum voltage (limited to 0.3V above VCOMP).

With high voltage on ICOMP, the minimum voltage buffer output

equals the voltage on VCOMP.

COMPENSATOR

MODULATOR

LOOP

F

ZERO

The voltage control loop is shown in Figure 30.

L

PHASE

11

-20

-40

-60

R_{L_DCR}

R_{FET_RDSON}

F

POLE1

FILTER

F

POLE2

CA2

R_F2

+

CSOP

CSON

0.25

S

Σ

+

20x

-

10

100

1k

10k

100k

1M

-

C_F2

R_S2

FREQUENCY (Hz)

FIGURE 28. CHARGE CURRENT LOOP BODE PLOTS

R3

R4

VCOMP

R_BAT

-

GMV

+

C_O

R_ESR

DCIN

C_VCOMP

R_VCOMP

L

PHASE

R_S1

DACV

11

R_{FET_RDSON}

R_{L_DCR}

R_F1

C_F1

FIGURE 30. VOLTAGE CONTROL LOOP

CA2

R_F2

CSOP

CSON

+

-

0.25

+

20X

-

S

Σ

C_F2

Output LC Filter Transfer Functions

The gain from the phase node to the system output and battery

depend entirely on external components. Typical output LC filter

R_S2

CSSN

-

20

C_O

+

R_BAT

CA1

response is shown in Figure 31. Transfer function A (s) is shown

CSSP

LC

R_ESR

in Equation 18:

s

-

GMS

+

⎛

⎝

⎞

⎠

-------------

1 –

DACS

ICOMP

ω

ESR

(EQ. 18)

--------------------------------------------------------

A

=

C_ICOMP

LC

2

⎛

⎜

⎝

⎞

s

ω

s

---------- -----------------------

+

+ 1

⎟

⎠

(ω ⋅ Q)

LC

DP

FIGURE 29. ADAPTER CURRENT LIMIT LOOP

1

L

C

o

The loop response equations, bode plots and the selection of

_ICOMPare the same as the charge current control loop with loop

gain reduced by the duty cycle and the ratio of R /R . In other

----------------------

=

(

-----------------------------

ω

=

Q = R

⋅

-----

LC

ESR

o

(R

⋅ C )

o

L ⋅ C )

o

ESR

C

S1 S2

The resistance R is a combination of MOSFET r

DCR, R and the internal resistance of the battery (normally

between 50mΩ and 200mΩ). The worst case for voltage mode

control is when the battery is absent. This results in the highest Q

of the LC filter and the lowest phase margin.

, inductor

DS(ON)

O

words, if R = R and the duty cycle D = 50%, the loop gain will

S1 S2

S2

be 6dB lower than the loop gain in Figure 29. This gives lower

crossover frequency and higher phase margin in this mode. If

R

/R = 2 and the duty cycle is 50% then the adapter current

S1 S2

loop gain will be identical to the gain in Figure 29.

The compensation network consists of the voltage error amplifier

A filter should be added between R and CSIP and CSIN to

S1

GMV and the compensation network R which give

, C

VCOMP VCOMP

reduce switching noise. The filter roll off frequency should be

between the crossover frequency and the switching frequency

(~100kHz).

the loop very high DC gain, a very low frequency pole and a zero at

. Inductor current information is added to the feedback to

F

ZERO1

create a second zero F

. The low pass filter R , C between

ZERO2

and ISL95871C add a pole at F

F2 F2

R

. R and R are internal

3 4

Voltage Control Loop

S2

FILTER

divider resistors that set the DC output voltage. For a 3-cell battery,

R = 500kΩ and R = 100kΩ. The equations following relate the

When the battery is charged to the voltage set by ChargeVoltage

register the voltage error amplifier (GMV) takes control of the

output (assuming that the adapter current is below the limit set

by ACLIM). The voltage error amplifier (GMV) discharges the cap

on VCOMP to limit the output voltage. The current to the battery

decreases as the cells charge to the fixed voltage and the voltage

3

4

compensation network’s poles, zeros and gain to the components

in Figure 30. Figure 32 shows an asymptotic Bode plot of the

DC/DC converter’s gain vs frequency. It is strongly recommended

that F

is approximately 30% of F and F is

ZERO1

LC ZERO2

approximately 70% of F

.

LC

FN6856.2

June 8, 2011

22

ISL95871C

1

-----------------------------------------

=

F

(EQ. 24)

ESR

10

(2π ⋅ C ⋅ R

)

ESR

o

0

NO BATTERY

-10

-20

-30

-40

-50

-60

Choose R

VCOMP

Equation 25.

equal or lower than the value calculated from

R

= 200mΩ

BATTERY

R

+ R

4

R

4

⎛

⎜

⎝

⎞

⎟

⎠

5

gm1

3

⎛

⎝

⎞

⎠

------------

--------------------

R

= (0.7 ⋅ F ) ⋅ (2π ⋅ C ⋅ R ) ⋅

⋅

R

= 50mΩ

BATTERY

VCOMP

LC

o

S2

(EQ. 25)

Next, choose C

from Equation 26.

equal or higher than the value calculated

VCOMP

-20

-40

-60

1

----------------------------------------------------------------------

=

C

(EQ. 26)

VCOMP

(0.3 ⋅ F ) ⋅ (2π ⋅ R

)

VCOMP

-80

-100

LC

-120

-140

PCB Layout Considerations

-160

Power and Signal Layers Placement on the PCB

100 200

500 1k 2k

5k 10k 20k

50k 100k 200k 500k

As a general rule, power layers should be close together, either

on the top or bottom of the board, with signal layers on the

opposite side of the board. As an example, layer arrangement on

a 4-layer board is shown below:

FREQUENCY (Hz)

FIGURE 31. FREQUENCY RESPONSE OF THE LC OUTPUT FILTER

60

1. Top Layer: signal lines, or half board for signal lines and the

other half board for power lines

COMPENSATOR

MODULATOR

40

2. Signal Ground

LOOP

F

3. Power Layers: Power Ground

F

POLE1

LC

20

0

4. Bottom Layer: Power MOSFET, Inductors and other Power

traces

Separate the power voltage and current flowing path from the

control and logic level signal path. The controller IC will stay on

the signal layer, which is isolated by the signal ground to the

power signal traces.

F

FILTER

-20

-40

-60

F

ZERO1

F

ZERO2

Component Placement

The highest priority for placement close to the IC are the high current

components. Place the VIN capacitors as close as possible to the VIN

and PGND pins. The power inductor, charge current sense resistor

and output caps are the second highest priority. A layer of power

ground under these components and high current pins on

ISL95871C (pins 9 through 33) will keep current loops small and

minimize EMI radiated from this high current loops.

F

ESR

100

1k

10k

100k

1M

FREQUENCY (Hz)

FIGURE 32. ASYMPTOTIC BODE PLOT OF THE VOLTAGE CONTROL

LOOP GAIN

Compensation Break Frequency Equations

Small signals such as current sense and compensation should be

placed near their connections to ISL95871C and have an area of

AGND “quiet ground”) on the adjacent layer. An area of quiet

ground should be on the layer under ISL95871C pins 1 through 8

and 34 through 50. The best tie-point between the signal ground

and the power ground is at the negative side of the output

capacitor on each side, where there is little noise; a noisy trace

beneath the IC is not recommended.

1

----------------------------------------------------------------

F

=

(EQ. 19)

(EQ. 20)

(EQ. 21)

ZERO1

(2π ⋅ C

⋅ R

)

VCOMP

R

4

⎛

⎜

⎝

⎞

⎛

⎞

⎟

⎠

gm1

5

VCOMP

⎛

⎝

⎞

⎠

--------------------------------

--------------------

------------

F

=

⋅

⎟

⎜

⎝

ZERO2

2π ⋅ R ⋅ C

R

+ R

3

⎠

S2

4

o

1

------------------------------

(2π L ⋅ C )

=

LC

Signal Ground and Power Ground Connection

o

At minimum, a reasonably large area of copper, which will shield

other noise couplings through the IC, should be used as signal

ground beneath the IC. The best tie-point between the signal

ground and the power ground is at the negative side of the output

capacitor on each side, where there is little noise; a noisy trace

beneath the IC is not recommended.

1

----------------------------------------

F

=

(EQ. 22)

(EQ. 23)

FILTER

POLE1

(2π ⋅ R ⋅ C

)

F2

1

-------------------------------------

(2π ⋅ R ⋅ C )

S2

o

FN6856.2

June 8, 2011

23

ISL95871C

AGND and VDD Pin

CSOP, CSON, CSIP and CSIN Pins

At least one high quality ceramic decoupling capacitor should be

used to cross these two pins. The decoupling capacitor can be

put close to the IC.

Accurate charge current and adapter current sensing is critical

for good performance. The current sense resistor connects to the

CSON and the CSOP pins through a low pass filter with the filter

capacitor very near the IC (see Figure 4 on page 4). Traces from

the sense resistor should start at the pads of the sense resistor

and should be routed close together, through the low pass filter

and to the CSOP and CSON pins (see Figure 33). The CSON pin is

also used as the battery voltage feedback. The traces should be

routed away from the high dv/dt and di/dt pins like PHASE, BOOT

pins. In general, the current sense resistor should be close to the

IC. These guidelines should also be followed for the adapter

current sense resistor and CSIP and CSIN. Other layout

PGND Pins

PGND pin should be laid out to the negative side of the relevant

output capacitor with separate traces. The negative side of the

output capacitor must be close to the source node of the bottom

MOSFET. This trace is the return path of LFET gate drive.

PHASE Pins

Connect this pin to the output inductor. This trace should be

short, and positioned away from other weak signal traces. This

node has a very high dv/dt with a voltage swing from the input

voltage to ground. No trace should be in parallel with it.

arrangements should be adjusted accordingly.

DCIN Pin

This pin connects to AC-adapter output voltage, and should be

less noise sensitive.

BOOT Pin

This pin carries gate drive current and trace should be as short as

possible.

Copper Size for the Phase Node

The capacitance of PHASE should be kept very low to minimize

ringing. It would be best to limit the size of the PHASE node

copper in strict accordance with the current and thermal

management of the application.

SEN SE

H IG H

C U R R EN T

TR A CE

H IG H

C U R R EN T

TR A CE

R ESISTO R

Identify the Power and Signal Ground

K ELV IN C O N N EC TIO N TR A C ES

TO TH E LO W PA SS FILTER A N D

C S O P A N D CS O N

The input and output capacitors of the converters, the source

terminal of the bottom switching MOSFET PGND should connect

to the power ground. The other components should connect to

signal ground. Signal and power ground are tied together at one

point as close as possible to the ISL95871C.

FIGURE 33. CURRENT SENSE RESISTOR LAYOUT

Clamping Capacitor for Switching MOSFET

It is recommended that ceramic capacitors be used closely

connected to VIN and PGND (the drain of the high-side MOSFET

and the source of the low-side MOSFET). This capacitor reduces

the noise and the power loss of the MOSFETs.

FN6856.2

June 8, 2011

24

ISL95871C

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE

REVISION

FN6856.2

CHANGE

5/27/11

On page 7 in the “Electrical Specifications” table:

Removed “ICM Gain” limits

Removed “ICM Offset” specs

9/28/10

9/20/10

FN6856.1

FN6856.0

Corrected max limit of “ACIN Rising Threshold” on page 7 from 3.25V to 3.28V

Initial Release.

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page

on intersil.com: ISL95871C

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

FITs are available from our website at: http://rel.intersil.com/reports/sear

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6856.2

June 8, 2011

25

ISL95871C

Package Outline Drawing

L50.5x7

50 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 1/10

3.50

B

PIN 1

INDEX AREA

5.00

2X 3.20

36X 0.40

41

A

42

50

PIN #1

IDENTIFICATION

1

46X 0.40

2.575

2X 6.00

4

50X 0.20

0.35

0.10 M C A B

0.45

0.62

2X 0.60

0.35

1.7299

1.275

1.725

2.525

2X 1.00

26

16

0.10

25

1.40

17

2X

0.296

0.5885

6X 0.1950

6X 0.15

1.40

TOP VIEW

BOTTOM VIEW

(3.50)

(2X 3.20)

PACKAGE OUTLINE

PIN ONE

SEE DETAIL "X"

0.10 C

(46X 0.40)

MAX. 1.0

(36X 0.60)

(2.575)

C

SEATING PLANE

0.05 C

SIDE VIEW

(2X 7.4)

(0.35)

(0.45)

(0.62)

(2X 6.0)

(0.35)

(1.7299)

5

(1.275)

(1.725)

(1.40)

0 . 2 REF

C

(2.725)

(0.7885)

0-0.05

(0.496)

DETAIL "X"

(6X 0.395)

(1.40)

(4.20)

(5.40)

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

TYPICAL RECOMMENDED LAND PATTERN

2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.10

Angular ±2.50°

4. Dimension applies to the metallized terminal and is measured

between 0.015mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN6856.2

June 8, 2011

26


型号：	ISL95871C_11
厂家：	Intersil
描述：	SMBus Interfaced Battery Charger with Internal FETs 的SMBus接口电池充电器，内置FET的电池
文件：	总26页 (文件大小：897K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL95871C_11 [INTERSIL]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E