ISL95872 [RENESAS]
Buck PWM Controller with Internal Compensation and External Reference Tracking;
| 型号： | ISL95872 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Buck PWM Controller with Internal Compensation and External Reference Tracking |
| 文件： | 总17页 (文件大小：830K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL95872
FN7974
Rev 0.00
January 26, 2012
Buck PWM Controller with Internal Compensation and External Reference
Tracking
The ISL95872 is a Single-Phase Synchronous-Buck PWM
Features
controller featuring Intersil’s proprietary R4™ Technology. The
• External Reference Tracking
• Intersil’s R4™ Modulator Technology
R4™ modulator has integrated compensation, fast transient
performance, accurate switching frequency control, and
excellent light-load efficiency. These technology advances,
together with integrated MOSFET drivers and a schottky
bootstrap diode, allow for a high performance regulator that is
highly compact and needs few external components.
Differential remote sensing of the output voltage is an
additional feature. For maximum efficiency, the converter
automatically enters diode-emulation mode (DEM) during
light-load conditions such as system standby.
- Internal Compensation
- Fast, Optimal Transient Response
• Input Voltage Range: 3.3V to 25V
• Output Voltage Range: 0.5V to 3.3V
• Precision Voltage Regulation
- ±0.5% System Accuracy Over -10°C to +100°C
• Output Voltage Remote Sense
The ISL95872 accepts a wide 3.3V to 25V input voltage range,
making it ideal for systems that run on battery or AC-adapter
power sources. It also is a low-cost solution for applications
requiring tracking of an external reference voltage during soft-
start. When the external reference level meets the internal
reference voltage, the ISL95872 switches from the external
reference to the internal reference. The external reference is
only used during soft-start.
• Fixed 300kHz PWM Frequency in Continuous Conduction
- Proprietary Frequency Control Loop
• Automatic Diode Emulation Mode for Highest Efficiency
• Power-Good Monitor for Soft-Start and Fault Detection
Applications
• Compact Buck Regulators Requiring External Tracking
R
C
VCC
+5V
C
VCC
PVCC
V
IN
3.3V TO 25V
CIN
Q
HS
1
12
11
10
9
GND
RTN
BOOT
R
FB1
RTN1
2
V
UGATE
PHASE
PGOOD
L
OUT
O
0.5V TO 3.3V
3
4
EN
GPIO
Q
LS
CO
REFIN
C
SEN
RTN1
C
BOOT
R
O
External
Reference
Voltage
0
R
FB
R
OFS
FIGURE 1. ISL95872 APPLICATION SCHEMATIC WITH DCR CURRENT SENSE
FN7974 Rev 0.00
January 26, 2012
Page 1 of 17
ISL95872
Application Schematics
R
VCC
+5V
C
VCC
C
PVCC
V
IN
3.3V TO 25V
CIN
Q
HS
GND
RTN
BOOT
1
2
3
4
12
11
10
9
R
FB1
RTN1
UGATE
PHASE
PGOOD
V
L
OUT
O
0.5V TO 3.3V
EN
GPIO
Q
LS
REFIN
CO
RTN1
C
SEN
C
BOOT
R
O
R
FB
External
Reference
Voltage
0
R
OFS
FIGURE 2. ISL95872 APPLICATION SCHEMATIC WITH ONE OUTPUT VOLTAGE SETPOINT AND DCR CURRENT SENSE
R
VCC
+5V
C
VCC
C
PVCC
V
IN
3.3V TO 25V
CIN
Q
HS
GND
RTN
BOOT
1
2
3
4
12
11
10
9
R
FB1
RTN1
UGATE
PHASE
PGOOD
V
L
OUT
O
R
SEN
0.5V TO 3.3V
EN
GPIO
Q
LS
REFIN
CO
C
SEN
RTN1
C
BOOT
R
O
R
1
R
FB
External
Reference
Voltage
0
R
2
FIGURE 3. ISL95872 APPLICATION SCHEMATIC WITH ONE OUTPUT VOLTAGE SETPOINT AND RESISTOR CURRENT SENSE
FN7974 Rev 0.00
January 26, 2012
Page 2 of 17
Block Diagram
VCC
POR
SOFT-START
CIRCUITRY
BOOT
EN
DRIVER
UGATE
PHASE
PGOOD
PGOOD
CIRCUITRY
DEAD-TIME
GENERATION
FB
PVCC
INTERNAL
COMPENSATION
AMPLIFIER
UNDERVOLTAGE
MONITOR
SREF
DRIVER
+
LGATE
PGND
R4TM
MODULATOR
VO
REFERENCE
VOLTAGE
CIRCUITRY
REMOTE SENSE
CIRCUITRY
REFIN
GND
OVERCURRENT
OCSET
RTN
FIGURE 4. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL95872
ISL95872
Ordering Information
PART NUMBER
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL95872HRUZ-T (Notes 1, 2)
GBT
-10 to +100
16 Ld 2.6x1.8 UTQFN
L16.2.6x1.8A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Functional Pin Descriptions
Pin Configuration
PIN
ISL95872
(16 LD 2.6X1.8 UTQFN)
TOP VIEW
NUMBER SYMBOL
DESCRIPTION
8
VO
Output voltage sense input for the R4TM modulator.
The VO pin also serves as the reference input for
the overcurrent detection circuit.
9
PGOOD Power-good open-drain indicator output. This pin
changes to high impedance when the converter is
able to supply regulated voltage.
10
PHASE Return current path for the UGATE high-side
GND 1
12 BOOT
11 UGATE
10 PHASE
9 PGOOD
MOSFET driver, V sense input for the R4TM
IN
RTN 2
EN 3
modulator, and inductor current polarity detector
input.
11
12
UGATE High-side MOSFET gate driver output. Connect to
the gate terminal of the high-side MOSFET of the
converter.
4
REFIN
BOOT Positive input supply for the UGATE high-side
MOSFET gate driver. The BOOT pin is internally
connected to the cathode of the Schottky
boot-strap diode. Connect an MLCC between the
BOOT pin and the PHASE pin.
Functional Pin Descriptions
13
14
VCC
Input for the IC bias voltage. Connect +5V to the
VCC pin and decouple with at least a MLCC to the
GND pin.
PIN
NUMBER SYMBOL
DESCRIPTION
1
2
GND
RTN
IC ground for bias supply and signal reference.
PVCC Input for the LGATE and UGATE MOSFET driver
circuits. The PVCC pin is internally connected to the
anode of the Schottky boot-strap diode. Connect
+5V to the PVCC pin and decouple with a MLCC to
the PGND pin.
Negative remote sense input of V . If resistor
OUT
divider consisting of R and R
is used at FB
FB OFS
pin, the same resistor divider should be used at
RTN pin, i.e. keep R = R , and R = R
.
FB1
FB OFS1 OFS
15
16
LGATE Low-side MOSFET gate driver output. Connect to
the gate terminal of the low-side MOSFET of the
converter.
3
4
5
EN
Enable input for the IC. Pulling EN above the rising
threshold voltage initializes the soft-start sequence.
REFIN Input for suppling the external reference voltage
followed by the controller during soft-start.
PGND Return current path for the LGATE MOSFET driver.
Connect to the source of the low-side MOSFET.
SREF Soft-start and voltage slew-rate programming
capacitor input. Connects internally to the inverting
input of the V
voltage setpoint amplifier.
SET
6
7
FB
Voltage feedback sense input. Connects internally
to the inverting input of the control-loop error
amplifier. The converter is in regulation when the
voltage at the FB pin equals the voltage on the
SREF pin.
OCSET Input for the overcurrent detection circuit. The
overcurrent setpoint programming resistor R
connects from this pin to the sense node.
OCSET
FN7974 Rev 0.00
January 26, 2012
Page 4 of 17
ISL95872
Table of Contents
Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Enabling the Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
External Reference Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Output Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
R4TM Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Diode Emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Undervoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Over-Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PGOOD Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Integrated MOSFET Gate-Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Adaptive Shoot-Through Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
General Application Design Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Selecting the LC Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Selecting the Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Selecting the Bootstrap Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Driver Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MOSFET Selection and Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package Outline Drawing L16.2.6x1.8A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FN7974 Rev 0.00
January 26, 2012
Page 5 of 17
ISL95872
Absolute Maximum Ratings
Thermal Information
VCC, PVCC, PGOOD, FSEL to GND. . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
VCC, PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
EN,VO,REFIN,FB,RTN,OCSET,SREF . . . . . . . . . . . . -0.3V to GND, VCC + 0.3V
Thermal Resistance (Typical)
16 Ld UTQFN (Notes 3, 4) . . . . . . . . . . . . . .
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -55C to +150C
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
JA (°C/W)
90
JC (°C/W)
60
BOOT Voltage (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 33V
BOOT-GND
BOOT To PHASE Voltage (V
). . . . . . . . . . . . . . . . -0.3V to 7V (DC)
BOOT-PHASE
-0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 28V
GND -8V (<20ns Pulse Width, 10µJ)
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Converter Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . 3.3V to 25V
VCC, PVCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%
UGATE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . V
- 0.3V (DC) to V
PHASE
- 5V (<20ns Pulse Width, 10µJ) to V
BOOT
BOOT
V
PHASE
LGATE Voltage. . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V (DC) to VCC + 0.3V
. . . . . . . . . . . . . . . . . .GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . . 175V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . . . . 1kV
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
4. For , the “case temp” location is taken at the package top center.
JC
Electrical Specifications All typical specifications T = +25°C, V = 5V. Boldface limits apply over the operating temperature
A
CC
range, -10°C to +100°C, unless otherwise stated.
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
VCC and PVCC
VCC Input Bias Current
VCC Shutdown Current
PVCC Shutdown Current
VCC POR THRESHOLD
Rising VCC POR Threshold Voltage
Falling VCC POR Threshold Voltage
REGULATION
I
EN = 5V, VCC = 5V, FB = 0.55V, SREF < FB
EN = GND, VCC = 5V
-
-
-
1.2
0
1.9
1.0
1.0
mA
µA
µA
VCC
I
VCCoff
I
EN = GND, PVCC = 5V
0
PVCCoff
V
4.40
4.10
4.52
4.22
4.60
4.35
V
V
VCC_THR
V
VCC_THF
System Accuracy
PWM Mode = CCM
-0.5
-
-
+0.5
-
%
V
Internal Reference Voltage
Feedback Voltage Reference Transfer Voltage
PWM
0.5
0.461
0.482
0.4975
V
Switching Frequency Accuracy
VO
F
PWM Mode = CCM
EN = 5V
255
300
345
kHz
SW
VO Input Impedance
R
-
-
-
600
8.5
0
-
-
-
k
µA
µA
VO
VO Reference Offset Current
VO Input Leakage Current
ERROR AMPLIFIER
I
V
< EN, SREF = Soft-Start Mode
ENTHR
VOSS
VOoff
I
EN = GND, VO = 3.6V
EN = 5V, FB = 0.50V
SREF = Soft-Start Mode
FB Input Bias Current
SREF
I
I
-30
-
+50
nA
µA
FB
SS
Maximum Soft-Start Current
POWER GOOD
±51
85
±119
PGOOD Pull-down Impedance
PGOOD Leakage Current
R
PGOOD = 5mA Sink
PGOOD = 5V
-
-
50
150
1.0
PG
I
0.1
µA
PG
FN7974 Rev 0.00
January 26, 2012
Page 6 of 17
ISL95872
Electrical Specifications All typical specifications T = +25°C, V = 5V. Boldface limits apply over the operating temperature
A
CC
range, -10°C to +100°C, unless otherwise stated. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
GATE DRIVER
UGATE Pull-Up Resistance (Note 5)
UGATE Source Current (Note 5)
UGATE Sink Resistance (Note 5)
UGATE Sink Current (Note 5)
LGATE Pull-Up Resistance (Note 5)
LGATE Source Current (Note 5)
LGATE Sink Resistance (Note 5)
LGATE Sink Current (Note 5)
UGATE to LGATE Deadtime
LGATE to UGATE Deadtime
PHASE
R
200mA Source Current
UGATE - PHASE = 2.5V
-
-
-
-
-
-
-
-
-
-
1.1
1.8
1.1
1.8
1.1
1.8
0.55
3.6
21
1.7
A
UGPU
I
-
UGSRC
R
250mA Sink Current
1.7
A
UGPD
I
UGATE - PHASE = 2.5V
-
UGSNK
R
250mA Source Current
LGATE - GND = 2.5V
1.7
A
LGPU
I
-
LGSRC
R
250mA Sink Current
1.0
A
LGPD
I
LGATE - PGND = 2.5V
-
-
-
LGSNK
t
UGATE falling to LGATE rising, no load
LGATE falling to UGATE rising, no load
ns
ns
UGFLGR
LGFUGR
t
21
R
-
33
-
k
PHASE Input Impedance
BOOTSTRAP DIODE
PHASE
Forward Voltage
V
PVCC = 5V, I = 2mA
F
-
-
0.58
0
-
-
V
F
Reverse Leakage
I
V
= 25V
R
µA
R
CONTROL INPUTS
EN High Threshold Voltage
EN Low Threshold Voltage
EN Input Bias Current
V
2.0
-
-
-
V
V
ENTHR
V
-
0.85
-
1.0
2.55
1.0
ENTHF
I
EN = 5V
1.7
0
µA
µA
EN
EN Leakage Current
I
EN = GND
ENoff
PROTECTION
OCP Threshold Voltage
OCP Reference Current
OCSET Input Resistance
OCSET Leakage Current
UVP Threshold Voltage
V
V
- V
-1.15
-
1.15
mV
µA
k
µA
%
OCPTH
OCSET
O
I
EN = 5.0V
EN = 5.0V
EN = GND
7.905
8.5
600
0
8.925
OCP
R
-
-
OCSET
I
-
81
-
-
87
-
OCSET
V
V
= %V
84
150
UVTH
FB
SREF
OTP Rising Threshold Temperature
(Note 5)
T
°C
OTRTH
OTP Hysteresis (Note 5)
NOTES:
T
-
25
-
°C
OTHYS
5. Limits established by characterization and are not production tested.
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and
are not production tested.
FN7974 Rev 0.00
January 26, 2012
Page 7 of 17
ISL95872
Soft-Start
Theory of Operation
The following sections will provide a detailed description of the
inner workings of the ISL95872.
Once the POR threshold on VCC has been met and ENABLE is
applied, the SREF pin releases its discharge clamp, and enables
the reference amplifier V . The soft-start current I is limited
SET SS
to 85µA and is sourced out of the SREF pin and begins charging
the C capacitor on the SREF pin until it equals V . The
soft-start current will adjust to match the external reference
ramp rate as seen through the resistor divider on the REFIN pin.
The regulator controls the PWM such that the voltage on the
SREF pin tracks the rising voltage on the REFIN pin. The
Power-On Reset
The IC is disabled until the voltage at the VCC pin has increased
above the rising power-on reset (POR) threshold voltage
SOFT REFIN
V
. The controller will become disabled when the voltage
VCC_THR
at the VCC pin decreases below the falling POR threshold voltage
V
. The POR detector has a noise filter of approximately
VCC_THF
1µs.
maximum dv/dt that the external voltage (V ) can achieve is
EXT
outlined in Equation 2.
dV
I
R + R
1 2
R
2
Enabling the Controller
EXT
SS
------------------
------------------- --------------------
(EQ. 2)
=
dt
C
SOFT
Once VCC has ramped above V
, the controller can be
VCC_THR
enabled by pulling the EN pin voltage above the input-high
threshold V . Once EN exceeds this threshold, the soft-start
sequence is initiated.
The elapsed time from when the EN pin is asserted to when
has charged C to V will depend on the dv/dt of
ENTHR
V
SREF
the external reference voltage used to generate the signal at
REFIN. C will not impact the dv/dt unless it is over sized or
SOFT
REF IN
SOFT
the dv/dt, outlined in Equation 2, is exceeded by the external
reference. The minimum C capacitance is 10nF.
External Reference Setup
The REFIN input of the ISL95872 requires an external reference
voltage to be connected to this pin. Typically, this will be another
system rail which requires the output of the ISL95872 to follow it
up during boot-up of the two regulators. A resistor divider is
required between the external reference voltage and the REFIN
pin to scale the external voltage down to the internal reference
voltage, see Figure 5.
SOFT
Once the feedback voltage, FB, exceeds the 0.482V threshold on
an internal comparator, the ISL95872 switches from the external
reference (V ) to the internal reference, V , see Figure 6.The
EXT REF
end of soft-start is detected by I tapering off when capacitor
SS
C
charges to V
. The pull-down on PGOOD is released to
SOFT
indicate that the controller is regulating properly.
REFIN
V
R
FB
OUT
Slope determined
by load current
FB
V
COMP
V
EXT
EA
V
REF
SET
V
SREF
V
REF
V
REFIN
V
REFIN
V
0.482V
EXT
REFIN
FB
R
1
FIGURE 6. SOFT-START TRACKING OF EXTERNAL REFERENCE
R
2
During soft-start, the regulator always operates in CCM until the
soft-start sequence is complete. Once soft-start is complete
diode emulation mode (DEM) is enabled.
FIGURE 5. REFIN CONNECTION TO SYSTEM RAIL
The relation between the voltage at the REFIN pin, V
REFIN
, and
the external reference voltage, V , is given in Equation 1:
Output Voltage Programming
The ISL95872 has a fixed 0.5V internal reference voltage
EXT
R
2
(EQ. 1)
--------------------
V
= V
= V
REFIN
REF
EXT
R
+ R
2
(V
). As shown in Figure 7, the output voltage is the reference
is open. A resistor divider
1
SREF
voltage if R is shorted and R
FB OFS
consisting of R
and R allows the user to scale the output
From this expression the resistor divider values can be
calculated. The voltage on the REFIN pin must equal to the
internal reference of the ISL95872.
OFS FB
voltage between 0.5V and 3.3V. The relation between the output
voltage and the reference voltage is given in Equation 3:
R
+ R
OFS
FB
(EQ. 3)
---------------------------------
V
= V
OUT
REF
R
OFS
FN7974 Rev 0.00
January 26, 2012
Page 8 of 17
ISL95872
COMPENSATION TO COUNTER
INTEGRATOR POLE
INTEGRATOR
V
R
FB
OUT
FOR HIGH DC GAIN
FB
V
V
COMP
EA
V
OUT
REF
V
COMP
V
SET
V
DAC
FIGURE 8. INTEGRATOR ERROR-AMPLIFIER CONFIGURATION
SREF
R3TM LOOP GAIN (dB)
INTEGRATOR POLE
p1
L/C DOUBLE-POLE
FIGURE 7. ISL95872 VOLTAGE PROGRAMMING CIRCUIT
p2
R4TM Modulator
-20dB CROSSOVER
REQUIRED FOR STABILITY
p3
The R4™ modulator is an evolutionary step in R3™ technology.
Like R3™, the R4™ modulator allows variable frequency in
response to load transients and maintains the benefits of
current-mode hysteretic controllers. However, in addition, the
R4™ modulator reduces regulator output impedance and uses
accurate referencing to eliminate the need for a high-gain
voltage amplifier in the compensation loop. The result is a
topology that can be tuned to voltage-mode hysteretic transient
speed while maintaining a linear control model and removes the
need for any compensation. This greatly simplifies the regulator
design for customers and reduces external component cost.
COMPENSATOR TO
ADD z2 IS NEEDED
CURRENT-MODE
ZERO
z1
f (Hz)
FIGURE 9. UNCOMPENSATED INTEGRATOR OPEN-LOOP RESPONSE
Stability
Figure 8 illustrates the classic integrator configuration for a
voltage loop error-amplifier. While the integrator provides the
high DC gain required for accurate regulation in traditional
technologies, it also introduces a low-frequency pole into the
control loop. Figure 9 shows the open-loop response that results
from the addition of an integrating capacitor in the voltage loop.
The compensation components found in Figure 8 are necessary
to achieve stability.
The removal of compensation derives from the R4™ modulator’s
lack of need for high DC gain. In traditional architectures, high DC
gain is achieved with an integrator in the voltage loop. The
integrator introduces a pole in the open-loop transfer function at
low frequencies. That, combined with the double-pole from the
output L/C filter, creates a three pole system that must be
compensated to maintain stability.
Classic control theory requires a single-pole transition through
unity gain to ensure a stable system. Current-mode architectures
(includes peak, peak-valley, current-mode hysteretic, R3™ and
R4™) generate a zero at or near the L/C resonant point,
effectively canceling one of the system’s poles. The system still
contains two poles, one of which must be canceled with a zero
before unity gain crossover to achieve stability. Compensation
components are added to introduce the necessary zero.
Because R4™ does not require a high-gain voltage loop, the
integrator can be removed, reducing the number of inherent
poles in the loop to two. The current-mode zero continues to
cancel one of the poles, ensuring a single-pole crossover for a
wide range of output filter choices. The result is a stable system
with no need for compensation components or complex
equations to properly tune the stability.
Figure 10 shows the R4™ error-amplifier that does not require an
integrator for high DC gain to achieve accurate regulation. The
result to the open loop response can be seen in Figure 11.
FN7974 Rev 0.00
January 26, 2012
Page 9 of 17
ISL95872
The dotted red and blue lines in Figure 12 represent the time
delayed behavior of V and V in response to a load
transient when an integrator is used. The solid red and blue lines
illustrate the increased response of R4™ in the absence of the
integrator capacitor.
OUT COMP
R2
V
OUT
V
COMP
R1
Diode Emulation
V
DAC
The polarity of the output inductor current is defined as positive
when conducting away from the phase node, and defined as
negative when conducting towards the phase node. The DC
component of the inductor current is positive, but the AC
component known as the ripple current, can be either positive or
negative. Should the sum of the AC and DC components of the
inductor current remain positive for the entire switching period,
the converter is in continuous-conduction-mode (CCM). However,
if the inductor current becomes negative or zero, the converter is
in discontinuous-conduction-mode (DCM).
FIGURE 10. NON-INTEGRATED R4TM ERROR-AMPLIFIER
CONFIGURATION
R4TM LOOP GAIN (dB)
L/C DOUBLE-POLE
p1
SYSTEM HAS 2 POLES
Unlike the standard DC/DC buck regulator, the synchronous
rectifier can sink current from the output filter inductor during
DCM, reducing the light-load efficiency with unnecessary
conduction loss as the low-side MOSFET sinks the inductor
current. The ISL95872 controller avoids the DCM conduction loss
by making the low-side MOSFET emulate the current-blocking
behavior of a diode. This smart-diode operation called diode-
emulation-mode (DEM) is triggered when the negative inductor
p2
AND 1 ZERO
NO COMPENSATOR IS
NEEDED
CURRENT-MODE
ZERO
z1
f (Hz)
current produces a positive voltage drop across the r
of the
DS(ON)
low-side MOSFET for eight consecutive PWM cycles while the
LGATE pin is high. The converter will exit DEM on the next PWM
FIGURE 11. UNCOMPENSATED R4TM OPEN-LOOP RESPONSE
pulse after detecting a negative voltage across the r
low-side MOSFET.
of the
DS(ON)
Transient Response
In addition to requiring a compensation zero, the integrator in
traditional architectures also slows system response to transient
conditions. The change in COMP voltage is slow in response to a
rapid change in output voltage. If the integrating capacitor is
It is characteristic of the R4™ architecture for the PWM switching
frequency to decrease while in DCM, increasing efficiency by
reducing unnecessary gate-driver switching losses. The extent of
the frequency reduction is proportional to the reduction of load
current. Upon entering DEM, the PWM frequency is forced to fall
approximately 30% by forcing a similar increase of the window
removed, COMP moves as quickly as V , and the modulator
OUT
immediately increases or decreases switching frequency to
recover the output voltage.
voltage V . This measure is taken to prevent oscillating between
W
modes at the boundary between CCM and DCM. The 30%
I
OUT
increase of V is removed upon exit of DEM, forcing the PWM
W
t
t
R4TM
switching frequency to jump back to the nominal CCM value.
R3TM
Overcurrent
The overcurrent protection (OCP) setpoint is programmed with
V
COMP
resistor R
, which is connected across the OCSET and
OCSET
PHASE pins. Resistor R is connected between the VO pin and
the actual output voltage of the converter. During normal
O
V
OUT
operation, the VO pin is a high impedance path, therefore there is
no voltage drop across R . The value of resistor R should always
O
O
t
match the value of resistor R
.
OCSET
FIGURE 12. R3TM vs R4TM IDEALIZED TRANSIENT RESPONSE
FN7974 Rev 0.00
January 26, 2012
Page 10 of 17
ISL95872
L
L
------------------------------------------
=
C
DCR
(EQ. 8)
V
SEN
I
O
R
DCR
L
OCSET
PHASE
_
V
+
DCR
For example, if L is 1.5µH, DCR is 4.5m, and R
OCSET
is 9kthe
C
SEN
choice of C
= 1.5µH/(9kx 4.5m) = 0.037µF
R
OCSET
SEN
C
O
When an OCP fault is declared, the converter will be latched off
and the PGOOD pin will be asserted low. The fault will remain
latched until the EN pin has been pulled below the falling EN
_
8.5µA
V
+
ROCSET
OCSET
R
O
threshold voltage V
or if VCC has decayed below the falling
ENTHF
VO
V
POR threshold voltage
.
VCC_THF
Undervoltage
The UVP fault detection circuit triggers after the FB pin voltage is
below the undervoltage threshold V for more than 2µs. For
FIGURE 13. OVERCURRENT PROGRAMMING CIRCUIT
UVTH
example if the converter is programmed to regulate 1.0V at the FB
Figure 13 shows the overcurrent set circuit. The inductor consists
of inductance L and the DC resistance DCR. The inductor DC
pin, that voltage would have to fall below the typical V
UVTH
threshold of 84% for more than 2µs in order to trip the UVP fault
latch. In numerical terms, that would be 84% x 1.0V = 0.84V.
When a UVP fault is declared, the converter will be latched off and
the PGOOD pin will be asserted low. The fault will remain latched
until the EN pin has been pulled below the falling EN threshold
current I creates a voltage drop across DCR, which is given by
Equation 4:
L
(EQ. 4)
V
= I DCR
L
DCR
voltage V
threshold voltage
or if VCC has decayed below the falling POR
The I
current source sinks 8.5µA into the OCSET pin,
ENTHF
OCSET
V
.
creating a DC voltage drop across the resistor R
, which is
VCC_THF
OCSET
given by Equation 5:
Over-Temperature
(EQ. 5)
V
= 8.5A R
OCSET
ROCSET
When the temperature of the IC increases above the rising threshold
temperature T , it will enter the OTP state that suspends the
OTRTH
The DC voltage difference between the OCSET pin and the VO pin,
which is given by Equation 6:
PWM, forcing the LGATE and UGATE gate-driver outputs low. The
status of the PGOOD pin does not change nor does the converter
latch-off. The PWM remains suspended until the IC temperature
V
– V
= V
– V
=I DCR – I
R
OCSET OCSET
OCSET
VO
DCR
ROCSET
L
falls below the hysteresis temperature T
at which time normal
OTHYS
PWM operation resumes. The OTP state can be reset if the EN pin is
pulled below the falling EN threshold voltage V or if VCC has
(EQ. 6)
ENTHF
V
The IC monitors the voltage of the OCSET pin and the VO pin.
When the voltage of the OCSET pin is higher than the voltage of
the VO pin for more than 10µs, an OCP fault latches the
converter off.
decayed below the falling POR threshold voltage
. All other
VCC_THF
protection circuits remain functional while the IC is in the OTP state.
It is likely that the IC will detect an UVP fault because in the absence
of PWM, the output voltage decays below the undervoltage
threshold V
.
UVTH
The value of R
written as:
is calculated with Equation 7, which is
OCSET
PGOOD Monitor
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an undefined
impedance if the VCC pin has not reached the rising POR threshold
I
DCR
(EQ. 7)
OC
---------------------------
R
=
OCSET
I
OCSET
Where:
- R
V
, or if the VCC pin is below the falling POR threshold
VCC_THR
() is the resistor used to program the overcurrent
V . If there is a fault condition of output overcurrent or
VCC_THF
OCSET
setpoint
undervoltage, PGOOD is asserted low. The PGOOD pull-down
impedance is 50
- I is the output DC load current that will activate the OCP
OC
fault detection circuit
Unlike the ISL95870, the ISL95872 does not feature overvoltage
protection and PGOOD remains high during an overvoltage event.
- DCR is the inductor DC resistance
For example, if I is 20A and DCR is 4.5m, the choice of
OC
R
is equal to 20A x 4.5m/8.5µA = 10.5k
Integrated MOSFET Gate-Drivers
OCSET
The LGATE pin and UGATE pins are MOSFET driver outputs. The
LGATE pin drives the low-side MOSFET of the converter while the
UGATE pin drives the high-side MOSFET of the converter.
Resistor R
and capacitor C
SEN
form an R-C network to
OCSET
sense the inductor current. To sense the inductor current
correctly not only in DC operation, but also during dynamic
operation, the R-C network time constant R
match the inductor time constant L/DCR. The value of C
then written as Equation 8:
C
needs to
is
OCSET SEN
The LGATE driver is optimized for low duty-cycle applications
where the low-side MOSFET experiences long conduction times.
In this environment, the low-side MOSFETs require exceptionally
SEN
low r
and tend to have large parasitic charges that conduct
DS(ON)
FN7974 Rev 0.00
January 26, 2012
Page 11 of 17
ISL95872
transient currents within the devices in response to high dv/dt
switching present at the phase node. The drain-gate charge in
particular can conduct sufficient current through the driver pull-
General Application Design
Guide
This design guide is intended to provide a high-level explanation of
the steps necessary to design a single-phase buck converter. It is
assumed that the reader is familiar with many of the basic skills
and techniques referenced in the following. In addition to this
guide, Intersil provides complete reference designs that include
schematics, bill of materials, and example board layouts.
down resistance that the V
of the device can be exceeded
GS(th)
and turned on. For this reason, the LGATE driver has been
designed with low pull-down resistance and high sink current
capability to ensure clamping the MOSFETs gate voltage below
V
.
GS(th)
Adaptive Shoot-Through Protection
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is expressed in
Equation 9:
Adaptive shoot-through protection prevents a gate-driver output
from turning on until the opposite gate-driver output has fallen
below approximately 1V. The dead-time shown in Figure 14 is
extended by the additional period that the falling gate voltage
remains above the 1V threshold. The high-side gate-driver output
voltage is measured across the UGATE and PHASE pins while the
low-side gate-driver output voltage is measured across the LGATE
and PGND pins. The power for the LGATE gate-driver is sourced
directly from the PVCC pin. The power for the UGATE gate-driver is
supplied by a boot-strap capacitor connected across the BOOT
and PHASE pins. The capacitor is charged each time the phase
node voltage falls a diode drop below PVCC such as when the
low-side MOSFET is turned on.
V
O
(EQ. 9)
---------
D =
V
IN
The output inductor peak-to-peak ripple current is expressed in
Equation 10:
V
1 – D
O
F
------------------------------
=
I
P-P
(EQ. 10)
L
SW
A typical step-down DC/DC converter will have an I of 20% to
PP
40% of the maximum DC output load current. The value of I
is
P-P
selected based upon several criteria such as MOSFET switching
loss, inductor core loss, and the resistive loss of the inductor
winding. The DC copper loss of the inductor can be estimated
using Equation 11:
UGATE
2
(EQ. 11)
1V
1V
1V
1V
P
= I
DCR
COPPER
LOAD
Where, I
is the converter output DC current.
LOAD
The copper loss can be significant so attention has to be given to
the DCR of the inductor. Another factor to consider when
choosing the inductor is its saturation characteristics at elevated
temperature. A saturated inductor could cause destruction of
circuit components, as well as nuisance OCP faults.
LGATE
A DC/DC buck regulator must have output capacitance C into
O
which ripple current I
can flow. Current I
develops a
across C which is the sum of
FIGURE 14. GATE DRIVE ADAPTIVE SHOOT-THROUGH PROTECTION
P-P
corresponding ripple voltage V
P-P
P-P
O,
the voltage drop across the capacitor ESR and of the voltage
change stemming from charge moved in and out of the
capacitor. These two voltages are expressed in Equations 12
and 13:
(EQ. 12)
V
= I
ESR
ESR
P-P
I
P-P
---------------------------------
(EQ. 13)
V
=
C
8 C F
O
SW
FN7974 Rev 0.00
January 26, 2012
Page 12 of 17
ISL95872
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled to
In addition to the bulk capacitors, some low ESL ceramic
capacitors are recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side MOSFET.
reduce the total ESR until the required V is achieved. The
P-P
inductance of the capacitor can significantly impact the output
voltage ripple and cause a brief voltage spike if the load transient
has an extremely high slew rate. Low inductance capacitors should
be considered. A capacitor dissipates heat as a function of RMS
Selecting the Bootstrap Capacitor
The integrated driver features an internal bootstrap schottky
diode. Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
capacitor voltage rating is selected to be at least 10V. Although the
current and frequency. Be sure that I
is shared by a sufficient
quantity of paralleled capacitors so that they operate below the
P-P
maximum rated RMS current at F . Take into account that the
SW
theoretical maximum voltage of the capacitor is PVCC-V
DIODE
rated value of a capacitor can fade as much as 50% as the DC
voltage across it increases.
(voltage drop across the boot diode), large excursions below
ground by the phase node requires at least a 10V rating for the
bootstrap capacitor. The bootstrap capacitor can be chosen from
Equation 16:
Selecting the Input Capacitor
0.6
Q
GATE
-----------------------
C
(EQ. 16)
BOOT
V
BOOT
0.5
x = 0
0.4
0.3
Where:
x = 0.5
- Q
is the amount of gate charge required to fully charge
GATE
the gate of the upper MOSFET
0.2
- V
is the maximum decay across the BOOT capacitor
BOOT
x = 1
0.1
0
As an example, suppose the high-side MOSFET has a total gate
charge Q , of 25nC at V = 5V, and a V
of 200mV. The
g
GS BOOT
calculated bootstrap capacitance is 0.125µF; for a comfortable
margin, select a capacitor that is double the calculated
capacitance. In this example, 0.22µF will suffice. Use a low
temperature-coefficient ceramic capacitor.
0
0.1 0.2
0.3 0.4 0.5 0.6 0.7
DUTY CYCLE
0.8 0.9
1.0
FIGURE 15. NORMALIZED INPUT RMS CURRENT FOR EFF = 1
Driver Power Dissipation
The important parameters for the bulk input capacitors are the
voltage rating and the RMS current rating. For reliable operation,
select bulk capacitors with voltage and current ratings above the
maximum input voltage and capable of supplying the RMS
current required by the switching circuit. Their voltage rating
should be at least 1.25x greater than the maximum input
voltage, while a voltage rating of 1.5x is a preferred rating.
Figure 15 is a graph of the input RMS ripple current, normalized
relative to output load current, as a function of duty cycle that is
adjusted for converter efficiency. The ripple current calculation is
written as Equation 14:
Switching power dissipation in the driver is mainly a function of
the switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for a
desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level will
push the IC beyond the maximum recommended operating
junction temperature of +125°C. When designing the
application, it is recommended that the following calculation be
performed to ensure safe operation at the desired frequency for
the selected MOSFETs. The power dissipated by the drivers is
approximated as Equation 17:
2
2
2
2
D
12
------
I
D – D + x I
(EQ. 17)
MAX
MAX
(EQ. 14)
P = F 1.5V
Q + V Q + P + P
L L U
U L
sw
U
--------------------------------------------------------------------------------------------------------
I
=
IN_RMS
I
MAX
Where:
Where:
- I
- F is the switching frequency of the PWM signal
sw
- V is the upper gate driver bias supply voltage
U
is the maximum continuous I
LOAD
of the converter
MAX
- x is a multiplier (0 to 1) corresponding to the inductor peak-
- V is the lower gate driver bias supply voltage
L
to-peak ripple amplitude expressed as a percentage of I
MAX
(0% to 100%)
- Q is the charge to be delivered by the upper driver into the
U
gate of the MOSFET and discrete capacitors
- D is the duty cycle that is adjusted to take into account the
efficiency of the converter
- Q is the charge to be delivered by the lower driver into the
L
gate of the MOSFET and discrete capacitors
Duty cycle is written as Equation 15:
- P is the quiescent power consumption of the lower driver
L
V
O
--------------------------
(EQ. 15)
D =
- P is the quiescent power consumption of the upper driver
U
V
EFF
IN
FN7974 Rev 0.00
January 26, 2012
Page 13 of 17
ISL95872
Where:
- I
1000
Q
=100nC
Q =50nC
U
U
Q
=50nC
U
Q =100nC
Q =200nC
900
800
700
600
500
400
300
200
100
0
L
is the difference of the DC component of the
VALLEY
L
Q =50nC
L
inductor current minus 1/2 of the inductor ripple current
- I is the sum of the DC component of the inductor
PEAK
current plus 1/2 of the inductor ripple current
- t is the time required to drive the device into saturation
ON
- t
OFF
Q
=20nC
U
Q =50nC
is the time required to drive the device into cut-off
L
Layout Considerations
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board. The ground-plane
layer should be adjacent to the signal layer to provide shielding.
The ground plane layer should have an island located under the
IC, the components connected to analog or logic signals. The
island should be connected to the rest of the ground plane layer
at one quiet point.
0
200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
FREQUENCY (Hz)
FIGURE 16. POWER DISSIPATION vs FREQUENCY
There are two sets of components in a DC/DC converter, the
power components and the small signal components. The power
components are the most critical because they switch large
amount of energy. The small signal components connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
MOSFET Selection and Considerations
The choice of MOSFETs depends on the current each MOSFET will
be required to conduct, the switching frequency, the capability of
the MOSFETs to dissipate heat, and the availability and nature of
heat sinking and air flow.
Typically, a MOSFET cannot tolerate even brief excursions beyond
their maximum drain to source voltage rating. The MOSFETs used
The power components should be placed first and these include
MOSFETs, input and output capacitors, and the inductor. Keeping
the distance between the power train and the control IC short
helps keep the gate drive traces short. These drive signals
include the LGATE, UGATE, PGND, PHASE and BOOT.
in the power stage of the converter should have a maximum V
DS
rating that exceeds the sum of the upper voltage tolerance of the
input power source and the voltage spike that occurs when the
MOSFETs switch.
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible. See Figure 17. Input high frequency
capacitors should be placed close to the drain of the upper
MOSFETs and the source of the lower MOSFETs. Place the output
inductor and output capacitors between the MOSFETs and the
load. High frequency output decoupling capacitors (ceramic)
should be placed as close as possible to the decoupling target,
making use of the shortest connection paths to any internal
planes. Place the components in such a way that the area under
the IC has less noise traces with high dV/dt and di/dt, such as
gate signals and phase node signals.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred high-
side MOSFET emphasizes low gate charge so that the device
spends the least amount of time dissipating power in the linear
region. The preferred low-side MOSFET emphasizes low r
DS(ON)
when fully saturated to minimize conduction loss.
For the low-side MOSFET, (LS), the power loss can be assumed to
be conductive only and is written as Equation 18:
2
(EQ. 18)
P
I
r
1 – D
DSON_LS
CON_LS
LOAD
For the high-side MOSFET, (HS), its conduction loss is written as
Equation 19:
GND
VIAS TO
GROUND
PLANE
OUTPUT
CAPACITORS
2
(EQ. 19)
P
= I
r
D
DSON_HS
CON_HS
LOAD
SCHOTTKY
DIODE
VOU
For the high-side MOSFET, its switching loss is written as Equation
20:
PHASE
LOW-SIDE
MOSFETS
INDUCTOR
NODE
HIGH-SIDE
MOSFETS
INPUT
V
I
t
F
V
I
t
F
IN PEAK OFF
SW
IN VALLEY ON
CAPACITORS
SW
VIN
--------------------------------------------------------------------- -----------------------------------------------------------------
P
=
+
SW_HS
2
2
FIGURE 17. TYPICAL POWER COMPONENT PLACEMENT
(EQ. 20)
FN7974 Rev 0.00
January 26, 2012
Page 14 of 17
ISL95872
VCC AND PVCC PINS
Place the decoupling capacitors as close as practical to the IC. In
particular, the PVCC decoupling capacitor should have a very
short and wide connection to the PGND pin. The VCC decoupling
capacitor should be referenced to GND pin.
EN AND PGOOD PINS
These are logic signals that are referenced to the GND pin. Treat
as a typical logic signal.
OCSET AND VO PINS
The current-sensing network consisting of R
, R , and C
SEN
OCSET
O
needs to be connected to the inductor pads for accurate
measurement of the DCR voltage drop. These components
however, should be located physically close to the OCSET and VO
pins with traces leading back to the inductor. It is critical that the
traces are shielded by the ground plane layer all the way to the
inductor pads. The procedure is the same for resistive current
sense.
FB, SREF, REFIN, AND RTN PINS
The input impedance of these pins is high, making it critical to
place the components connected to these pins as close as
possible to the IC.
LGATE, PGND, UGATE, BOOT, AND PHASE PINS
The signals going through these traces are high dv/dt and high
di/dt, with high peak charging and discharging current. The
PGND pin can only flow current from the gate-source charge of
the low-side MOSFETs when LGATE goes low. Ideally, route the
trace from the LGATE pin in parallel with the trace from the PGND
pin, route the trace from the UGATE pin in parallel with the trace
from the PHASE pin. In order to have more accurate zero-crossing
detection of inductor current, it is recommended to connect
Phase pin to the drain of the low-side MOSFETs with Kelvin
connection. These pairs of traces should be short, wide, and
away from other traces with high input impedance; weak signal
traces should not be in proximity with these traces on any layer.
FN7974 Rev 0.00
January 26, 2012
Page 15 of 17
ISL95872
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN7974.0
CHANGE
January 26, 2012
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
© Copyright Intersil Americas LLC 2012. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7974 Rev 0.00
January 26, 2012
Page 16 of 17
ISL95872
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
L16.2.6x1.8A
D
A
B
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
6
INDEX AREA
SYMBOL
MIN
0.45
NOMINAL
MAX
0.55
NOTES
N
E
A
A1
A3
b
0.50
-
2X
0.10 C
1 2
-
-
0.05
-
2X
0.10 C
0.127 REF
-
TOP VIEW
0.15
2.55
1.75
0.20
0.25
2.65
1.85
5
D
2.60
-
0.10 C
E
1.80
-
C
A
0.05 C
SEATING PLANE
e
0.40 BSC
-
K
0.15
0.35
0.45
-
0.40
0.50
16
4
-
0.45
0.55
-
A1
L
-
SIDE VIEW
L1
N
-
2
e
Nd
Ne
3
PIN #1 ID
L1
K
1 2
4
3
NX L
0
-
12
4
5
NX b
16X
Rev. 5 2/09
(DATUM B)
(DATUM A)
NOTES:
0.10 M C A B
0.05 M C
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
BOTTOM VIEW
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
C
L
(A1)
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX (b)
5
L
e
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
SECTION "C-C"
TERMINAL TIP
C C
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
3.00
1.80
1.40
0.90
1.40
2.20
0.40
0.20
0.40
0.20
0.50
10
LAND PATTERN
FN7974 Rev 0.00
January 26, 2012
Page 17 of 17
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