ISL5927_技术文档

ISL5927

®

Data Sheet

May 2004

FN6084

Dual 14-Bit, +3.3V, 260+MSPS, High Speed

D/A Converter

Features

• Low Power . . . . . 233mW with 20mA Output at 130MSPS

• Adjustable Full Scale Output Current. . . . . 2mA to 20mA

• Guaranteed Gain Matching < 0.14dB

The ISL5927 is a dual 14-bit, 260+MSPS (Mega Samples

Per Second), CMOS, high speed, low power, D/A (digital to

analog) converter, designed specifically for use in high

performance communication systems such as base

transceiver stations utilizing 2.5G or 3G cellular protocols.

.

• +3.3V Power Supply

• 3V LVCMOS Compatible Inputs

• Excellent Spurious Free Dynamic Range

Ordering Information

(75dBc to Nyquist, f = 130MSPS, f

= 10MHz)

S

OUT

TEMP.

RANGE

(°C)

• UMTS Adjacent Channel Power = 71dB at 19.2MHz

• EDGE/GSM SFDR = 94dBc at 11MHz in 20MHz Window

• Dual, 3.3V, Lower Power Replacement for AD9767

PART

NUMBER

PKG.

DWG. #

CLOCK

SPEED

PACKAGE

ISL5927IN

-40 to 85 48 Ld LQFP Q48.7x7A 260MHz

ISL5927EVAL1

25

Evaluation Platform

260MHz

Applications

Pinout

• Cellular Infrastructure - Single or Multi-Carrier: IS-136,

IS-95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA

ISL5927

(LQFP)

• BWA Infrastructure

TOP VIEW

• Quadrature Transmit with IF Range 0–80MHz

• Medical/Test Instrumentation and Equipment

• Wireless Communication Systems

48 47 46 45 44 43 42 41 40 39 38 37

36

QD6

QD7

QD8

1

ID7

35

34

33

32

31

ID6

ID5

ID4

2

3

QD9

4

5

QD10

QD11

ID3

ID2

ID1

6

7

QD12

30

29

28

27

26

25

QD13 (MSB)

CLK

(LSB) ID0

SLEEP

8

9

DGND

AGND

QCOMP

D

10

VDD

AGND

11

12

ICOMP

13 14 15 16 17 18 19 20 21 22 23 24

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL5927

Typical Applications Circuit

48 47 46 45 44 43 42 41 40 39 3837

36

QD6

QD7

QD8

QD9

QD10

QD11

QD12

QD13 (MSB)

ID7

ID6

ID5

ID4

ID3

ID2

1

35

34

33

32

31

2

3

4

5

6

7

8

9

30

29

ID1

ID0 (LSB)

SLEEP

CLK 28

27

26

25

DGND

AGND

R

1

DV

PP

10

11

12

D

VDD

AGND

50Ω

ICOMP

QCOMP

C

1

13 14 15 16 17 18 19 20 21 22 23 24

0.1µF

C

3

2

0.1µF

A

VDD

C

AV

PP

4

C

5

0.1µF

C

0.1µF

6

R

SET

1.91kΩ

50Ω

R

3

2

1:1 TRANSFORMER

REPRESENTS

ANY 50Ω LOAD

(50Ω)

IOUT

(50Ω)

QOUT

BEAD

FERRITE

DV

PP

(DIGITAL POWER PLANE) = +3.3V

L

C

10µF

1

+

C

0.1µF

11

10

1µF

9

10µH

+3.3V POWER SOURCE

FERRITE

BEAD

AV (ANALOG POWER PLANE) = +3.3V

PP

L

2

10µH

C

14

C

12

0.1µF

13

1µF

10µF

2

ISL5927

Functional Block Diagram

(LSB) QD0

QD1

QOUTA

QOUTB

QD2

INPUT

LATCH

QD3

QD4

CASCODE

QD5

CURRENT

SOURCE

SWITCH

40

QD6

QD7

QD8

MATRIX

9 LSBs

QD9

QD10

+

31 MSB

UPPER

5-BIT

SEGMENTS

QD11

QD12

DECODER

(MSB) QD13

QCOMP

SLEEP

FSADJ

INT/EXT

BIAS

GENERATION

CLK

VOLTAGE

REFIO

REFERENCE

REFLO

ICOMP

(LSB) ID0

ID1

IOUTA

IOUTB

ID2

INPUT

LATCH

ID3

ID4

CASCODE

ID5

SWITCH

MATRIX

CURRENT

SOURCE

40

ID6

ID7

ID8

9 LSBs

+

ID9

ID10

31 MSB

SEGMENTS

UPPER

5-BIT

ID11

ID12

DECODER

(MSB) ID13

3

ISL5927

Pin Des criptions

PIN NO.

11, 19, 26

13, 24

28

PIN NAME

PIN DESCRIPTION

AGND

Analog ground.

A

Analog supply (+2.7V to +3.6V).

Clock Input.

VDD

CLK

27

DGND

Connect to digital ground.

Digital supply (+2.7V to +3.6V).

10

D

VDD

20

FSADJ

Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output

current = 32 x V /R

.

FSADJ SET

14, 23

12, 25

NC

Not internally connected. Recommend no connect.

ICOMP, QCOMP

Compensation pin for internal bias generation. Each pin should be individually decoupled to AGND with

a 0.1µF capacitor.

1-8, 29-48

15, 22

ID13-ID0, QD13-QD0 Digital data input ports. Bit 13 is most significant bit (MSB) and bit 0 is the least significant bit (LSB).

IOUTA, QOUTA

IOUTB, QOUTB

Current outputs of the device. Full scale output current is achieved when all input bits are set to binary 1.

16, 21

Complementary current outputs of the device. Full scale output current is achieved on the complementary

outputs when all input bits are set to binary 0.

17

REFIO

Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an

external load. Use 0.1µF cap to ground when internal reference is enabled.

18

9

REFLO

SLEEP

Connect to analog ground to enable internal 1.2V reference or connect to AV

to disable internal reference.

DD

Connect to digital ground or leave floating for normal operation. Connect to DV

DD

for sleep mode.

4

ISL5927

Absolute Maximum Ratings

Thermal Information

Digital Supply Voltage DV

to DGND . . . . . . . . . . . . . . . . . +3.6V

to AGND. . . . . . . . . . . . . . . . . . +3.6V

Thermal Resistance (Typical, Note 1)

θ

(°C/W)

70

DD

Analog Supply Voltage AV

JA

DD

LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V

Digital Input Voltages (DATA, CLK, SLEEP) . . . . . . . . DV

Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

+ 0.3V

DD

Analog Output Current (I

) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA

OUT

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

JA

Electrical Specifications AV = DV = +3.3V, V

= Internal 1.2V, IOUTFS = 20mA, T = 25°C for All Typical Values

A

DD

REF

T

= -40°C TO 85°C

A

PARAMETER

SYSTEM PERFORMANCE

Resolution

TEST CONDITIONS

MIN

TYP

MAX

UNITS

14

-5

-

Bits

LSB

Integral Linearity Error, INL

Differential Linearity Error, DNL

“Best Fit” Straight Line (Note 8)

(Note 8)

±2.5

±1.5

+5

+3

-3

Offset Error, I

IOUTA (Note 8)

(Note 8)

-0.006

-

+0.006 % FSR

OS

Offset Drift Coefficient

0.1

-

ppm

FSR/°C

Full Scale Gain Error, FSE

With External Reference (Notes 2, 8)

With Internal Reference (Notes 2, 8)

With External Reference (Note 8)

-3

-

±0.5

±50

+3

-

% FSR

Full Scale Gain Drift

Crosstalk

ppm

FSR/°C

With Internal Reference (Note 8)

-

±100

-

ppm

FSR/°C

f

= 100MSPS, f

= 260MSPS, f

= 10MHz

= 40MHz

= 40.4MHz

-

83

74

73

0.6

0.05

20

-

dB

CLK

OUT

f

CLK

f

-

dB

CLK

Gain Matching Between Channels

(DC Measurement)

As a percentage of Full Scale Range

In dB Full Scale Range

-1.6

-0.14

2

+1.6

+0.14

22

% FSR

dB FSR

mA

Full Scale Output Current, I

FS

Output Voltage Compliance Range

(Note 3)

-1.0

1.25

V

DYNAMIC CHARACTERISTICS

Maximum Clock Rate, f

Output Rise Time

Output Fall Time

Output Capacitance

Output Noise

ISL5927IN

260

300

1

-

MHz

ns

CLK

Full Scale Step

-

1

ns

5

pF

IOUTFS = 20mA

IOUTFS = 2mA

50

30

pA/√Hz

5

ISL5927

Electrical Specifications AV = DV = +3.3V, V

= Internal 1.2V, IOUTFS = 20mA, T = 25°C for All Typical Values (Continued)

DD

REF

A

T

= -40°C TO 85°C

A

PARAMETER

AC CHARACTERISTICS (Using Figure 13 with R

TEST CONDITIONS

MIN

TYP

MAX

UNITS

= 50Ω and R

= 50Ω, Full Scale Output = -2.5dBm)

DIFF

LOAD

Spurious Free Dynamic Range,

SFDR Within a Window

f

= 210MSPS, f

= 130MSPS, f

= 260MSPS, f

= 210MSPS, f

= 200MSPS, f

= 130MSPS, f

= 100MSPS, f

= 80.8MHz, 30MHz Span (Notes 4, 8)

-

73

80

86

56

63

68

56

67

68

-

dBc

CLK

OUT

f

= 40.4MHz, 30MHz Span (Notes 4, 8)

= 20.2MHz, 20MHz Span (Notes 4, 8)

= 80.8MHz (Notes 4, 8)

CLK

f

-

CLK

Spurious Free Dynamic Range,

f

-

CLK

SFDR to Nyquist (f

/2)

CLK

f

= 40.4MHz (Notes 4, 8)

-

CLK

f

= 20.2MHz (Notes 4, 8)

-

CLK

f

= 80.8MHz (Notes 4, 8)

-

CLK

f

= 40.4MHz (Notes 4, 8, 10)

= 20.2MHz, T = 25°C (Notes 4, 8)

= 20.2MHz, T = -40°C to 85°C (Notes 4, 8)

= 50.5MHz (Notes 4, 8)

-

CLK

f

62

60

-

CLK

f

CLK

f

59

63

70

75

79

61

64

71

75

78

68

75

79

65

CLK

f

= 40.4MHz (Notes 4, 8)

-

CLK

f

= 20.2MHz (Notes 4, 8)

-

CLK

f

= 10.1MHz , T = -40°C to 85°C (Notes 4, 8)

= 5.05MHz, (Notes 4, 8)

70

-

CLK

f

CLK

f

= 40.4MHz (Notes 4, 8)

-

CLK

f

= 80MSPS, f

= 50MSPS, f

= 30.3MHz (Notes 4, 8)

= 20.2MHz (Notes 4, 8)

= 10.1MHz (Notes 4, 8, 10)

= 5.05MHz (Notes 4, 8)

= 20.2MHz (Notes 4, 8)

= 10.1MHz (Notes 4, 8)

= 5.05MHz (Notes 4, 8)

-

CLK

OUT

f

-

CLK

f

-

CLK

f

-

CLK

f

-

CLK

f

-

CLK

f

-

CLK

Spurious Free Dynamic Range,

f

= 210MSPS, f

OUT

= 28.3MHz to 45.2MHz, 2.1MHz Spacing,

-

CLK

SFDR in a Window with Eight Tones

50MHz Span (Notes 4, 8, 10)

f

= 130MSPS, f = 17.5MHz to 27.9MHz, 1.3MHz Spacing,

-

69

76

77

94

71

-

dBc

dB

CLK

OUT

35MHz Span (Notes 4, 8)

f

= 80MSPS, f

= 10.8MHz to 17.2MHz, 811kHz Spacing,

CLK

OUT

15MHz Span (Notes 4, 8)

f

= 50MSPS, f

= 6.7MHz to 10.8MHz, 490kHz Spacing,

CLK

OUT

10MHz Span (Notes 4, 8)

Spurious Free Dynamic Range,

f

= 78MSPS, f = 11MHz, in a 20MHz Window, RBW = 30kHz

CLK

OUT

SFDR in a Window with EDGE or GSM (Notes 4, 8, 10)

Adjacent Channel Power Ratio,

ACPR with UMTS

f

= 76.8MSPS, f = 19.2MHz, RBW = 30kHz (Notes 4, 8, 10)

OUT

CLK

VOLTAGE REFERENCE

Internal Reference Voltage, V

Pin 20 Voltage with Internal Reference

1.2

1.23

±40

0

1.3

V

ppm/°C

µA

FSADJ

Internal Reference Voltage Drift

-

Internal Reference Output Current

Sink/Source Capability

Reference is not intended to drive an external load

Reference Input Impedance

-

1

-

MΩ

Reference Input Multiplying Bandwidth (Note 8)

1.0

MHz

6

ISL5927

Electrical Specifications AV = DV = +3.3V, V

= Internal 1.2V, IOUTFS = 20mA, T = 25°C for All Typical Values (Continued)

DD

REF

A

T

= -40°C TO 85°C

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUTS D13-D0, CLK

Input Logic High Voltage with

(Note 3)

2.3

-

3.3

0

-

V

3.3V Supply, V

IH

Input Logic Low Voltage with

3.3V Supply, V

(Note 3)

1.0

IL

Sleep Input Current, I

-25

-20

-10

-

+25

+20

+10

-

µA

pF

IH

Input Logic Current, I

IH, IL

Clock Input Current, I

IH, IL

-

Digital Input Capacitance, C

3

IN

TIMING CHARACTERISTICS

Data Setup Time, t

See Figure 15

-

1.5

1

-

ns

SU

Data Hold Time, t

HLD

Propagation Delay Time, t

PD

Clock

Period

CLK Pulse Width, t

, t

PW1 PW2

See Figure 15 (Note 3)

0.9

-

ns

POWER SUPPLY CHARACTERISTICS

AV

DV

Power Supply

(Note 9)

2.7

3.3

60

3.6

62

-

V

DD

(Note 9)

2.7

V

DD

Analog Supply Current (I

AVDD

)

3.3V, IOUTFS = 20mA

3.3V, IOUTFS = 2mA

3.3V (Note 5)

3.3V (Note 6)

-

mA

mW

-

24

Digital Supply Current (I

)

-

11

15

21

-

DVDD

-

17

Supply Current (I

) Sleep Mode

3.3V, IOUTFS = Don’t Care

3.3V, IOUTFS = 20mA (Note 5)

3.3V, IOUTFS = 20mA (Note 6)

3.3V, IOUTFS = 20mA (Note 7)

3.3V, IOUTFS = 2mA (Note 5)

Single Supply (Note 8)

-

5

AVDD

Power Dissipation

-

233

253

275

115

-

255

274

-

Power Supply Rejection

NOTES:

-0.125

+0.125 %FSR/V

2. Gain Error measured as the error in the ratio between the full scale output current and the current through R

ratio should be 32.

(typically 625µA). Ideally the

SET

3. Parameter guaranteed by design or characterization and not production tested.

4. Spectral measurements made with differential transformer coupled output and no external filtering. For multitone testing, the same pattern was

used at different clock rates, producing different output frequencies but at the same ratio to the clock rate.

5. Measured with the clock at 130MSPS and the output frequency at 10MHz.

6. Measured with the clock at 200MSPS and the output frequency at 20MHz.

7. Measured with the clock at 260MSPS and the output frequency at 40.4MHz.

8. See “Definition of Specifications.”

9. Recommended operation is from 3.0V to 3.6V. Operation below 3.0V is possible with some degradation in spectral performance. Reduction in

analog output current may be necessary to maintain spectral performance.

10. See Typical Performance Plots.

7

ISL5927

Typical Performance (+3.3V Supply, Using Figure 13 with R

= 100Ω and R

= 50Ω)

LOAD

DIFF

SPECTRAL MASK FOR

GSM900/DCS1800/PCS1900

P>43dBm NORMAL BTS

WITH 30kHz RBW

FIGURE 1. EDGE AT 11MHz, 78MSPS CLOCK

FIGURE 2. EDGE AT 11MHz, 78MSPS CLOCK

(77dBc -NYQUIST, 6dB PAD)

(94+dBc @ ∆f = +6MHz)

SPECTRAL MASK FOR

GSM900/DCS1800/PCS1900

P>43dBm NORMAL BTS

WITH 30kHz RBW

FIGURE 3. GSM AT 11MHz, 78MSPS CLOCK

FIGURE 4. GSM AT 11MHz, 78MSPS CLOCK

(79dBc - NYQUIST, 9dB PAD)

(94+dBc @ ∆f = +6MHz, 3dB PAD)

FIGURE 5. FOUR EDGE CARRIERS AT 12.4–15.6MHz,

800kHz SPACING, 78MSPS (75+dBc - 20MHz

WINDOW)

FIGURE 6. FOUR GSM CARRIERS AT 12.4–15.6MHz,

78MSPS (75+dBc - 20MHz WINDOW, 6dB PAD)

8

ISL5927

Typical Performance (+3.3V Supply, Using Figure 13 with R

= 100Ω and R

= 50Ω) (Continued)

LOAD

DIFF

SPECTRAL MASK

UMTS TDD

P>43dBm BTS

FIGURE 7. UMTS AT 19.2MHz, 76.8MSPS (71dB 1st ACPR,

75dB 2nd ACPR)

FIGURE 8. ONE TONE AT 10.1MHz, 80MSPS CLOCK

(71dBc - NYQUIST, 6dB PAD)

FIGURE 9. ONE TONE AT 40.4MHz, 210MSPS CLOCK

(61dBc - NYQUIST, 6dB PAD)

FIGURE 10. EIGHT TONES (CREST FACTOR = 8.9) AT 37MHz,

210MSPS CLOCK, 2.1MHz SPACING

(65dBc - NYQUIST)

FIGURE 11. TWO TONES (CF = 6) AT 8.5MHz, 50MSPS

CLOCK, 500kHz SPACING (83dBc - 10MHz

WINDOW, 6dB PAD)

FIGURE 12. FOUR TONES (CF = 8.1) AT 14MHz, 80MSPS

CLOCK, 800kHz SPACING (70dBc - NYQUIST,

6dB PAD)

9

ISL5927

through a known resistance. Offset error is defined as the

maximum deviation of the IOUTA output current from a

value of 0mA.

Definition of Specifications

Adjacent Channel Power Ratio, ACPR, is the ratio of the

average power in the adjacent frequency channel (or offset)

to the average power in the transmitted frequency channel.

Output Voltage Compliance Range, is the voltage limit

imposed on the output. The output impedance should be

chosen such that the voltage developed does not violate the

compliance range.

Crosstalk, is the measure of the channel isolation from one

DAC to the other. It is measured by generating a sinewave in

one DAC while the other DAC is clocked with a static input,

and comparing the output power of each DAC at the

frequency generated.

Power Supply Rejection, is measured using a single power

supply. The nominal supply voltage is varied ±10% and the

change in the DAC full scale output is noted.

Differential Linearity Error, DNL, is the measure of the

step size output deviation from code to code. Ideally the step

size should be one LSB. A DNL specification of one LSB or

less guarantees monotonicity.

Reference Input Multiplying Bandwidth, is defined as the

3dB bandwidth of the voltage reference input. It is measured

by using a sinusoidal waveform as the external reference

with the digital inputs set to all 1s. The frequency is

increased until the amplitude of the output waveform is

0.707 (-3dB) of its original value.

EDGE, Enhanced Data for Global Evolution, a TDMA

standard for cellular applications which uses 200kHz BW,

8-PSK modulated carriers.

Spurious Free Dynamic Range, SFDR, is the amplitude

difference from the fundamental signal to the largest

harmonically or non-harmonically related spur within the

specified frequency window.

Full Scale Gain Drift, is measured by setting the data inputs

to be all logic high (all 1s) and measuring the output voltage

through a known resistance as the temperature is varied

from T

to T . It is defined as the maximum deviation

MIN

MAX

from the value measured at room temperature to the value

Total Harmonic Distortion, THD, is the ratio of the RMS

value of the fundamental output signal to the RMS sum of

the first five harmonic components.

measured at either T or T . The units are ppm of FSR

MIN

(full scale range) per °C.

MAX

Full Scale Gain Error, is the error from an ideal ratio of 32

between the output current and the full scale adjust current

UMTS, Universal Mobile Telecommunications System, a

W-CDMA standard for cellular applications which uses

3.84MHz modulated carriers.

(through R

SET

).

Gain Matching, is a measure of the full scale amplitude

match between the I and Q channels given the same input

pattern. It is typically measured with all 1s at the input to both

channels, and the full scale output voltage developed into

matching loads is compared for the I and Q outputs.

Detailed Des cription

The ISL5927 is a dual 14-bit, current out, CMOS, digital to

analog converter. The maximum update rate is at least

260+MSPS and can be powered by a single power supply in

the recommended range of +3.0V to +3.6V. It consumes

less than 125mW of power per channel when using a +3.3V

supply, the maximum 20mA of output current, and the data

switching at 210MSPS. The architecture is based on a

segmented current source arrangement that reduces glitch

by reducing the amount of current switching at any one time.

In previous architectures that contained all binary weighted

current sources or a binary weighted resistor ladder, the

converter might have a substantially larger amount of current

turning on and off at certain, worst-case transition points

such as midscale and quarter scale transitions. By greatly

reducing the amount of current switching at these major

transitions, the overall glitch of the converter is dramatically

reduced, improving settling time, transient problems, and

accuracy.

GSM, Global System for Mobile Communication, a TDMA

standard for cellular applications which uses 200kHz BW,

GMSK modulated carriers.

Integral Linearity Error, INL, is the measure of the worst

case point that deviates from a best fit straight line of data

values along the transfer curve.

Internal Reference Voltage Drift, is defined as the

maximum deviation from the value measured at room

temperature to the value measured at either T

or T .

MAX

MIN

The units are ppm per °C.

Offset Drift, is measured by setting the data inputs to all

logic low (all 0s) and measuring the output voltage at IOUTA

through a known resistance as the temperature is varied

from T

to T . It is defined as the maximum deviation

MIN

MAX

Digital Inputs and Termination

from the value measured at room temperature to the value

The ISL5927 digital inputs are formatted as offset binary and

guaranteed to 3V LVCMOS levels. The internal register is

updated on the rising edge of the clock. To minimize

reflections, proper termination should be implemented. If the

lines driving the clock and the digital inputs are long 50Ω

measured at either T or T . The units are ppm of FSR

(full scale range) per degree °C.

MIN

MAX

Offset Error, is measured by setting the data inputs to all

logic low (all 0s) and measuring the output voltage of IOUTA

10

ISL5927

lines, then 50Ω termination resistors should be placed as

close to the converter inputs as possible connected to the

digital ground plane (if separate grounds are used). These

termination resistors are not likely needed as long as the

digital waveform source is within a few inches of the DAC.

For pattern drivers with very high speed edge rates, it is

recommended that the user consider series termination (50-

200Ω) prior to the DAC’s inputs in order to reduce the

amount of noise.

If the full scale output current is set to 20mA by using the

internal voltage reference (1.23V) and a 1.91kΩ R

resistor, then the input coding to output current will resemble

SET

the following:

TABLE 1. INPUT CODING vs OUTPUT CURRENT WITH

INTERNAL REFERENCE (1.23V TYP) AND

RSET = 1.91kΩ

INPUT CODE (D13-D0)

11 1111 1111 1111

10 0000 0000 0000

00 0000 0000 0000

IOUTA (mA)

IOUTB (mA)

20.6

10.3

0

Power Supply

10.3

20.6

Separate digital and analog power supplies are

recommended. The allowable supply range is +2.7V to

+3.6V. The recommended supply range is +3.0 to 3.6V

(nominally +3.3V) to maintain optimum SFDR. However,

operation down to +2.7V is possible with some degradation

in SFDR. Reducing the analog output current can help the

SFDR at +2.7V. The SFDR values stated in the table of

specifications were obtained with a +3.3V supply.

Analog Output

IOUTA and IOUTB are complementary current outputs. The

sum of the two currents is always equal to the full scale

output current minus one LSB. If single ended use is

desired, a load resistor can be used to convert the output

current to a voltage. It is recommended that the unused

output be either grounded or equally terminated. The voltage

developed at the output must not violate the output voltage

Ground Planes

Separate digital and analog ground planes should be used.

All of the digital functions of the device and their

corresponding components should be located over the

digital ground plane and terminated to the digital ground

plane. The same is true for the analog components and the

analog ground plane.

compliance range of -1.0V to 1.25V. R

(the impedance

OUT

loading each current output) should be chosen so that the

desired output voltage is produced in conjunction with the

output full scale current. If a known line impedance is to be

driven, then the output load resistor should be chosen to

match this impedance. The output voltage equation is:

Nois e Reduction

V

= I

X R .

OUT

To minimize power supply noise, 0.1µF capacitors should be

OUT

placed as close as possible to the converter’s power supply

The most effective method for reducing the power

consumption is to reduce the analog output current, which

dominates the supply current. The maximum recommended

output current is 20mA.

pins, AV

and DV . Also, the layout should be designed

DD

using separate digital and analog ground planes and these

capacitors should be terminated to the digital ground for

DV

DD

and to the analog ground for AV . Additional

DD

Differential Output

filtering of the power supplies on the board is recommended.

IOUTA and IOUTB can be used in a differential-to-single-

ended arrangement to achieve better harmonic rejection.

Voltage Reference

The internal voltage reference of the device has a nominal

value of +1.23V with a ±40ppm/°C drift coefficient over the

full temperature range of the converter. It is recommended

that a 0.1µF capacitor be placed as close as possible to the

REFIO pin, connected to the analog ground. The REFLO pin

selects the reference. The internal reference can be selected

if REFLO is tied low (ground). If an external reference is

desired, then REFLO should be tied high (the analog supply

voltage) and the external reference driven into REFIO. The

full scale output current of the converter is a function of the

With R

= 50Ω and R = 50Ω, the circuit in Figure 13

DIFF

LOAD

will provide a 500mV (-2.5dBm) signal at the output of the

transformer if the full scale output current of the DAC is set

to 20mA (used for the electrical specifications table). Values

of R

= 100Ω and R = 50Ω were used for the typical

DIFF

LOAD

performance curves to increase the output power and the

dynamic range. The center tap in Figure 13 must be

grounded.

In the circuit in Figure 14, the user is left with the option to

ground or float the center tap. The DC voltage that will exist

at either IOUTA or IOUTB if the center tap is floating is

voltage reference used and the value of R

be within the 2mA to 22mA range, though operation below

2mA is possible, with performance degradation.

. I should

SET OUT

IOUT

x (R //R ) V because R is DC shorted by the

DC

A

B

DIFF

transformer. If the center tap is grounded, the DC voltage is

0V. Recommended values for the circuit in Figure 14 are

If the internal reference is used, V

will equal

approximately 1.2V. If an external reference is used, V

FSADJ

OUT

R = R = 50Ω, R

DIFF

= 100Ω, assuming R = 50Ω.

LOAD

A

B

will equal the external reference. The calculation for I

(Full Scale) is:

The performance of Figure 13 and Figure 14 is basically the

same, however leaving the center tap of Figure 14 floating

allows the circuit to find a more balanced virtual ground,

I

(Full Scale) = (V

/R

X 32.

OUT

FSADJ SET)

11

ISL5927

theoretically improving the even order harmonic rejection,

but likely reducing the signal swing available due to the

output voltage compliance range limitations.

R

= 0.5 x (R

// R

// R ), WHERE R =R

EQ

LOAD

DIFF

A

B

AT EACH OUTPUT

R

A

V

= (2 x OUTA x R )V

EQ

OUT

OUTA

R

= 0.5 x (R

//R )

LOAD DIFF

EQ

AT EACH OUTPUT

R

DIFF

LOAD

V

= (2 x OUTA x R )V

EQ

OUT

1:1

OUTB

ISL5927

R

B

OUTA

R

DIFF

LOAD

R

REPRESENTS THE

LOAD

LOAD SEEN BY THE TRANSFORMER

OUTB

ISL5927

FIGURE 14. ALTERNATIVE OUTPUT LOADING

R

REPRESENTS THE

Propagation Delay

LOAD

LOAD SEEN BY THE TRANSFORMER

The converter requires two clock rising edges for data to be

represented at the output. Each rising edge of the clock

captures the present data word and outputs the previous

data. The propagation delay is therefore 1/CLK, plus <2ns of

processing. See Figure 15.

FIGURE 13. OUTPUT LOADING FOR DATASHEET

MEASUREMENTS

Tes t Service

Intersil offers customer-specific testing of converters with a

service called Testdrive. To submit a request, fill out the

Testdrive form at www.intersil.com/testdrive. Or, send a

request to the technical support center.

Timing Diagram

t

PW2

PW1

50%

CLK

t

SU

W

t

HLD

D13-D0

W

0

3

1

2

t

PD

OUTPUT=W

PD

0

I

OUT

OUTPUT=W

1

-1

FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM

12

ISL5927

Thin Plas tic Quad Flatpack Packages (LQFP)

D

Q48.7x7A (JEDEC MS-026BBC ISSUE B)

D1

48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE

-D-

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

-

MAX

1.60

0.15

1.45

0.27

0.23

9.10

7.10

9.10

7.10

0.75

NOTES

A

A1

A2

b

-

0.062

0.005

0.057

0.010

0.009

0.358

0.280

0.358

0.280

0.029

-

0.002

0.054

0.007

0.350

0.272

0.350

0.272

0.018

0.05

1.35

0.17

8.90

6.90

8.90

6.90

0.45

-

-A-

-B-

-

6

E

E1

b1

D

-

3

D1

E

4, 5

3

e

E1

L

4, 5

-

PIN 1

N

48

0.020 BSC

48

0.50 BSC

7

e

-

SEATING

PLANE

-H-

A

Rev. 2 1/99

NOTES:

0.08

1. Controlling dimension: MILLIMETER. Converted inch

dimensions are not necessarily exact.

0.003

-C-

2. All dimensions and tolerances per ANSI Y14.5M-1982.

3. Dimensions D and E to be determined at seating plane -C- .

4. Dimensions D1 and E1 to be determined at datum plane

0.08

0.003

D

A-B

C

S

M

S

b

-H-

.

o

11 -13

0.020

5. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is 0.25mm (0.010 inch) per side.

b1

MIN

0.008

o

0

MIN

0.09/0.16

0.004/0.006

6. Dimension b does not include dambar protrusion. Allowable

dambar protrusion shall not cause the lead width to exceed

the maximum b dimension by more than 0.08mm (0.003

inch).

A2

A1

GAGE

PLANE

BASE METAL

WITH PLATING

7. “N” is the number of terminal positions.

L

0.09/0.20

0.004/0.008

o

11 -13

0.25

0.010

o

0 -7

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

3-13


型号：	ISL5927
厂家：	Intersil
描述：	Dual 14-Bit, +3.3V, 260+MSPS, High Speed D/A Converter 双路14位， + 3.3V ， + 260 MSPS，高速D / A转换器转换器
文件：	总13页 (文件大小：665K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL5927 [INTERSIL]

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