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ISL59311_0704 [INTERSIL]

Differential Video Amplifier with Common Mode Sync Encoder and Serial Digital Interface; 差分视频放大器共模同步编码器和串行数字接口
ISL59311_0704
型号： ISL59311_0704
厂家： Intersil    Intersil
描述：

Differential Video Amplifier with Common Mode Sync Encoder and Serial Digital Interface
差分视频放大器共模同步编码器和串行数字接口

视频放大器 编码器
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ISL59311  
®
Data Sheet  
April 25, 2007  
FN6372.3  
Differential Video Amplifier with Common  
Mode Sync Encoder and Serial Digital  
Interface  
Features  
• Fully differential inputs, outputs, and feedback  
• 650MHz -3dB bandwidth  
The ISL59311 is a high bandwidth triple differential amplifier  
with integrated encoding of video sync signals. The inputs  
are suitable for handling high speed video or other  
communications signals in either single-ended or differential  
form, and the common-mode input range extends all the way  
to the negative rail enabling ground-referenced signaling in  
single supply applications. The high bandwidth enables  
differential signaling onto standard twisted-pair or coax with  
very low harmonic distortion, while internal feedback  
ensures balanced gain and phase at the outputs reducing  
radiated EMI and harmonics.  
• 1500V/µs slew rate  
• -70dB distortion at 20MHz  
• Single 5V operation  
• 50mA minimum output current  
• Low power: 57mA total supply current  
• Pb-free plus anneal available (RoHS compliant)  
Block Diagram  
Embedded logic encodes standard video horizontal and  
vertical sync signals onto the common mode of the twisted  
pair(s), transmitting this additional information without the  
requirement for additional buffers or transmission lines. The  
ISL59311 enables significant system cost savings when  
compared with discrete line driver alternatives.  
VCCA  
VCCD  
VCCA domain  
VINA+  
VINA-  
+
-
VOUTA+  
VOUTA-  
Disable  
The digital block of the chip is a data transceiver which is  
intended to drive one twisted pair line. The maximum  
baudrate for this block is 50Mbps.  
V
INB+  
+
-
VOUTB+  
VOUTB-  
V
INB-  
CMA  
CMB  
HSYNC  
VSYNC  
Sync to  
Common Mode  
Translation  
The ISL59311 is available in a 32 Ld QFN package and is  
specified for operation over the -40°C to +85°C temperature  
range.  
CMC  
+
-
V
OUTC+  
V
INC+  
Applications  
V
INC-  
VOUTC-  
• Twisted-pair drivers  
VCCS domain  
VCCD domain  
VCCS  
• Differential line drivers  
• VGA over twisted-pair  
Transmit  
SOUT+  
• Transmission of analog signals in a noisy environment  
TXDATA  
RXDATA  
SDATA  
Ordering Information  
SOUT  
-
PART  
NUMBER  
(Note)  
PART  
MARKING REEL  
TAPE & PACKAGE  
(Pb-Free)  
PKG.  
DWG. #  
SIN  
+
-
+
-
SIN  
ISL59311IRZ  
59311 IRZ  
-
32 Ld QFN L32.5x6A  
32 Ld QFN L32.5x6A  
ISL59311IRZ-T13 59311 IRZ  
13”  
GNDA  
GNDD  
NOTE: Intersil Pb-free plus anneal products employ special Pb-free  
material sets; molding compounds/die attach materials and 100% matte  
tin plate termination finish, which are RoHS compliant and compatible  
with both SnPb and Pb-free soldering operations. Intersil Pb-free  
products are MSL classified at Pb-free peak reflow temperatures that  
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
ISL59311  
Pinout  
ISL59311  
(32 LD QFN)  
VSYNC  
HSYNC  
1
2
3
4
25  
V
C-  
OUT  
24 V  
23 V  
22 V  
B+  
B-  
OUT  
OUT  
OUT  
V
B+  
IN  
V
B-  
C+  
IN  
THERMAL  
PAD  
V
C+  
C-  
21 GND  
5
6
7
8
9
IN  
A
V
20 GND  
IN  
D
GND  
19 V  
CCD  
A
CCS  
CCS  
V
V
18 NC  
17 S  
+
OUT  
Pin Descriptions  
PIN NAME  
DESCRIPTIONS  
EQUIVALENT CIRCUIT  
V
A±, V B±, V C±  
Differential video inputs  
IN  
IN  
IN  
B±, V  
OUT  
V
A±, V  
C± Differential video outputs to transmission line  
Horizontal and Vertical Sync inputs to be encoded  
OUT  
OUT  
HSYNC, VSYNC  
H,V  
GNDA  
Disable  
Disable video amplifiers signal.  
Logic low enables the video amplifiers.  
Logic high disables the video amplifiers, reducing V  
consumption.  
ENV  
power  
CCA  
The Serial Digital Interface is always enabled regardless of the state of the  
Disable pin.  
GNDA  
Transmit  
Transmit/receive logic input.  
Logic high: Transmits data from the S  
line.  
pin data down the transmission  
DATA  
TR  
Logic low: Data received from the transmission line is output on the S  
pin.  
DATA  
GNDA  
S
±
Differential serial data outputs to transmission line  
Differential serial data inputs from transmission line  
OUT  
S
±
IN  
FN6372.3  
April 25, 2007  
2
ISL59311  
Pin Descriptions (Continued)  
PIN NAME  
DESCRIPTIONS  
EQUIVALENT CIRCUIT  
S
DATA  
Digital data input/output.  
When Transmit is high, this is an input, receiving the serial data to be  
transmitted over the S ± pins.  
TXRX  
OUT  
When Transmit is low, this is an output, representing the data received on  
the S ± pins.  
IN  
DIFF DATA  
V
Power supply for S  
I/O pin - sets input thresholds and output swing.  
DATA  
CCS  
Typically set to 3.3V or 5V.  
V
V
for line interface section (5V)  
CCD  
CC  
Digital ground for the Serial Digital Interface  
V for the video amplifiers (5V)  
CC  
GND  
D
V
CCA  
GND  
Analog ground for the video amplifiers  
A
NC  
No Connection. Do not connect these pins to anything. Leave these  
pins floating!  
FN6372.3  
April 25, 2007  
3
ISL59311  
Absolute Maximum Ratings (T = +25°C)  
A
Supply Voltage (V  
, V  
CCA CCD  
). . . . . . . . . . . . . . . . . . . . . . . . . +6.5V  
Input/Output Voltages  
Maximum Output Continuous Current . . . . . . . . . . . . . . . . . . ±70mA  
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C  
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+125°C  
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C  
All signal (non-supply) pins . . . . . . . . . . . . -0.6V to V  
ESD Classification  
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000V  
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250V  
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below  
http://www.intersil.com/pbfree/Pb-FreeReflow.asp  
+ 0.6V  
CCA  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all  
tests are at the specified temperature and are pulsed tests, therefore: T = T = T  
J
C
A
Electrical Specifications  
V
= V  
CCD  
= V  
= +5V, GND = GND = 0V, T = +25°C, V = 0V, R = 200Ω, unless otherwise  
CCA  
specified.  
CCS  
A
D
A
IN  
L
DESCRIPTION  
CONDITION  
MIN  
TYP  
MAX  
UNIT  
Video Amplifier Electrical Characteristics  
Output Voltage Range  
1
V
- 1  
V
CC  
Output Impedance, Disabled  
AC PERFORMANCE  
10  
MΩ  
Bandwidth, -3dB  
A
= 2, V  
= 200mV  
650  
600  
1500  
20  
MHz  
MHz  
V/µs  
ns  
V
OUT  
V
V
= 2V  
OUT  
OUT  
Differential Slew Rate,  
= 2V  
P-P  
Settling Time (0.1%, 2V  
)
P-P  
Gain Bandwidth Product  
2nd Harmonic Distortion  
3rd Harmonic Distortion  
Hostile Crosstalk  
1300  
-70  
MHz  
dBc  
dBc  
dB  
20MHz, R = 200Ω  
L
20MHz, R = 200Ω  
-70  
L
75  
Differential Phase @100MHz  
Differential Gain @100MHz  
INPUT CHARACTERISTICS  
Input Referred Offset Voltage  
Input Bias Current  
0.01  
0.01  
°
%
-10  
2
±1  
6
10  
12  
mV  
µA  
Differential Input Impedance  
Differential Input Range  
Common Mode Input Voltage Range  
Input Referred Noise  
10  
MΩ  
V
±0.75  
-0.3  
60  
V
- 2.6  
V
CCA  
15  
75  
nV/√Hz  
dB  
CMRR  
V
= 0V to 2V  
CM  
OUTPUT CHARACTERISTICS  
Output Peak Current  
±40  
1
±60  
mA  
V
Output Voltage Range  
DC PERFORMANCE  
V
- 1  
CC  
Voltage Gain  
1.90  
1.95  
2.00  
V/V  
FN6372.3  
April 25, 2007  
4
ISL59311  
Electrical Specifications  
V
= V  
CCD  
= V  
= +5V, GND = GND = 0V, T = +25°C, V = 0V, R = 200Ω, unless otherwise  
CCA  
CCS  
A
D
A
IN  
L
specified. (Continued)  
DESCRIPTION  
CONDITION  
MIN  
TYP  
MAX  
UNIT  
PSRR  
Rejection of V  
60  
75  
dB  
CCA  
Digital Transceiver Block Electrical Characteristics  
TRANSMITTER DC CHARACTERSTICS  
S
± Differential Output Voltage  
No load  
V
V
V
V
OUT  
CCD  
R
= 100Ω (Figure 1A)  
= 100Ω (Figure 1A)  
3.0  
3.3  
L
L
Change in Magnitude of Driver Differential  
R
.08  
0.2  
S
± for Complementary Output States  
|(S  
+) - (S  
-)|  
OUT  
OUT  
OUT  
S
± Common-Mode Voltage (deviation  
R
= 100Ω (Figure 1A)  
-0.1  
±0.06  
+0.1  
V
OUT  
L
from V  
/2)  
CCD  
S
± Short Circuit Current  
Driving high, output tied to GND  
Driving low, output tied to V  
95  
95  
±2  
110  
110  
mA  
mA  
nA  
OUT  
CCD  
S
± Leakage Current  
S
(Transmit = GND)  
±100  
OUT  
OUT  
TRANSMITTER SWITCHING CHARACTERISTICS  
Maximum Data Rate  
R
= 100Ω, (Figure 1A)  
50  
Mbps  
ns  
L
Differential Propagation Delay  
t
t
(Figure 2, R  
(Figure 2, R  
= 100Ω)  
6
6
2
4
10  
10  
4
PLH  
PHL  
DIFF  
DIFF  
= 100Ω)  
ns  
Differential Output Skew  
Output Enable Time  
|t  
– t  
| (Figure 2, R  
= 100Ω)  
ns  
PLH  
PHL DIFF  
t
: Driver Enable to Output High  
20  
ns  
PZH  
(Figure 3, I  
= 1mA, I  
= off)  
SOURCE  
SINK  
t
: Driver Enable to Output Low  
6
20  
35  
ns  
ns  
ns  
nA  
PZL  
(Figure 3, I  
= off, I  
SOURCE  
= 1mA)  
SINK  
Output Disable Time  
t
: Output High to Output Disabled  
PHZ  
28  
28  
±2  
(Figure 3, I  
= 25mA, I = off)  
SINK  
SOURCE  
t
: Output Low to Output Disabled  
PLZ  
35  
(Figure 3, I  
= off, I = 25mA)  
SINK  
SOURCE  
Disabled Output Leakage  
±100  
RECEIVER DC CHARACTERISTICS  
S
S
S
± Input Hysteresis  
V
= 2.5V  
CM  
2
30  
50  
mV  
V
IN  
IN  
IN  
± Input Range  
GND - 0.5  
2.5  
V
+ 0.5  
CC  
± Input Resistance; Each Input to GND  
3.0  
3.5  
kΩ  
RECEIVER SWITCHING CHARACTERISTICS  
Maximum Data Rate  
Driven with 100mV differential signal  
(Figure 4, Note 4)  
50  
Mbps  
Receiver Input to Output Propagation Delay  
T
T
(Figure 4)  
(Figure 4)  
4.7  
5.5  
0.8  
2
8
8
2
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PLH  
PHL  
PLH  
Receiver Skew  
|t  
– t  
| (Figure 4)  
PHL  
t
/t  
RISE FALL  
100kΩ II10pF load  
Receiver Enable to Output High  
Receiver Enable to Output Low  
Receiver High to Hi-Z  
15  
35  
15  
20  
42  
25  
FN6372.3  
April 25, 2007  
5
ISL59311  
Electrical Specifications  
V
= V  
CCD  
= V  
= +5V, GND = GND = 0V, T = +25°C, V = 0V, R = 200Ω, unless otherwise  
CCA  
CCS  
A
D
A
IN  
L
specified. (Continued)  
DESCRIPTION  
CONDITION  
MIN  
TYP  
MAX  
UNIT  
Receiver Low to Hi-Z  
10  
20  
ns  
System Logic Inputs DC Characteristics  
VSYNC, HSYNC, TRANSMIT, AND DISABLE INPUT CHARACTERISTICS  
Input High Voltage  
V
V
2
V
V
IH  
IL  
Input Low Voltage  
0.8  
±5  
VSYNC, HSYNC, Transmit Input Current  
Disable Pin Pull-down Resistance to GNDA  
I
±1  
µA  
kΩ  
IN  
R
500  
Disable  
S
INPUT CHARACTERISTICS (Transmit = V  
)
CCD  
DATA  
Input High Voltage  
Input Low Voltage  
Input Current  
V
V
0.7 V  
V
V
IH  
IL  
CCS  
0.3 V  
CCS  
I
±0.001  
±1  
µA  
IN  
S
OUTPUT CHARACTERISTICS (Transmit = GND)  
DATA  
High Output Level  
Sourcing 4mA to GND  
Sinking 4mA from V  
4.5  
4.7  
0.3  
20  
V
V
Low Output Level  
0.4  
CCS  
Driving high, output tied to GND  
Short Circuit Output Current  
mA  
mA  
Driving low, output tied to V  
40  
CCS  
Power Supply Characteristics  
V
V
Operating Range  
4.5  
5.5  
60  
3
V
CCA  
CCA  
Supply Current (all 3 channels)  
Operating (Disable = GND)  
50  
mA  
mA  
V
Disabled (Disable = V  
)
2.3  
CCA  
V
V
V
Operating Range  
Supply Current  
Input Impedance  
4.5  
4
5.5  
12  
6
CCD  
CCD  
CCS  
7
5
mA  
kΩ  
V
= 5V (Note 2)  
CCS  
NOTES:  
1. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless  
otherwise specified.  
2. V  
current is equal to the V  
voltage applied divided by the V  
CCS  
Input Impedance. Some additional current is consumed when S  
is  
DATA  
CCS  
CCS  
driving high into the external load.  
3. Applies to peak current. See “Typical Performance Curves” for more information.  
4. Guaranteed by characterization but not tested.  
FN6372.3  
April 25, 2007  
6
ISL59311  
Test Circuits and Waveforms  
50Ω  
50Ω  
50Ω  
S
S
-
S
S
-
OUT  
OUT  
V
CM  
S
S
DATA  
DATA  
V
V
D
D
OD  
OD  
0V to 5V  
+
+
OUT  
OUT  
V
50Ω  
OC  
FIGURE 1B. V  
WITH COMMON MODE LOAD  
FIGURE 1A. V  
AND V  
OC  
OD  
OD  
FIGURE 1. DC DRIVER TEST CIRCUITS  
5V  
DI  
2.5V  
PLH  
2.5V  
0V  
C
C
= 50pF  
= 50pF  
L
L
t
t
PHL  
V
OH  
S
S
-
S
-
OUT  
OUT  
S
DATA  
100Ω  
D
V
+
OL  
S
+
OUT  
OUT  
SIGNAL  
GENERATOR  
+V  
OD  
90%  
10%  
90%  
10%  
DIFF OUT  
(S  
+ - S -)  
OUT  
OUT  
-V  
OD  
t
t
R
F
SKEW = |t  
- t |  
PLH PHL  
FIGURE 2A. TEST CIRCUIT  
FIGURE 2B. MEASUREMENT POINTS  
FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES  
TRANSMIT  
2.5V  
2.5V  
I
I
SOURCE  
t
t
t
S
S
±
PZH  
PZL  
PHZ  
90%  
DATA  
OUT  
D
3.5V  
S
±
50pF  
OUT  
SINK  
SIGNAL  
GENERATOR  
t
PLZ  
S
±
OUT  
1.5V  
10%  
FIGURE 3B. MEASUREMENT POINTS  
FIGURE 3A. TEST CIRCUIT  
FIGURE 3. DRIVER DATA RATE  
4.0V  
S
+
2.5V  
PLH  
2.5V  
IN  
S
S
-
IN  
50pF  
S
2.5V  
DATA  
1.0V  
V
+
R
IN  
t
t
PHL  
= 5V  
CCS  
SIGNAL  
GENERATOR  
1.5V  
1.5V  
S
DATA  
0V  
FIGURE 4B. MEASUREMENT POINTS  
FIGURE 4. RECEIVER PROPAGATION DELAY AND DATA RATE  
FIGURE 4A. TEST CIRCUIT  
FN6372.3  
April 25, 2007  
7
ISL59311  
Typical Performance Curves  
V
C
= 5V  
CCA  
= 0pF  
R
= 500Ω  
BLUE CM  
OUT (CH C)  
L
L
CHAN A  
R
= 200Ω  
L
GREEN CM  
OUT (CH B)  
RED CM  
R
= 100Ω  
OUT (CH A)  
L
R
= 50Ω  
L
V
SYNC  
H
SYNC  
TIME (0.5ms/DIV)  
FIGURE 6. DIFFERENTIAL FREQUENCY RESPONSE FOR  
FIGURE 5. COMMON MODE OUTPUT  
VARIOUS R - DIFF (CHANNEL A)  
L
V
C
= 5V  
= 0pF  
V
C
= 5V  
CCA  
R
= 500Ω  
CCA  
= 0pF  
L
R
= 500Ω  
L
L
L
CHAN C  
CHAN B  
R
= 200Ω  
L
R
= 200Ω  
L
R
= 100Ω  
L
R
= 100Ω  
L
R
= 50Ω  
L
R
= 50Ω  
L
FIGURE 8. DIFFERENTIAL FREQUENCY RESPONSE FOR  
FIGURE 7. DIFFERENTIAL FREQUENCY RESPONSE FOR  
VARIOUS R - DIFF (CHANNEL C)  
VARIOUS R - DIFF (CHANNEL B)  
L
L
V
R
= 5V  
= 200Ω  
CCA  
V
R
= 5V  
= 200Ω  
CCA  
C
= 12pF  
C = 12pF  
L
L
L
L
CHAN A  
CHAN B  
C
C
= 8.2pF  
C
= 8.2pF  
L
L
C
= 4.7pF  
L
C
= 4.7pF  
L
= 2.2pF  
C
= 2.2pF  
L
L
FIGURE 9. DIFFERENTIAL FREQUENCY RESPONSE FOR  
FIGURE 10. DIFFERENTIAL FREQUENCY RESPONSE FOR  
VARIOUS C - DIFF (CHANNEL B)  
VARIOUS C - DIFF (CHANNEL A)  
L
L
FN6372.3  
April 25, 2007  
8
ISL59311  
Typical Performance Curves (Continued)  
V
R
= 5V  
= 200Ω  
V
R
THD  
= 5V  
= 200Ω  
CCA  
CCA  
C
= 12pF  
L
L
L
CHAN C  
C
= 8.2pF  
L
OUTPUT C  
OUTPUT A  
C
= 4.7pF  
L
OUTPUT B  
C
= 2.2pF  
L
FIGURE 11. DIFFERENTIAL FREQUENCY RESPONSE FOR  
VARIOUS C - DIFF (CHANNEL C)  
FIGURE 12. TOTAL HARMONIC DISTORTION  
L
V
= 5V  
V
= 5V  
CCA  
CCA  
R
= 200Ω  
HARMONIC  
R
= 200Ω  
L
L
ND  
RD  
2
3
HARMONIC  
OUTPUT C  
OUTPUT B  
OUTPUT A  
OUTPUT A  
OUTPUT B  
OUTPUT C  
ND  
RD  
FIGURE 13. 2  
HARMONIC DISTORTION  
FIGURE 14.  
3
HARMONIC DISTORTION  
R
C
= 200Ω DIFF  
= 0pF  
R
C
= 200Ω DIFF  
= 0pF  
L
L
L
L
RISE  
FALL  
Δt = 1.4ns  
Δt = 1.3ns  
RISE  
FALL  
Δt = 1.2ns  
Δt = 1.1ns  
TIME (20ns/DIV)  
TIME (20ns/DIV)  
FIGURE 15. DIFFERENTIAL LARGE SIGNAL TRANSIENT  
RESPONSE  
FIGURE 16. DIFFERENTIAL SMALL SIGNAL TRANSIENT  
RESPONSE  
FN6372.3  
April 25, 2007  
9
ISL59311  
Typical Performance Curves (Continued)  
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL  
CONDUCTIVITY TEST BOARD - QFN EXPOSED  
DIEPAD SOLDERED TO PCB PER JESD51-5  
JEDEC JESD51-3 AND SEMI G42-88  
(SINGLE LAYER) TEST BOARD  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
3
2.857W  
2.5  
758mW  
2
1.5  
1
0.5  
0
0
25  
50  
75 85 100  
125  
150  
0
25  
50  
75 85 100  
125  
150  
AMBIENT TEMPERATURE (°C)  
AMBIENT TEMPERATURE (°C)  
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT  
TEMPERATURE  
FIGURE 17. PACKAGE POWER DISSIPATION vs AMBIENT  
TEMPERATURE  
consists of three fully differential video signals, with sync  
encoded on the common mode of each of the three RGB  
Operational Description and Application  
Information  
differential signals. H  
and V can easily be  
SYNC  
SYNC  
Introduction  
separated from the differential output signals, decoded and  
transmitted along with the RGB video signals to the video  
monitor.  
The ISL59311 is designed to differentially drive composite  
RGB video signals onto twisted pair lines, while  
simultaneously encoding horizontal and vertical sync signals  
as common mode output. The entire video signal plus sync  
can therefore be transmitted on 3 twisted pairs of wire. When  
utilizing CAT5 cable, the 4th available twisted pair can be  
used for transmission of audio, data or control information.  
The distribution of composite video over standard CAT5  
cable enables enormous cost and labor savings compared  
with traditional coaxial cable, when considering both the  
relative low price and ease of pulling CAT5 cable.  
Sync Transmission  
The ISL59311 encodes H  
and V signals on the  
SYNC  
SYNC  
common mode output of the differential video signals; Red,  
Green and Blue respectively. Data Sheet Table 1 shows the  
common mode levels for the different SYNC input  
combinations. Note that the sum of the common mode  
voltages results in a fixed average DC level with no AC  
content. This dramatically reduces EMI radiation into any  
common mode signal along the twisted pairs of CAT5 cable.  
The digital block of the chip is a data transceiver which is  
intended to drive one twisted pair line. The maximum  
baudrate for this block is 50Mbps.  
Extract Common Mode Sync and Decode H  
SYNC  
and V  
SYNC  
Functional Description  
H
and V  
can be regenerated from the Common  
SYNC  
SYNC  
The ISL59311 provides three fully differential high-speed  
amplifiers, suitable for driving high-resolution composite  
video signals onto twisted pair or standard coaxial cable.  
The input common-mode range extends to the negative rail,  
allowing simple ground-referenced input termination to be  
used with a single supply. The amplifiers provide a fixed gain  
of +2 to compensate for standard video cable termination  
Mode sync output voltages. The relationships between  
, V and the 3 common mode levels are given by  
Table 1. The common mode levels are easily separated from  
the differential outputs of the ISL59311 using this simple  
resistor network at the cable receiver input of each  
differential channel; see Figure 20.  
H
SYNC SYNC  
TABLE 1. SYNC SIGNAL ENCODING  
schemes. Horizontal and Vertical sync signals (H  
and  
SYNC  
V
) are passed to an internal Logic Encoding Block to  
COMMON  
MODE A  
(RED)  
COMMON  
MODE B  
(GREEN)  
COMMON  
MODE C  
(BLUE)  
SYNC  
encode the sync information as three discrete signals of  
different voltage levels. Generally, in differential amplifiers an  
HSYNC  
Low  
VSYNC  
High  
Low  
external V  
pin is used to control the common mode level  
3.0  
2.5  
2.0  
2.5  
2.0  
3.0  
3.0  
2.0  
2.5  
2.0  
2.5  
3.0  
REF  
of the differential output; in the case of the ISL59311 the  
of each of the three internal amplifier channels  
Low  
V
REF  
receives a signal from the Logic Encoding Block with  
encoded H and V information. The final output  
High  
High  
Low  
High  
SYNC  
SYNC  
FN6372.3  
April 25, 2007  
10  
ISL59311  
Long Distance Video Transmission  
DISABLE  
The SXGA Video Transmission System makes it possible to  
transmit Red, Green and Blue (RGB) video plus sync up to  
1000ft through CAT5 cable. The input to the SXGA Video  
Transmission System is the output of a video source  
+
+
+
-
V
A
V
A
OUT  
IN  
-
-
V
REF  
transmitting RGB video signals plus sync. The signals are  
received initially by the ISL59311; which converts the single  
ended input RGB signals to three fully differential waveforms  
with sync encoded on the discrete common modes of each  
color channel and then drives the signals through a length of  
CAT5 cable. The signal is received by the EL9111, which can  
provide 6-pole equalization for both high and low frequency  
signal transmission line losses. Then the EL9111 converts  
the differential RGB video signals back into single ended  
format while extracting the common mode component for  
decoding. The single ended RGB signal is taken directly  
from the output of the EL9111 and is ready for the output  
device. The EL9111 Common Mode Decoder Circuit  
DISABLE  
+
+
+
-
V
V
B
V
B
C
V
H
IN  
OUT  
SYNC  
-
-
CM  
CM  
CM  
A
B
C
V
REF  
LOGIC  
DECODING  
SYNC  
DISABLE  
DISABLE  
+
+
+
-
C
V
IN  
OUT  
-
-
V
REF  
FIGURE 19. VIDEO DRIVER BLOCK DIAGRAM  
Twisted Pair Termination  
The schematic in Figure 20 illustrates a termination scheme  
for 50Ω series termination and a 100Ω twisted pair cable.  
Note RCM is the common mode termination to allow  
receives the common mode signals and decodes them and  
transmits H  
SYNC  
and V  
to the output device.  
SYNC  
measurement of V  
loads the ISL59311; a little over a 100Ω is recommended for  
RCM.  
and should not be too small since it  
CM  
Disabling the Amplifiers with the Disable Pin  
The Disable pin must be a logic low for normal operation of  
the video amplifiers. When Disable is taken high, the  
amplifiers are disabled, reducing supply V  
current. (The Disable pin has no effect on the Serial Digital  
Transceiver - it is always enabled as long as power is  
supply  
+
50Ω  
CCA  
TWISTED  
PAIR  
50Ω  
50Ω  
+
-
V
CM  
50Ω  
Z
=100Ω  
O
120Ω  
applied to V  
.)  
-
CCD  
(RCM: SHOULD BE >100Ω)  
(FOR LOADING  
CONSIDERATIONS)  
V
REF  
Serial Digital Transceiver Operation  
FIGURE 20. TWISTED PAIR TERMINATION  
The digital transceiver is a half-duplex design, either  
receiving data on the S pins and sending it out on the  
IN  
S
pin, or transmitting data from the S  
pin out on  
pins. The digital transceiver operates in a  
DATA  
some the 2 S  
DATA  
Video Transmission  
OUT  
The ISL59311 is a twisted pair differential line driver directed  
at the transmission of Video Signals through cables up to  
100 feet; however, as signal losses increase with  
transmission line length the ISL59311 will need additional  
support to equalize video signals along longer twisted pair  
transmission lines. A full solution to accomplish this is the  
SXGA Video Transmission System presented in the  
ISL59311 Data Sheet. Note the inclusion of the EL9111 for  
signal equalization of up to 1000ft of CAT5 cable and  
common mode extraction; see Data Sheet for additional  
information on the EL9111.  
high speed (up to 50MBaud) differential mode. The SDATA  
pin is the half-duplex logic-level transmit and receive data  
pin. SDATA is an output when Transmit = low (receive mode)  
and an input when Transmit = high (transmit mode). This can  
be made to work with existing designs that use independent  
transmit and receive pins by connecting SDATA directly to the  
transmit pin and through a resistor to the receive pin.  
Figure 21 shows an example of how to interface the  
ISL59311 with an RS485 transceiver.  
V
is the power source for the digital line interface drivers  
CCD  
and receivers.  
FN6372.3  
April 25, 2007  
11  
ISL59311  
+5V  
+5V  
+
+
0.1μF  
0.1μF  
19  
8
V
V
CCS  
CC  
S
+
IN  
15  
16  
17  
13  
S
11  
12  
DATA  
4
DI  
R
S -  
IN  
D
R
T
R
T
3
2
S
+
-
7
6
B/Z  
A/Y  
DE  
RE  
OUT  
TRANSMIT  
S
OUT  
1
RO  
R
D
GND  
GND  
5
ISL59311  
7
ISL83088  
FIGURE 21. RS-485 SERIAL INTERFACE CONNECTION DIAGRAM  
Digital Transceiver Block Diagram  
Proper Layout Technique  
TXEN  
A critical concern with any PCB layout is the establishment  
of a “healthy” ground plane. It is imperative to provide  
ground planes terminated close to inputs to minimize input  
capacitance. Additionally, the ground plane can be  
selectively removed from inputs to prevent load and supply  
currents from flowing near the input nodes.  
S
+
OUT  
R1  
In general the following guidelines apply to all PCB layout:  
• Keep all traces as short as possible.  
ENCODING  
TXDATA  
(S  
S
-
OUT  
R3  
)
DATA  
• Keep power supply bypass components as close to the  
chip as possible - extremely close.  
TRANSMIT  
• Create a healthy ground with low impedance and  
continuous ground pathways available to all grounded  
components board-wide.  
• In high frequency applications on multi-level boards try to  
keep one level of board with continuous ground plane and  
minimum via cutouts - providing it is affordable.  
S
S
+
IN  
• Provide extremely short loops from power pin to ground.  
RDATA  
(S  
)
DATA  
-
• If it is affordable, a ferrite bead is always of benefit to  
isolate device from Power Supply noise and the rest of the  
circuit from the noise of the device.  
IN  
FN6372.3  
April 25, 2007  
12  
ISL59311  
Power Dissipation Calculation  
When switching at high speeds, or driving heavy loads, the  
ISL59311 drive capability is ultimately limited by the rise in die  
temperature brought about by internal power dissipation. For  
reliable operation die temperature must be kept below T  
JMAX  
(+125°C). It is necessary to calculate the power dissipation for  
a given application prior to selecting package type. Power  
dissipation may be calculated:  
4
2
S
2
PD = (V × I ) × (C  
× V × f) + (C × V  
× f)  
Σ
S
S
INT  
L
OUT  
1
where:  
• V is the total power supply to the ISL59311 (= V  
)
CCD  
S
• V  
OUT  
is the swing on the output (V - V )  
H L  
• C is the load capacitance  
L
• C  
INT  
is the internal load capacitance (80pF max)  
• I is the quiescent supply current  
S
• f is frequency  
Having obtained the application's power dissipation, the  
maximum junction temperature can be calculated:  
T
= T  
+ Θ × PD  
MAX JA  
JMAX  
where:  
• T  
• T  
is the maximum junction temperature (+125°C)  
JMAX  
is the maximum ambient operating temperature  
MAX  
• PD is the power dissipation calculated above  
θ
is the thermal resistance, junction to ambient, of the  
JA  
application (package + PCB combination). Refer to the  
Package Power Dissipation curves. See Technical Bulletin  
389 (http://www.intersil.com/data/tb/TB389.pdf) for additional  
QFN PCB layout information.  
FN6372.3  
April 25, 2007  
13  
ISL59311  
Quad Flat No-Lead Plastic Package (QFN)  
Micro Lead Frame Plastic Package (MLFP)  
L32.5x6A (One of 10 Packages in MDP0046)  
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE  
(COMPLIANT TO JEDEC MO-220)  
A
MILLIMETERS  
D
SYMBOL  
MIN  
0.80  
0.00  
NOMINAL  
0.90  
MAX  
1.00  
0.05  
NOTES  
B
A
A1  
D
-
0.02  
-
1
2
3
5.00 BSC  
2.48 REF  
6.00 BSC  
3.40 REF  
0.50  
-
PIN #1  
I.D. MARK  
D2  
E
-
-
E
E2  
L
-
0.45  
0.20  
0.55  
0.24  
-
b
0.22  
-
2X  
0.075 C  
c
0.20 REF  
0.50 BSC  
32 REF  
7 REF  
-
e
-
2X  
0.075 C  
N
4
TOP VIEW  
ND  
NE  
6
9 REF  
5
0.10 M C A B  
b
Rev 0 9/05  
NOTES:  
L
1. Dimensioning and tolerancing per ASME Y14.5M-1994.  
2. Tiebar view shown is a non-functional feature.  
PIN #1 I.D.  
3
1
2
3
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.  
4. N is the total number of terminals on the device.  
5. NE is the number of terminals on the “E” side of the package  
(or Y-direction).  
(E2)  
6. ND is the number of terminals on the “D” side of the package  
(or X-direction). ND = (N/2)-NE.  
5
NE  
7. Inward end of terminal may be square or circular in shape with  
radius (b/2) as shown.  
7
(D2)  
BOTTOM VIEW  
0.10 C  
e
C
(c)  
2
SEATING  
PLANE  
A
C
0.08 C  
(L)  
SEE DETAIL "X"  
N LEADS  
& EXPOSED PAD  
A1  
DETAIL X  
N LEADS  
SIDE VIEW  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN6372.3  
April 25, 2007  
14  

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