ISL54230IRTZ-T [INTERSIL]
Octal Multiprotocol Switch; 八通道多协议交换机
| 型号： | ISL54230IRTZ-T |
| 厂家： | 
Intersil |
| 描述： | Octal Multiprotocol Switch |
| 文件： | 总16页 (文件大小：1479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL54230
®
Data Sheet
December 26, 2008
FN6825.0
Octal Multiprotocol Switch
Features
The Intersil ISL54230 is a multiprotocol Quad Double-Pole
Double-Throw (DPDT) analog switch that can operate from a
single +2.0V to +5.5V supply. It contains eight SPDT (Single
Pole/Double Throw) switches configured into four DPDT
blocks. Each DPDT block is independently controlled by a
logic input for Normally Open (NO) or Normally Closed (NC)
switch configuration.The part is designed for switching or
routing a combination of USB High-Speed, USB Full-Speed,
digital, and analog signals in portable battery powered
products.
• High Speed (480Mbps) and Full Speed (12Mbps)
Signaling Capability per USB 2.0
• Compliant with USB 2.0 Short Circuit and Overvoltage
Requirements Without Additional External Components
• 1.8V Logic Compatible (+2.7V to +3.6V Supply)
• Switch Terminals Overvoltage Protected Up to +5.5V
• Enable Pin to disable Switch Blocks
• Two DPDT 1Ω/6Ω Switches
• Two DPDT USB 2.0 FS/HS Capable Switches
• USB Switch Low ON Capacitance. . . . . . . . . . . . . . . 12pF
• USB Switch Low ON-Resistance. . . . . . . . . . . . . . . . . 6Ω
The digital inputs are 1.8V logic compatible when operated
with a 2.7V to 3.6V supply. The ISL54230 has two switch
enable pins to disable certain blocks of the switch. The
ISL54230 is available in a 32 Ld TQFN 5mmx5mm package.
It operates over a temperature range of -40 to +85°C.
• Single Supply Operation (V ) . . . . . . . . . . +2.0V to +5.5V
DD
• Low Power Consumption (P ) . . . . . . . . . . . . . . . . . . 1µA
D
Applications
• Low I+ Current when V
is not at the V+ Rail
INH
• Cellular/Mobile Phones
• PDA’s
• Available in 32 Ld 5mmx5mm TQFN package
• Pb-Free (RoHS Compliant)
• Digital Cameras and Camcorders
• USB/UART/Audio Switching
Block Diagram
V
DD
NO1A
1Ω
6Ω
COM1A
IN1
NC1A
NO1B
COM1B
NC1B
NO2A
NC2A
NO2B
NC2B
HS_USB
HS_USB
HS_USB
HS_USB
COM2A
IN2
COM2B
NO3A
COM3A
IN3
NC3A
NO3B
COM3B
NC3B
NO4A
1Ω
6Ω
COM4A
IN4
NC4A
NO4B
COM4B
OE1
NC4B
GND
OE2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL54230
Pinouts
ISL54230
(32 LD 5X5 TQFN)
TOP VIEW
*Refer to OE Control
Truth Table, page 3
31
30 29
28
26 25
32
27
NC_1A
24
23
1
2
NC_4A
COM_1A
COM_4A
22
21
NC_2A
NO_1A
NC_3A
NO_4A
NO_3A
NC_3B
3
4
*LEFT PLANE
*RIGHT PLANE
20
19
NO_2A
NC_2B
5
6
18
17
NO_2B
NC_1B
7
8
NO_3B
NC_4B
9
10
11 12
13
15 16
14
SWITCHES 1 AND 2
SWITCHES 3 AND 4
V
V
DD
DD
NO1A
NO3A
USB HS SWITCH
USB HS SWITCH
1Ω SWITCH
6Ω SWITCH
COM1A
COM1B
COM3A
COM3B
NC1A
NO1B
NC1B
NC3A
NO3B
NC3B
NO4A
NO2A
USB HS SWITCH
USB HS SWITCH
1Ω SWITCH
6Ω SWITCH
COM4A
COM4B
COM2A
COM2B
NC4A
NO4B
NC4B
NC2A
NO2B
NC2B
IN1
IN2
OE1
OE2
IN3
IN4
LOGIC
CONTROL
LOGIC
CONTROL
OE1
OE2
GND
GND
NOTE: Switches shown in Logic “0” position. Logic “0” when INx
<0.5V
FN6825.0
December 26, 2008
2
ISL54230
Pin Descriptions (Continued)
OE Control Truth Table
PIN NUMBER
TQFN
SWITCH
ON
SWITCH
OFF
MODE
USB
PIN NAME
COM_1A
COM_1B
COM_2A
COM_2B
COM_3A
COM_3B
COM_4A
COM_4B
NC_1A
DESCRIPTION
OE1
OE2
23
28
25
26
32
31
2
HS Switch Common 1A
HS Switch Common 1B
HS Switch Common 2A
HS Switch Common 2B
6Ω Switch Common 3A
1Ω Switch Common 3B
6Ω Switch Common 4A
1Ω Switch Common 4B
Switch Normally Closed 1A
Switch Normally Closed 1B
Switch Normally Closed 2A
Switch Normally Closed 2B
Switch Normally Closed 3A
Switch Normally Closed 3B
Switch Normally Closed 4A
Switch Normally Closed 4B
Switch Normally Open 1A
Switch Normally Open 1B
Switch Normally Open 2A
Switch Normally Open 2B
Switch Normally Open 3A
Switch Normally Open 3B
Switch Normally Open 4A
Switch Normally Open 4B
0
0
COM2x,
COM3x
COM1x,
COM4x
0
1
1
1
0
1
COM3x,
COM4x
COM1x,
COM2x
Left Plane
Right Plane
All On
COM1x,
COM2x
COM3x,
COM4x
ALL
NONE
Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a 2.7V to 3.6V
Supply.
29
24
17
22
19
3
Input Select Truth Table
NC_1B
INx
NOx
OFF
ON
NCx
ON
NC_2A
0
NC_2B
1
OFF
NC_3A
Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a
NC_3B
6
2.7V to 3.6V Supply.
NC_4A
1
Pin Descriptions
NC_4B
8
PIN NUMBER
NO_1A
NO_1B
NO_2A
NO_2B
NO_3A
NO_3B
NO_4A
NO_4B
21
16
20
18
5
PIN NAME
VDD
GND
OE1
OE2
IN1
TQFN
DESCRIPTION
Power Supply Pin
14
11
Ground Connection
27
Switch Enable Control 1
Switch Enable Control 2
Switch Input Select 1
Switch Input Select 2
Switch Input Select 3
Switch Input Select 4
30
7
15
4
IN2
13
9
IN3
12
IN4
10
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL54230IRTZ-T* 54230 IRTZ
-40 to +85
32 Ld 5x5 TQFN (Tape and Reel)
L32.5x5A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN6825.0
December 26, 2008
3
ISL54230
Absolute Maximum Ratings
Thermal Information
V
to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.5V
Thermal Resistance (Typical, Notes 2, 3)
32 Ld 5x5mm TQFN Package . . . . . . .
θ
(°C/W)
30
θ
JC
(°C/W)
1.5
DD
JA
Input Voltages
NCx, NOx (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +6.5V
INx, OEx (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.5V
Output Voltages
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
COMx (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Continuous Current (NC2x, NO3x) . . . . . . . . . . . . . . . . . . . . ±40mA
Continuous Current (NC1x, NO4x) . . . . . . . . . . . . . . . . . . . ±150mA
Peak Current (NC2x, NO3x)
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±100mA
Peak Current (NC1x, NO4x)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
V
Supply Voltage Range . . . . . . . . . . . . . . . . . . . +2.0V to +5.5V
DD
Logic Control Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to V
Analog Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V
DD
DD
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±300mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Signals on NCx, NOx, COMx, INx, and OEx exceeding V
DD
or GND by specified amount are clamped. Limit current to maximum current ratings.
2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379 for details.
3. For θ , the “case temperature” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: V = +2.7V, GND = 0V, V
= 1.4V, V
= 0.5V,
INxL
DD
INxH
V
= 1.4V, V
= 0.5V, (Note 4), Unless Otherwise Specified
OExH
OExL
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Notes 5, 6) TYP (Notes 5, 6) UNITS
ANALOG SWITCH CHARACTERISTICS
USB HS Switch, COM2x and COM3x
Analog Signal Range, V
ANALOG
Full
25
0
-
-
-
-
-
-
-
-
-
-
-
V
V
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
DD
-
ON-Resistance, r
High Speed
V
V
= 2.7V, V
= V
, I
OExH COMx
= 40mA, V
= 40mA, V
= 40mA, V
or
or
or
8.3
ON
DD
OEx
= 0V to 400mV (see Figure 1)
NOx
NOx
NOx
NCx
Full
25
9.25
0.11
0.22
1.45
1.8
-
-
-
-
-
r
Matching Between Channels,
V
V
= 2.7V, V = V
OEx
= Voltage at max r , (Note 8)
, I
OExH COMx
ON
Δr
DD
High Speed
ON,
NCx
ON
Full
25
r
Flatness, R
V
V
= 2.7V, V
= V
, I
OExH COMx
ON
High Speed
FLAT(ON)
DD
OEx
= 0V to 400mV, (Note 7)
NCx
Full
25
ON-Resistance, r
Full Speed
V
V
= 2.7V, V
= V
, I
OExH COMx
= 1mA, V
or
130
150
1.2
150
ON
DD
OEx
=0V to 2.7V (see Figure 1, Note 9)
NOx
NCx
Full
25
178
r
Matching Between Channels,
V
V
= 2.7V, V = V
OEx
= Voltage at max R over signal range of 0V to 2.7V
, I
OExH COMx
= 1mA, V
or
-
-
ON
Δr
DD
NOx
Full-Speed
ON,
NCx
ON
Full
2.6
(Note 8)
r
Flatness, R
V
V
= 2.7V, V
= V
, I
OExH COMx
= 1mA, V
= 1mA, V
or
or
25
Full
25
-
-
4
5
-
-
Ω
Ω
ON
Full-Speed
FLAT(ON)
DD
OEx
= 0V to 1V (Note 7)
NOx
NCx
ON-Resistance, R
ON
V
V
= 2.7V, V
= V
, I
OExH COMx
-
128
140
4
-
Ω
DD
OEx
= 0V to 1.8V (see Figure 1)
NOx
NCx
Full
25
-
-
Ω
OFF Leakage Current, I
or
V
V
= 3.6V, V
= Such that switch is disabled,
-20
-100
-50
-100
20
100
50
100
nA
nA
nA
nA
NOx(OFF)
DD
OEx
I
= 0.3V, 3.3V, V
= 3.3V, 0.3V, V = 3.3V, 0.3V
NCx
NCx(OFF)
COMx
NOx
Full
25
-
ON Leakage Current, I
V
V
= 3.6V, V
= V
, V
= 0.3V, 3.3V,
= 0.3V, 3.3V
NCx
4
COMx(ON)
DD
OEx
= 0.3V, 3.3V, V
OExH COMx
NOx
Full
-
FN6825.0
December 26, 2008
4
ISL54230
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: V = +2.7V, GND = 0V, V
= 1.4V, V
= 0.5V,
INxL
DD
INxH
V
= 1.4V, V
= 0.5V, (Note 4), Unless Otherwise Specified (Continued)
OExH
OExL
TEMP MIN MAX
PARAMETER
Power OFF Leakage Current, I , I
TEST CONDITIONS
= 0V to 5.25V, V = 0V to 5.25V,
(°C) (Notes 5, 6) TYP (Notes 5, 6) UNITS
V
V
= 0V, V
= 0V, V
25
-
-
2
-
100
2
nA
µA
D+ D- DD
NOx
NCx
such that switch is disabled
OEX
INX
(see Figure 5)
Full
1Ω Switch, COM1A and COM4A
Analog Signal Range, V
Full
25
0
-
-
V
V
Ω
Ω
Ω
Ω
ANALOG
DD
ON-Resistance, R
ON
V
V
= 2.7V, V
= V
, I
OExH COMx
= 100mA, V
or
or
1.26
1.5
1.5
DD
OEx
= 0V to 2.7V (see Figure 1, Note 9)
NOx
NCx
Full
25
-
1.74
r
Matching Between Channels,
V
V
= 2.7V, V = V
OEx
= Voltage at max r
, I
OExH COMx
= 100mA, V
-
0.05
0.07
-
-
ON
Δr
DD
NOx
over signal range of 0V to 2.7V,
ON
NCx
ON
Full
-
(Note 8)
r
Flatness, R
V
V
= 2.7V, V
= V
, I
OExH COMx
= 100mA, V
or
or
25
Full
25
-
-
0.37
0.37
1.3
1.4
4
0.52
0.6
-
Ω
Ω
ON
FLAT(ON)
DD
OEx
= 0V to 2.7V (Note 7)
NOx
NOx
NCx
ON-Resistance, R
ON
V
V
= 2.7V, V
= V
, I
OExH COMx
= 100mA, V
-
Ω
DD
OEx
= 0V to 1.8V (see Figure 1)
NCx
Full
25
-
-
Ω
OFF Leakage Current, I
or
V
V
= 3.6V, V = 0.3V, 3.3V,
OEx
= 3.3V, 0.3V, V = 3.3V, 0.3V
NCx
= V
, V
-20
-150
-50
-300
20
150
50
300
nA
nA
nA
nA
NOx(OFF)
DD
OExL COMx
I
NCx(OFF)
NOx
Full
25
-
ON Leakage Current, I
V
V
= 3.6V, V
= V
, V
= 0.3V, 3.3V,
= 0.3V, 3.3V
NCx
10
-
COMx(ON)
DD
OEx
= 0.3V, 3.3V, V
OExH COMx
NOx
Full
6Ω Switch, COM1B and COM4B
Analog Signal Range, V
Full
25
0
-
-
V
V
Ω
Ω
Ω
Ω
ANALOG
DD
ON-Resistance, r
V
V
= 2.7V, V
= V
, I
OExH COMx
= 40mA, V
or
8
9.2
ON
DD
OEx
= 0V to 2.7V (see Figure 1, Note 9)
NOx
NCx
Full
25
-
9.2
0.08
0.3
10.8
r
Matching Between Channels,
V
V
= 2.7V, V = V
OEx
= Voltage at max r
, I
OExH COMx
= 40mA, V
or
-
-
-
ON
Δr
DD
NOx
over signal range of 0V to 2.7V,
ON
NC x
ON
Full
-
(Note 8)
r
Flatness, R
V
V
= 2.7V, V
= V
, I
OExH COMx
= 40mA, V
or
or
25
Full
25
-
-
1.9
1.9
8
2.8
3.3
-
Ω
Ω
ON
FLAT(ON)
DD
OEx
= 0V to 2.7V (Note 7)
NOx
NOx
NCx
ON-Resistance, R
ON
V
V
= 2.7V, V
= V
, I
OExH COMx
= 40mA, V
-
Ω
DD
OEx
= 0V to 1.8V (see Figure 1)
NCx
Full
25
-
8.8
4
-
Ω
OFF Leakage Current, I
or
V
V
= 3.6V, V = 0.3V, 3.3V,
OEx
= 3.3V, 0.3V, V = 3.3V, 0.3V
NCx
= V
, V
-20
-100
-50
-130
20
100
50
130
nA
nA
nA
nA
NOx(OFF)
DD
OExL COMx
I
NCx(OFF)
NOx
Full
25
-
ON Leakage Current, I
V
V
= 3.6V, V
= V
, V
= 0.3V, 3.3V,
= 0.3V, 3.3V
NCx
4
COMx(ON)
DD
OEx
= 0.3V, 3.3V, V
OExH COMx
NOx
Full
-
DYNAMIC CHARACTERISTICS
USB HS Switch
Skew, t
V
= 3.0V, V
= V
, R = 45Ω, C = 10pF,
25
-
50
-
ps
SKEW
DD
OEx
OExH
L
L
t
= t = 720ps at 480Mbps, Duty Cycle = 50%
R
F
(see Figure 6)
Total Jitter, t
V
=3.0V, V
= V
, R = 45Ω, C = 10pF,
25
25
-
-
210
250
-
-
ps
ps
J
DD
OEx
OExH
L
L
t
= t = 750ps at 480Mbps
R
F
Propagation Delay, t
V
= 3.0V, V
= V
, R = 45Ω, C = 10pF
OExH L L
PD
DD
(see Figure 6)
OEx
OFF-Isolation
V
= 3.0V, R = 50Ω, f = 240MHz (see Figure 2)
25
25
-
-
-15
-
-
dB
DD
L
HS Switch -3dB Bandwidth,
Signal = 50mV
, R = 50Ω
500
MHz
RMS
L
FN6825.0
December 26, 2008
5
ISL54230
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: V = +2.7V, GND = 0V, V
= 1.4V, V
= 0.5V,
INxL
DD
INxH
V
= 1.4V, V
= 0.5V, (Note 4), Unless Otherwise Specified (Continued)
OExH
OExL
TEMP MIN MAX
PARAMETER
OFF Capacitance, C
TEST CONDITIONS
(°C) (Notes 5, 6) TYP (Notes 5, 6) UNITS
or
f = 1MHz, V
DD
(see Figure 3)
= 3.0V, V
= V
, V
OExH NOx
or V
or V
= 0V
= 0V
25
-
6.2
-
pF
NOxOFF
OEx
NCx
NCx
C
NCxOFF
COM ON Capacitance, C
f = 1MHz, V
= 3.0V, V
= V
, V
OExH NOx
25
-
12.5
-
pF
COMxON
DD
(see Figure 3)
OEx
1Ω Switches
Crosstalk
V
V
= 3.0V, R = 50Ω, f = 10MHz (see Figure 4)
25
25
25
25
-
-
-
-
-90
55
78
21
-
-
-
-
dB
dB
DD
DD
L
OFF-Isolation
Switch -3dB Bandwidth
= 3.0V, R = 50Ω, f = 1MHz (see Figure 2)
L
Signal = 50mV
, R = 50Ω
MHz
pF
RMS
L
OFF Capacitance, C
NOxOFF
or
f = 1MHz, V
DD
(see Figure 3)
= 3.0V, V
= V
, V
OExH NOx
or V
or V
= 0V
= 0V
OEx
NCx
NCx
C
NCxOFF
COM ON Capacitance, C
f = 1MHz, V
= 3.0V, V
= V
, V
OExH NOx
25
-
61
-
pF
COMxON
DD
(see Figure 3)
OEx
6Ω Switches
Crosstalk
V
V
= 3.0V, R = 50Ω, f = 10MHz (see Figure 4)
25
25
25
25
-
-
-
-
-67
50
310
6
-
-
-
-
dB
dB
DD
DD
L
OFF-Isolation
Switch -3dB Bandwidth
= 3.0V, R = 50Ω, f = 10MHz (see Figure 2)
L
50mV
, R = 50Ω
MHz
pF
RMS
L
OFF Capacitance, C
NOxOFF
or
f = 1MHz, V
DD
(see Figure 3)
= 3.0V, V
= V
= V
, V
OExH NOx
or V
or V
= 0V
= 0V
OEx
OEx
NCx
NCx
C
NCxOFF
COM ON Capacitance, C
f = 1MHz, V
= 3.0V, V
, V
OExH NOx
25
-
15
-
pF
COMxON
DD
(see Figure 3)
POWER SUPPLY CHARACTERISTICS
Power Supply Range, V
Full
25
2.7
3.6
V
DD
Positive Supply Current, I
V
V
= 3.6V, V
= V
= 0V, V
or V
NCx
= 0V,
NCx
-
-
-
1
1.24
1
2
-
µA
µA
µA
DD
DD
OEx
INx
NOx
or V
= 0V
COMx
Full
25
Power Supply Current, I
V
V
= 3.6V, V
= 1.8V, V
NOx
= 0V,
-
DD
DD
Logic
= 0V. Driving one logic pin only.
COMx
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
, V
INLx OELx
V
V
V
V
= 2.7V to 3.6V
= 2.7V to 3.6V
= 2.7V to 3.6V
= 2.7V to 3.6V
Full
Full
Full
Full
-
-
-
0.5
-
V
V
DD
DD
DD
DD
Input Voltage High, V
Input Current Low, I
, V
INHx OEHx
1.4
-50
-2
, I
20
1
50
2
nA
µA
INLx OELx
Input Current High, I
NOTES:
, I
INHx OEHx
4. V
= Input voltage to perform proper function.
logic
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range
8. r
ON
matching between channels is calculated by subtracting the channel with the highest max r
value from the channel with lowest max r
ON ON
value, between NCx or NOx.
9. Limits established by characterization and are not production tested.
FN6825.0
December 26, 2008
6
ISL54230
Test Circuits and Waveforms
V
V
DD
DD
C
C
50Ω SIGNAL
GENERATOR
NO OR NC
r
= V /Icom
1
ON
NOx OR NCx
IN
0V OR V+
V
NO/NC
INx
V
1
COM
Icom
ANALYZER
GND
VIN
COMx
GND
R
L
Signal direction through switch is reversed, worst case values
are recorded.
Repeat test for all switches.
FIGURE 2. OFF-ISOLATION TEST CIRCUIT
FIGURE 1. r
TEST CIRCUIT
ON
V
V
DD
DD
C
C
50Ω SIGNAL
GENERATOR
NOx/NCx
R
NO1/NC1
INx
COM
L
1
INx
IMPEDANCE
ANALYZER
0V OR
VDD
VIN
COMx
NOx/NCx
COMx
ANALYZER
NC
GND
GND
50Ω
COM is connected to NO or NC
during ON capacitance measurement.
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 3. CAPACITANCE TEST CIRCUIT
FIGURE 4. CROSSTALK TEST CIRCUIT
V
DD
NOx OR NCx
A
5.25V
INx
COMx
GND
NOTE: OEx such that switch is disabled
FIGURE 5. POWER OFF LEAKAGE TEST CIRCUIT
FN6825.0
December 26, 2008
7
ISL54230
Test Circuits and Waveforms (Continued)
V
DD
C
t
ri
90%
50%
10%
90%
V
INx
INx
DIN+
DIN-
NO2A
OR NC2A
t
skew_i
15.8Ω
OUT+
COM2A
COM2B
DIN+
DIN-
50%
10%
45Ω
143Ω
15.8Ω
C
L
NO2B
OR NC2B
OUT-
t
fi
t
ro
45Ω
C
143Ω
L
90%
10%
90%
50%
50%
10%
OUT+
OUT-
GND
t
skew_o
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals.
|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
t
f0
FIGURE 6A. MEASUREMENT POINTS
FIGURE 6B. TEST CIRCUIT
FIGURE 6. SKEW TEST
Power Supply Considerations
Detailed Description
The power supply connected to the V
and GND pins
The ISL54230 is a multiprotocol switch containing eight
switches configured as a Quad DPDT. Each DPDT switch is
independently controlled by a logic pin. The ISL54230 has
four switches that are compliant in passing USB2.0 signals
DD
provides the DC bias voltage necessary to operate the IC.
The ISL54230 can be operated with a supply voltage in the
range of +2.0V to +5.5V. For USB applications the supply
voltage should be in the range of +3.0V to +5.5V to ensure
proper signal levels on the USB data lines.
and four switches with low r
that can be used to pass
ON
analog or digital signals such as audio or UART. It is offered
in a 32 Ld 5x5mm TQFN package for applications which
require small package size such as cellphones and PDAs.
A decoupling capacitor in the range 0.01µF to 0.1µF should
be connected to the V
supply pin of the IC to filter out any
DD
power supply noise that may be present on the supply lines.
The capacitor should be place as closed as possible to the
The ISL54230 contains four switches capable of passing
USB2.0 Full-Speed and High-Speed signals with minimal
distortion, two 1Ω switches and two 6Ω switches for
analog/digital signals. The USB capable switches were
designed with low capacitance and high bandwidth to pass
USB HS signals (480Mbps) with minimal edge and phase
distortion. The 1Ω switches are designed for passing low
bandwidth signals (<8MHz) and are ideal for switching
power lines since the low ON-resistance minimizes power
dissipation. The 6Ω switches are designed to pass audio or
V
pin.
DD
Supply Sequencing and Power-On Reset
Protection
Proper power supply sequencing is necessary to protect the
ISL54230 from operating in fault conditions. The ISL54230
integrates Power-On Reset (POR) circuitry that prevents the
switches from turning ON until the supply voltage is at least
+1.4V. The POR has a 100mV hysteresis built in that will turn
the switches OFF when the supply has gone below +1.3V.
This function prevents signals from the switch input being
passed to the output when the device operating voltage has
not reached appropriate levels yet, protecting the switch
from fault conditions.
data signals up to 100MHz while maintaining a low r
for
ON
good THD performance.
In addition to the four independent logic control pins that
control each DPDT switch, the ISL54230 contains two
Output Enable (OE) logic pins that permits the IC to disable
certain switches giving the user a high degree of flexibility in
signal routing. Please see “OE Control Truth Table” on
page 3 for an explanation of the OE pins. All logic pins on
the ISL54230 are 1.8V logic compatible up to a +3.3V
supply.
The POR circuitry also protects the switch from operating in
a fault condition should the power supply to the IC drop
below the POR threshold. Thus, the recommended
operational supply voltage is within +2.0V to +5.5V.
Operating at supply voltages below +2.0V may still be
functional but the noise margin between the POR threshold
FN6825.0
December 26, 2008
8
ISL54230
and supply voltage will be reduced. The device may
unexpectedly shut down if transient voltages trigger the
POR.
The two 6Ω switches are bi-directional analog switches that
can pass rail-to-rail signals, making them well suited for
analog or digital signal routing such as audio, UART or
Full-Speed USB.
Overvoltage and Short Circuit Considerations
The ISL54230 should be protected from overvoltage
conditions. The IC contains ESD protection diodes that are
back biased from the switch terminals to ground. Negative
voltages on the switch terminals that are large enough to
forward-bias these ESD protection diodes will result in a
large current flowing from ground that may destroy these
diodes. Thus signals on the switch terminals should not
swing below ground and cannot exceed the specified
“Absolute Maximum Ratings” on page 4 for safe operation.
The low ON-resistance of these switches are well suited for
passing audio signals with good THD performance, even
with low impedance loads such as 32Ω headphones
(see Figure 24 for THD performance curves).
Logic Control Pins
The ISL54230 contains six logic control pins, IN1 through
IN4 for independently controlling each DPDT switch and two
OE enable pins. The logic control pins determine the state of
the switches. Refer to the “Input Select” and “OE Control”
Truth Tables on page 3.
The ISL54230 can have signals that go above the positive
supply rail with no adverse effects up to +5.5V. The ESD
protection circuitry permits the signal from going beyond the
When the OEx control pins are logic LOW, only the switches
on COM2x and COM3x are active and the switch state
determined by IN2 and IN3 respectively. When the OEx
control pins are logic HIGH, all switches are active and the
switch state determined by the INx control pins.
V
supply (even with V
= 0V) without inducing large
DD
DD
leakage currents on the switch pins when the supply voltage
is less than +5.5V. This feature complies with the USB 2.0
Specifications for short circuit protection in the event that the
5.25V V
BUS
line shorts to the USB signal lines.
When the OEx control pins are in opposing logic states
either COM1x and COM2x are active or COM3x and COM4x
are active depending on what states OE1 and OE2 are at.
The active switches are controlled by the respective INx
control pin. This feature is useful for applications that
interface the ISL54230 to Master/Slave devices or
controlling two SIM cards in Dual SIM Card cellphones. The
OEx control pins permit total deactivation of each half of the
switch blocks to disable devices connected to those
switches.
Note: When the supply voltage is above the POR threshold
but below the V voltage and a V fault conditions
occurs, the V
the switch if the logic control pins are biased such that the
switch is turned ON.
BUS BUS
signal will be passed to the other side of
BUS
USB Switches (COM2x and COM3x)
The four USB FS and HS capable switches are bi-directional
analog switches that can pass rail-to-rail signals with
minimal distortion. With a 3.0V power supply these switches
have a nominal ON-resistance of 6Ω in the 0V to 400mV
signal range. The low capacitance and high bandwidth of the
switches makes them ideal for USB applications. They are
specifically designed to pass both USB FS (12Mbps) and
USB HS (480Mbps) differential signals while meeting the
USB 2.0 signal quality eye diagrams (Figures 25 and 26).
LOGIC CONTROL VOLTAGE LEVELS
OEx = Logic “0” (Low) when V
OEx
≤ 0.5V
≥ 1.4V
OEx = Logic “1” (High) when V
OEx
INx = Logic “0” (Low) when V
INx
≤ 0.5V
≥ 1.4V
INx = Logic “1” (High) when V
INx
The logic control pins are +1.8V CMOS logic compatible (0.45V
V and 1.35V V ) for supply voltages from +1.8V to
OLMAX
The USB switches are designed with integrated protection
circuitry for fault conditions as defined in the USB 2.0
OHMIN
+3.6V. over a supply range of 1.8V to 3.3V (see Figure 23). At
Specifications-Section 7.1.1. If a condition where V
3.6V the V level is 0.5V maximum. This is still below the 1.8V
BUS
IL
(5.25V) is shorted to the D+ or D- pin this will not damage
CMOS guaranteed low output maximum level of 0.45V, but
the device, even without power to the IC.
noise margin is reduced. At 3.6V the V level is 1.4V minimum.
IH
While this is above the 1.8V CMOS guaranteed high output
minimum of 1.35V under most operating conditions the switch
will recognize this as a valid logic high.
1Ω Switches (COM1A and COM4A) And 6Ω
Switches (COM1B and COM4B)
The two 1Ω switches are bi-directional analog switches that
can pass rail-to-rail signals, making them well suited for
analog or digital signal routing. The low ON-resistance of the
switches makes them ideal for switching ON/OFF power
supply lines for applications that interface with devices that
require power (ie: SIM cards or flash memory devices). With
a ON-resistance of 1Ω the power dissipation through the
switch is minimal.
The digital input stages draws a larger supply current whenever
the digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation. The ISL54230 has been
designed to minimize the supply current whenever the digital
input voltage is not driven to the supply rails (0V to V+). For
example driving the device with 1.8V logic high while
operating with a 3.6V supply the device draws only 1µA of
current.
FN6825.0
December 26, 2008
9
ISL54230
Application Block Diagram
MAIN
V
DD
MICROPHONE
NO1A
COM1A
IN1
NC1A
NO1B
COM1B
EAR BUD
MICROPHONE
NC1B
BASEBAND
CODEC
NO2A
NC2A
NO2B
NC2B
COM2A
IN2
COM2B
MULTIMEDIA
CODEC
NO3A
USB
TRANSCEIVER A
COM3A
IN3
NC3A
NO3B
COM3B
USB
TRANSCEIVER B
NC3B
NO4A
COM4A
IN4
AUDIO
CODEC A
NC4A
NO4B
COM4B
OE1
NC4B
GND
AUDIO
CODEC B
OE2
µCONTROLLER
OR
BASEBAND
PROCESSOR
Typical Performance Curves T = +25°C, Unless Otherwise Specified
A
10
8.0
V
= 3.0V
DD
T = +25°C
9
8
7
6
5
4
3
I
= 40mA
COM
7.5
7.0
6.5
6.0
5.5
5.0
4.5
I
= 40mA
COM
+85°C
+2.7V
+3V
+25°C
-40°C
+3.6V
0
0.05
0.15
0.25
(V)
0.35
0.45
0.10
0.20
COM
0.30
0.40
0
0.05
0.15
0.25
(V)
0.35
0.45
0.10
0.20
V
0.30
0.40
V
COM
FIGURE 7. ON-RESISTANCE vs SWITCH VOLTAGE; COM2x
AND COM3x
FIGURE 8. ON- RESISTANCE vs SWITCH VOLTAGE, COM2,
COM3
FN6825.0
December 26, 2008
10
ISL54230
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
160
140
120
100
80
160
140
120
100
80
V
= 3.0V
= 1mA
DD
T = +25°C
= 1mA
I
COM
I
COM
+85°C
+25°C
+2.7V
-40°C
+3V
60
60
+3.6V
40
40
20
20
0
0
0
0.5
1.0
1.5
V
2.0
(V)
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
4.0
V
COM
COM
FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE; COM2x
AND COM3x
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE; COM2x
AND COM3x
2.50
2.50
T = +25°C
V
= 3.0V
DD
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
I
= 100mA
COM
I
= 100mA
COM
+85°C
+2.7V
+3V
+3.6V
+25°C
-40°C
0
0.5
1.0
1.5
V
2.0
(V)
2.5
3.0
3.5
0
0.5
1.0
1.5
V
2.0
(V)
2.5
3.0
3.5
4.0
COM
COM
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE;, COM1A
AND COM 4A
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE; COM1A
AND COM4A
12
12
V
= 3.0V
T = +25°C
DD
11
10
9
11
10
9
I
= 100mA
COM
I
= 100mA
COM
+85°C
8
8
+2.7V
+3V
7
+25°C
-40°C
7
6
6
+3.6V
5
5
4
4
3
3
0
0.5
1.5
2.5
3.5
1.0
2.0
(V)
3.0
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
4.0
V
COM
V
COM
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE; COM1B
AND COM4B
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE; COM1B
AND COM4B
FN6825.0
December 26, 2008
11
ISL54230
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1
V
= 3.0V
= 50mV
= 50Ω
DD
0
V
IN
RMS
-1
R
L
-2
-3
-4
-5
-6
V
= 3.0V
DD
V
R
= 0dBm 100mV
OFFSET
DC
IN
= 50Ω
L
1M
10M
100M
1G
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY(Hz)
FIGURE 15. FREQUENCY RESPONSE; COM2x and COM3x
FIGURE 16. OFF-ISOLATION; COM2x and COM3x
0
1
0
V
= 3.0V
DD
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
V
= 50mV
IN
RMS
R
= 50Ω
L
-1
-2
-3
V
= 3.0V
DD
-4
V
R
= 50mV
IN
RMS
= 50Ω
L
-5
1M
1k
10k
100k
1M
10M
100M
10M
100M
1G
FREQUENCY(Hz)
FREQUENCY (Hz)
FIGURE 18. OFF-ISOLATION; COM1A AND COM4A
FIGURE 17. FREQUENCY RESPONSE; COM1A AND COM4A
0
1
0
-10
-20
-30
-40
-50
-60
-70
-8 0
-90
-100
V
= 3.0V
DD
V
= 50mV
IN
RMS
R
= 50Ω
L
-1
-2
-3
V
= 3.0V
DD
V
= 50mV
IN
RMS
-4
R
= 50Ω
L
-5
1M
10M
100M
1G
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 19. FREQUENCY RESPONSE; COM1B and COM4B
FIGURE 20. OFF-ISOLATION; COM1B and COM4B
FN6825.0
December 26, 2008
12
ISL54230
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
0
0
V
= 3.0V
V
= 3.0V
DD
DD
-20
-20
V
= 0dBm
V
= 0dBm
IN
IN
COM3A TO COM4A
= 50
COM3A TO COM4B
R = 50Ω
R
Ω
-40
-40
L
L
-60
-60
-80
-80
-100
-100
-120
1M
-120
1M
10M
100M
1G
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 22. CROSSTALK
FIGURE 21. CROSSTALK
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
COM1B AND COM 4B
V
= 3.3V
DD
V
R
= 100mV
WITH 1.5VDC OFFSET
RMS
IN
= 32Ω
L
COM1A AND COM 4A
100 200
20
1k
2k
10k 20k
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
FIGURE 24. TOTAL HARMONIC DISTORTION vs FREQUENCY
FIGURE 23. LOGIC INPUT THRESHOLD VOLTAGE vs SUPPLY
VOLTAGE
FN6825.0
December 26, 2008
13
ISL54230
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
V
= 3.3V
DD
TIME SCALE (10ns/DIV)
FIGURE 25. EYE PATTERN: 12Mbps; COM2x or COM3x SWITCH IN THE SIGNAL PATH
FN6825.0
December 26, 2008
14
ISL54230
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
V
= 3.3V
DD
TIME SCALE (0.2ns/DIV)
FIGURE 26. EYE PATTERN: 480Mbps; COM2x or COM 3x SWITCH IN THE SIGNAL PATH
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
1216
PROCESS:
Submicron, Dual Gate, Analog CMOS
FN6825.0
December 26, 2008
15
ISL54230
Thin Quad Flat No-Lead Plastic Package (TQFN)
Thin Micro Lead Frame Plastic Package (TMLFP)
2X
L32.5x5A
0.15
C A
32 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220WJJD-1 ISSUE C)
D
A
D/2
MILLIMETERS
SYMBOL
MIN
0.70
-
NOMINAL
MAX
0.80
0.05
NOTES
A
A1
A3
b
0.75
-
2X
N
0.15 C
B
6
-
0.20 REF
0.25
-
INDEX
AREA
1
2
3
-
E/2
0.18
3.30
0.30
3.55
5, 8
E
B
D
5.00 BSC
3.45
-
D2
E
7, 8
5.00 BSC
5.75 BSC
3.45
-
E1
E2
e
9
TOP VIEW
3.30
3.55
7, 8
0.50 BSC
-
-
k
0.20
0.30
-
-
A
/ /
0.10 C
0.08 C
L
0.40
0.50
8
C
N
32
2
Nd
Ne
8
3
SEATING PLANE
A1
A3
SIDE VIEW
8
3
Rev. 2 05/06
5
NX b
NOTES:
0.10 M C A B
1. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
2. N is the number of terminals.
D2
8
7
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
NX k
D2
2
(DATUM B)
(DATUM A)
N
(Ne-1)Xe
REF.
6
E2
INDEX
AREA
7
8
E2/2
3
2
1
NX L
N
e
8
(Nd-1)Xe
REF.
BOTTOM VIEW
A1
NX b
5
SECTION "C-C"
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6825.0
December 26, 2008
16
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