ISL54301IRZ [RENESAS]
QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PQCC20, 4 X 4 MM, ROHS COMPLIANT, PLASTIC, QFN-20;
| 型号： | ISL54301IRZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PQCC20, 4 X 4 MM, ROHS COMPLIANT, PLASTIC, QFN-20 输出元件 |
| 文件： | 总17页 (文件大小：589K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL54301
®
Data Sheet
March 18, 2008
FN6591.0
12V, 1.5Ω Quad SPST Switch with Serial
Daisy Chain Interface
Features
• 4 independently controlled SPST switches
• On-resistance @ 12V . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5Ω
• Single or split supply voltage operation
The ISL54301 is a quad analog bidirectional switch device
targeted at industrial applications, including test and
measurement equipment. It features low resistance and low
leakage along with a 12V operation and can be digitally
controlled via a latched serial interface. This serial interface
features a buffered and retimed clock output pin that can be
used to connect multiple devices into a daisy chained
arrangement with minimal data to clock skew up to a serial
data rate exceeding 40MHz.
• r
• r
flatness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <1Ω
matching between channels . . . . . . . . . . . . . . . . . <0.2Ω
ON
ON
• Turn-on/turn-off time . . . . . . . . . . . . . . . . . . . . . . . 25ns/80nS
• Switch bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60MHz
• Serial data interface up to 40MHz
• 3V logic interface
The ISL54301 can operate from a single, or split bipolar
power supply and has a 3V logic interface. The ISL54301 is
specified for use over the -40°C to +85°C temperature range
and is available in a 20 Ld 4x4 QFN Pb-free package.
• 20 Ld QFN package
• Pb-free (RoHS compliant)
Table 1 summarizes the performance of this family.
Related Literature
TABLE 1. FEATURES AT A GLANCE
• TB363 “Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)”
CONFIGURATION
QUAD SPST
2.5Ω
r
ON
• TB389 “PCB Land Pattern and Surface Mount Guidelines
for QFN Packages”
t
/t
25ns/80ns
20 Ld QFN 4x4
ON OFF
Package
• AN557 “Recommended Test Procedures for Analog
Switches”
Pinout
Ordering Information
ISL54301
PART NUMBER
(Note)
PART
TEMP.
PACKAGE
(Pb-free)
PKG.
DWG. #
(20 LD QFN)
TOP VIEW
MARKING RANGE (°C)
ISL54301IRZ*
54 301IRZ
-40 to +85 20 Ld QFN
L20.4x4C
*Add “T” suffix for tape and reel. Please refer to TB347 for details on reel
specifications.
20 19 18 17 16
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
2B
3A
3B
4A
4B
NC
1
2
3
4
5
15
14
13
12
11
2A
1B
1A
CS_PULSE
ISL54301 Block Diagram
CS_PULSE
DATA_IN
6
7
8
9
10
CLK_IN
VPLUS
VDD
A
VLOGIC
LEVEL
SHIFTER
GND
B
CLK_OUT
DATA_OUT
VSS
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL54301
Pin Descriptions
PIN NUMBER
PIN NAME
2B
PIN DESCRIPTION
1
2
Switch 2 signal terminal
Switch 2 signal terminal
Switch 1 signal terminal
Switch 1 signal terminal
Chip select input
2A
3
1B
4
1A
5
CS_PULSE
DATA-IN
CLK-IN
GND
6
Serial data input
7
Serial cock input
8
Device ground terminal
Buffered clock output
Buffered serial data output
Not internally connected
Switch 4 signal terminal
Switch 4 signal terminal
Switch 3 signal terminal
Switch 3 signal terminal
Positive analog power supply
Logic supply voltage
9
CLK-OUT
DATA-OUT
NC
10
11, 20
12
13
14
15
16
17
18
19
4B
4A
3B
3A
VPLUS
VLOGIC
VDD
Level shifter supply voltage
Negative analog power supply
VSS
FN6591.0
March 18, 2008
2
ISL54301
Absolute Maximum Ratings
Thermal Information
VPLUS to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5V
VLOGIC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5V
VSS to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4V to 0.3V
VPLUS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V
All Other Pins (Note 1). . . . . . . . ((VSS) - 0.3V) to ((VPLUS) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 35mA
Peak Current, 1A-4A,1B-4B
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . 100mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>3kV
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Resistance (Typical)
θ
(°C/W)
38
θ
(°C/W)
3.8
JA
JC
20 Ld QFN Package (Notes 2, 3) . . .
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Analog Switch Signal Range . . . . . . . VSS + 0.5V to VPLUS - 0.5V
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Signals on 1A-4A,1B-4B, exceeding VPLUS or VSS are clamped by internal diodes. DATA_IN, CLOCK_IN, CS_Pulse exceeding VLOGIC or
VSS are clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
3. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Test Conditions: VPLUS = +9V, VSS = -3V Supply, VLOGIC = 3V, VDD = GND = 0V, V
= 2.2V, V
= 0.8V,
INH
INL
Unless Otherwise Specified.
TEMP
(°C)
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
(Note 12) (Note 10) (Note 12) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-resistance, r
I
= 10mA, VXA, VXB within analog signal
COM
25
Full
25
2.0
2.5
0.2
0.3
0.4
0.6
15
Ω
Ω
ON
(see Figure 4)
r
Matching Between Channels,
I
= 10mA, VXA, VXB within analog signal range
Ω
ON
Δr
COM
(Note 5)
ON
Full
25
Ω
r
Flatness, r
FLAT(ON)
I
= 10mA, VXA, VXB within analog signal range
COM
Ω
ON
(Note 4)
Full
25
Ω
OFF Leakage Current, I
VXA, VXB within analog signal range
nA
nA
NO(OFF)
Full
-200
2.2
+200
0.8
DIGITAL INPUT CHARACTERISTICS (Note 11)
Input Voltage High, Digital Interface Data-In, Clock-In, CS_PULSE
Input Voltage Low, Digital Interface Data-In, Clock-In, CS_PULSE
Minimum Clock Low Time
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.75
1.75
12.5
12.5
1
V
V
ns
ns
ns
ns
µA
ns
ns
Minimum Clock High Time
Data-In to Clock Setup Time
Data-In to Clock Hold Time
t
t
and t
, (Note 6, Figure 5)
SETUP1
SETUP2
, (Note 6, Figure 5)
HOLD2
and t
3.5
0.01
3
HOLD1
= 0V or VLOGIC
Input Current, I
, I
CS_PULSE Rise, Fall Time
V
-1
1
INH INL
IN
10% to 90% and 90% to 10%: (Note 6)
CS_PULSE Minimum Pulse Width Rising to Falling Edge 50% Points: (Note 6)
10
DIGITAL OUTPUT CHARACTERISTICS (Note 11)
High, Digital Interface
Low, Digital Interface
Data-Out, Clock-Out @ 1mA: (Notes 7, 8)
Data-In, Clock-Out @ 1mA: (Notes 7, 8)
Full
Full
3.1
0.2
V
V
0.4
FN6591.0
March 18, 2008
3
ISL54301
Electrical Specifications Test Conditions: VPLUS = +9V, VSS = -3V Supply, VLOGIC = 3V, VDD = GND = 0V, V
Unless Otherwise Specified. (Continued)
= 2.2V, V
= 0.8V,
INH
INL
TEMP
(°C)
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
(Note 12) (Note 10) (Note 12) UNITS
Clock-In to Clock-Out propagation (Notes 6, 7, 8)
Delay
20
ns
SWITCH DYNAMIC CHARACTERISTICS
Turn-ON Time, t
VXA, VXB = 3V, R = 300Ω, C = 35pF, V = 0V to 3V,
IN
(see Figure 1)
25
Full
25
50
55
ns
ns
ON
L
L
Turn-OFF Time, t
VXA, VXB = 3V, R = 300Ω, C = 35pF, V = 0V to 3V,
IN
90
ns
OFF
L
L
(see Figure 1)
Full
25
95
ns
OFF-Capacitance, C
f = 1MHz, VXA or VXB = 0V
f = 1MHz, VXA or VXB = 0V
50
pF
pF
dB
dB
MHz
pC
OFF
ON-Capacitance, C
25
100
-45
-65
60
COM(ON)
OFF-Isolation
R
= 50Ω, C = 15pF, f = 1MHz,
25
L
L
VXA or VXB = 1V
(see Figure 3)
P-P
Crosstalk (Note 5)
25
Switch Contact 3dB Bandwidth
Charge Injection, Q
R
C
= 50Ω, C = 5pF
L
L
L
= 1.0nF, V = 0V, R = 0Ω, (see Figure 2)
25
125
G
G
POWER SUPPLY CHARACTERISTICS
VPLUS Supply, I (Quiescent)
25
Full
25
15
17
18
22
16
22
1
µA
µA
µA
µA
µA
µA
mA
mA
µA
µA
mA
mA
µA
µA
mA
mA
45
50
10
10
VPLUS Supply, I (40MHz)
VSS Supply, I (Quiescent)
VSS Supply, I (40MHz)
VDD Supply, I (Quiescent)
VDD Supply, I (40MHz)
Full
25
Full
25
Full
25
1
1
Full
25
4
0.4
0.4
0
Full
25
VLOGIC Internal Logic Supply, I
(Quiescent)
Full
25
1
VLOGIC Internal Logic Supply, I
(40MHz)
(Note 9)
3.5
3.5
Full
FN6591.0
March 18, 2008
4
ISL54301
Electrical Specifications Test Conditions: VPLUS = +7V, VSS = 0V Supply, VLOGIC = 3V, VDD = 3V, GND = 0V, V
= 2.2V,
INH
V
= 0.8V, Unless Otherwise Specified
INL
TEMP
(°C)
MIN
TYP
MAX
PARAMETER
ANALOG SWITCH CHARACTERISTICS
TEST CONDITIONS
(Note 12) (Note 10) (Note 12) UNITS
ON-resistance, r
I
= 10mA, VXA, VXB within Analog Signal Range
25
Full
25
2.7
3.5
0.1
0.15
0.5
0.6
3
Ω
Ω
ON
COM
(see Figure 4)
r
Matching Between Channels,
I
= 10mA, VXA, VXB within Analog Signal Range
Ω
ON
Δr
COM
(Note 5)
ON
Full
25
Ω
r
Flatness, r
FLAT(ON)
I
= 10mA, VXA, VXB within Analog Signal Range
COM
Ω
ON
(Note 4)
Full
25
Ω
Off Leakage Current, I
VXA = 1V, 4.5V, VXB = 4.5V, 1V
nA
nA
NO(OFF)
Full
-200
2.2
30
200
0.8
DIGITAL INPUT CHARACTERISTICS (Note 11)
Input Voltage High, Digital Interface Data-In, Clock-In, CS_PULSE
Input Voltage Low, Digital Interface Data-In, Clock-In, CS_PULSE
Minimum Clock Low Time
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.75
1.75
12.5
12.5
1
V
V
ns
ns
ns
ns
µA
ns
ns
Minimum Clock High Time
Data-In to Clock Setup Time
Data-In to Clock Hold Time
t
t
and t
, (Note 6, Figure 5)
SETUP1
SETUP2
, (Note 6, Figure 5)
HOLD2
and t
3.5
0.01
3
HOLD1
= 0V or VLOGIC
Input Current, I
, I
V
-1
1
INH INL
IN
10% to 90% and 90% to 10%: (Note 6)
CS_PULSE Rise, Fall Time
CS_PULSE Minimum Pulse Width Rising to Falling Edge 50% Points: (Note 6)
10
DIGITAL OUTPUT CHARACTERISTICS (Note 11)
High, Digital Interface
Low, Digital Interface
Data-Out, Clock-Out at 1mA: (Notes 7, 8)
Data-In, Clock-Out at 1mA: (Notes 7, 8)
Full
Full
3.1
0.2
20
V
V
0.4
Clock-In to Clock-Out Propagation (Notes 6, 7, 8)
Delay
ns
SWITCH DYNAMIC CHARACTERISTICS
Turn-ON Time, t
VXA or VXB = 3V, R = 300Ω, C = 35pF,
(see Figure 1)
25
Full
25
25
30
ns
ns
ON
L
L
Turn-OFF Time, t
VXA or VXB= 3V, R = 300Ω, C = 35pF,
80
ns
OFF
L
L
(see Figure 1)
Full
25
85
ns
OFF-Capacitance, C
f = 1MHz, VXA or VXB = V
f = 1MHz, VXA or VXB = V
= 0V
50
pF
OFF
COM
COM
ON-Capacitance, C
OFF-Isolation
= 0V
25
100
-45
-65
60
pF
COM(ON)
R
= 50Ω, C = 15pF, f = 1MHz,
25
dB
dB
MHz
pC
L
L
VXA or VXB = 1V , (see Figure 3)
P-P
Crosstalk (Note 5)
25
Switch Contact 3dB Bandwidth
Charge Injection, Q
R
C
= 50Ω, C = 5pF
25
L
L
L
= 1.0nF, V = 0V, R = 0Ω, (see Figure 2)
25
25
G
G
FN6591.0
March 18, 2008
5
ISL54301
Electrical Specifications Test Conditions: VPLUS = +7V, VSS = 0V Supply, VLOGIC = 3V, VDD = 3V, GND = 0V, V
= 2.2V,
INH
V
= 0.8V, Unless Otherwise Specified (Continued)
INL
TEMP
(°C)
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
(Note 12) (Note 10) (Note 12) UNITS
POWER SUPPLY CHARACTERISTICS
VPLUS Supply, I (Quiescent)
25
Full
25
13
15
18
20
14
19
0.7
0.7
1
µA
µA
µA
µA
µA
µA
mA
mA
µA
µA
mA
mA
µA
µA
mA
mA
45
50
10
10
VPLUS Supply, I (40MHz)
VSS Supply, I (Quiescent)
VSS Supply, I (40MHz)
VDD Supply, I (Quiescent)
VDD Supply, I (40MHz)
Full
25
Full
25
Full
25
Full
25
4
0.4
0.5
0
Full
25
VLOGIC Internal Logic Supply, I
(Quiescent)
(Note 9)
Full
25
1
VLOGIC Internal Logic Supply, I
(40MHz)
(Note 9)
3.2
3.2
Full
NOTES:
4. Flatness is defined as the delta between the maximum and minimum r
5. Between any two switches.
values over the specified voltage range.
ON
6. CS_Pulse must remain low when performing serial operations (Toggling Clock-In). Only after all serial transfers are completed should CS_Pulse
be toggled. Likewise, while CS_Pulse is being toggled, it is important to keep Clock -In and Data-In in a low logic state.
7. Clock-Out is a manufactured pulse internally produced by the ISL54301. Regardless of Clock-In pulse width, Clock-Out will always be ~10ns in
width. Capacitive loading on Clock-Out and Data-Out should be kept to a minimum.
8. Clock-Out and Data-Out relationship is kept constant so multiple units can be cascaded. Propagation delay of Data-Out is controlled so that
Clock-Out will reach the next device before Data-Out changes. This assures long serial-chain capability and removes the need for a “High
Current Master Clock”. The delay of Data/Clock In-to-Out also reduces simultaneous switching noise.
9. Typical value is based on design simulation. VLOGIC dynamic current drain is greatly influenced by frequency and capacitive loading. VLOGIC
40MHz currents based on Data-out and Clock-loads of ~10pF load.
10. Limits established by characterization and are not production tested.
11. Digital Characteristics remain stable with respect to VPLUS and VSS variation. These parameters are controlled by the difference between VSS
and VDD which the user should maintain at a constant spread of VDD = VSS + 3V.
12. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
FN6591.0
March 18, 2008
6
ISL54301
Test Circuits and Waveforms
3V
t < 20ns
r
t < 20ns
f
VPLUS
VDD
VLOGIC
C
C
C
CS_PULSE
C
50%
INPUT
0V
t
ON
V
1-4A
OUT
V
1-4B
OUT
V
NB
SWITCH
INPUTS
IN
25%
75%
SERIAL LATCH
GND
V
NB
C
R
L
L
SWITCH
OUTPUT
35pF
300Ω
DATA AND
CLK INPUT
t
OFF
C
V
OUT
V
VSS
NB
Repeat test for all switches. C includes fixture and stray
L
capacitance.
R
L
+ r
ON
-----------------------
L
V
= V
Switch changes state on rising edge of CS_PULSE. V
all times.
= V
at
OUT
OUT
(NB)
NA
R
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
VPLUS
VDD
VLOGIC
C
C
C
SWITCH
OUTPUT
DV
OUT
V
R
OUT
G
1-4A
1-4B
V
OUT
SHIFT REGISTER
GND
3V
ON
ON
V
G
IN
OFF
C
L
0V
CONTROLLER
SEQUENCE
C
Q = DV
x C
L
SW: ON/OFF/ON
OUT
VSS
Repeat test for all switches. C includes fixture and stray
L
capacitance.
Switch changes state on rising edge of CS_PULSE.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
VPLUS
VDD
VLOGIC
C
VPLUS
VDD
VLOGIC
C
C
C
C
C
r
= V /10mA
1
ON
SIGNAL
GENERATOR
1-4A
1-4B
1-4A
1-4B
V
XA
SERIAL
CLOCK/DATA
SERIAL
CLOCK/DATA
10mA
V
1
ANALYZER
GND
GND
R
L
C
C
VSS
VSS
Repeat test for all switches.
Repeat test for all switches.
FIGURE 4. r
FIGURE 3. OFF-ISOLATION TEST CIRCUIT
TEST CIRCUIT
ON
FN6591.0
March 18, 2008
7
ISL54301
Test Circuits and Waveforms (Continued)
DATA-IN AND CLOCK-IN SHOULD REMAIN LOW, BEFORE DURING AND AFTER CS_PULSE
CS_PULSE
INPUT
t
PULSE
DATA = 1
100%
100%
DATA-IN
DATA = 0
t
HOLD2
t
SETUP2
t
SETUP1
SW3
SW2
50%
CLK-IN
t
SW1
HOLD1
FIGURE 5. SETUP AND HOLD TIMES
ISL54301 Serial Communications and Cascade
ISL54301 Detailed Description
The ISL54301 operates based on synchronous serial data.
Data and Clock inputs are 3V level compatible. Setup and
Hold times relative to the rising the edge of the clock input
must be maintained for proper operation. All serial data is
clocked through internal shift registers.
The ISL54301 Quad analog switches offer switching
capability from a split-supply (3V and +9V or single 0V and
5V to 12V). Please review “Power Supply Considerations”
on page 8 before powering up the device.
The user can employ a single or multi-device serial control
data chain. Cascading serial control make it well suited for
large scale switching systems applications.
DATA-IN/DATA-OUT
Data on the Data-Out Pin will follow the Data-In pattern, but
will be delayed for 4 clock cycles. The Data-Out function
works in tandem with the Clock-Out pin and provides a
means of programming several devices connected in series.
Power Supply Considerations
The ISL54301 construction consists of CMOS analog
switches and has four supply pins: VPLUS, VSS, VLOGIC,
VDD and GND. VPLUS and VSS determine the switch
voltage range of the four SPST CMOS switches and set their
analog voltage limits. There are no connections between the
switch contact signal path and GND.
CLOCK IN/CLOCK OUT
The Clock Output is derived from the Clock Input and
delayed to compensate for internal latch propagation delay.
Use of the Clock Output enables the user to cascade scores
of devices without concern for clock phase skew or large
clock distribution loading.
VLOGIC and GND power the digital input/output logic level
shifters. The level shifters convert the external logic levels to
VDD and VSS signals to drive the internal digital circuitry.
Clock out is an internally generated pulse which occurs
~20ns after the rising edge of Clock-In. The Clock-Out pin is
a pulse that is sensitive to capacitive loading. Figure 36
shows the influence of various loads. The user should keep
PCB trace lengths of Data-Out and Clock-Out to a minimum.
VDD and VSS power the internal logic of the device. VDD
must always be held at a fixed 3V above VSS to avoid
device damage.
Whether operating split or single device, Gnd will
always be @ 0V, VLOGIC will always be @ 3V.
ISL54301 Operation and Control
The ISL54301 utilizes two levels of serial to parallel latch
circuitry. During serial information transmission, only the
primary register is affected. Once serial communications is
completed, a secondary 4-bit latch/register can receive the
new data. The information contained in the secondary latch
controls the switch state of the ISL54301 switches. The pin
controlling the transfer of information from the primary to the
secondary registers is the CS_Pulse pin.
VDD should always remain 3V above VSS. VSS to
VPLUS should not exceed a maximum spread of more
than 12V. For example:
SPLIT POSITIVE AND NEGATIVE SWITCH RANGE
OPERATION:
• VSS = -3V, VDD = +0V, VPLUS = +9V, VLOGIC = 3V
• VSS = -1V, VDD = +2V, VPLUS = +11V, VLOGIC = 3V
In general, for test vector verification and diagnostics,
primary registers can be looped-back with the
Data Out/ Clock Out Pins.
POSITIVE SWITCH RANGE OPERATION:
• VSS = 0V, VDD = +3V, VPLUS = +12V, VLOGIC = 3V
FN6591.0
March 18, 2008
8
ISL54301
The switch from present to next operation occurs on the
ISL54301 CS_Pulse Pin Discussion
rising edge on the CS_Pulse pin. This rising edge transfers
data to the internal 4-bit switch control register. This transfer
updates open and closing of the four switches.
The ISL54301’s operational state does not change while
serial transmissions in the Primary Serial Latch Register are
occurring.The user must insure that the CS_Pulse pin
remains low and does not change state during this time.
ISL54301 Power On Reset (POR)
Once the user has loaded the Primary Register with the
intended data, the CS_Pulse pin is then utilized. Just as the
CS_Pulse pin must remain low during serial transfers, the
CLK-IN and DATA-IN pins must remain low before, during
and after the CS_PULSE operation.
Switch conditions are controlled during POR, Power On
Reset. During and after a POR condition, the switches are
opened until closed by the controller..
SERIAL DATA
SW2-B
SW2-A
SW3-A
S3 CONTROL
S2 CONTROL
SW3-B
SECONDARY
CS_PULSE
LATCHES
SECONDARY
CS_PULSE
LATCHES
SW1-B
SW1-A
SW4-A
S4 CONTROL
S1 CONTROL
SW4-B
CLOCK GEN.
LEVEL
SHIFTER
LEVEL
LEVEL
LEVEL
LEVEL
SHIFTER SHIFTER
SHIFTER SHIFTER
FIGURE 6. ISL54301 FUNCTIONAL DIAGRAM
TABLE 2. ISL54301 4-BIT SWITCH CONTROL SERIAL STREAM
Bit 4 MSB (First)
Bit 3
Bit 2
Bit 1 LSB (Last)
Switch 4 Control
Switch 3 Control
Switch 2 Control
Switch 1 Control
Refer to Figure 37 on page 16 for Scope Capture of Serial Communications
SPECIFIC POWER SEQUENCE:
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All Switch contact
I/O pins contain ESD protection diodes from the pin to
VPLUS and to VSS(see Figure 7). To prevent forward
biasing these diodes, VPLUS, GND and VSS must be
applied before any input signals, and switch signal voltages
must remain between VPLUS and VSS. Digital control
signals should be limited to VLOGIC and VSS.
1. GND
2. VSS Typical ..................... -3V to 0V with respect to GND
3. VPLUS Typical.............. +5V to +9V with respect to GND
4. VDD......................................+3.0 to with respect to VSS
5. VLOGIC....................................+3V with respect to GND
If these conditions cannot be guaranteed, then one of the
following two protection methods should be employed.
FN6591.0
March 18, 2008
9
ISL54301
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input. The resistor limits the input
current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
Logic-Level Thresholds
VLOGIC and GND power the internal logic level shifter
stages, so VPLUS and VSS have no affect on logic
thresholds. Thus Clock, Data, CS_Pulse receive thresholds
and Clock-Out, Data-Out drive levels will remain constant
despite changes VPLUS and VSS.
Adding a series resistor to the switch input defeats the purpose
of using a low r
switch, so two small signal diodes can be
ON
Leakage Considerations
added in series with the supply pins to provide overvoltage
protection for all pins (see Figure 7). These additional diodes
limit the analog signal from 1V below VPLUS to 1V above
VSS.
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both VPLUS and VSS.
One of these diodes conducts if any analog signal exceeds
VPLUS or VSS.
The leakage current performance is unaffected by this
approach, but the switch resistance may increase, especially
at low supply voltages.
ISL54301 Device Programming
Programming the device entails accessing the internal
switch control register. To write data into the register the data
must be transferred through the Primary Serial Latch.
ESD Protection
The device contains ESD protection and voltage clamps.
Clamps are design to work based on dV/dT. During
power-up, the user should review the rise and fall times on
the power connections. Rise time of the power rails should
not be faster than 1µs.
Via the CS_Pulse pin the programmer has complete control
as to “when” data is transferred to the secondary latch. Until
such time as the CS_Pulse pin is “toggled” the device will
remain as previously programmed. So data transfers
through the primary latches will not effect the switches
operational condition.
VPLUS
VDD
VLOGIC
The programmer can view multiple devices as one long
serial stream cascading from device to device and finally
back to the controller. This with each four bits controlling
each device. Again, no switch conditions will change until
CS_Pulse is toggled.
CLAMP
VSS
CLAMP
VSS
CLAMP
GND
VPLUS
ONE FOR EACH PIN LISTED: 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B,
VDD, VLOGIC
Note: If the user wishes to “loop-back” the serial data
for self-test purposes, the controller’s serial receive
shift register needs to operate off the “Clock-Out” pin of
the last device in the chain. Capacitance must be kept to
a minimum on the Clock-Out signal.
VSS
VLOGIC
If the user intends to “loop-back” the serial data, a
buffer should be placed on the final ISL54301 in the
serial chain before routing it to the system controller.
ONE FOR EACH PIN LISTED: DATA_OUT, CLK_OUT
GND
ISL54301 Programming Discussion
The amount of clock cycles is crucial to proper operation.
Data must always be synchronized with the Clock position
serially. The number of clocks must coincide with the amount
of devices in the over all chain. Each ISL54301 device must
receive 4-clock pulses.
VLOGIC
ONE FOR EACH PIN LISTED: DATA_IN, CLK_IN, CS_PULSE
Evaluation Board
GND
VSS
An evaluation board, part number ISL54301EVAL1Z, is
available to assist in assessing the ISL54301 IC’s
performance. The board’s design and software allows for
evaluation of all standard features. Refer to the evaluation
board application note for details, and contact your sales rep
for ordering information.
FIGURE 7. ESD/OVERVOLTAGE PROTECTION
FN6591.0
March 18, 2008
10
ISL54301
VPLUS (VSUB+5 TO VSUB+12V)
VLOGIC (GND + 3V)
VDD (VSUB +3V)
VSUB (-3V TO 0V)
C1
4.7µF
C2
4.7µF
C3
4.7µF
C4
4.7µF
SWITCH CONTACT
CONNECTIONS
GND
CS_PULSE IN FROM SYSTEM CONTROLLER
U1
DATA-IN FROM SYSTEM CONTROLLER
CLOCK-IN FROM SYSTEM CONTROLLER
6
7
8
9
20
19
18
17
16
DATA-IN
NC
VSS
CLK-IN
GND
CLK-OUT
DATA-OUT
VDD
VLOGIC
VPLUS
10
C5
0.1µF
C8
0.1µF
C9
0.1µF
C10
0.1µF
ISL54301
SWITCH CONTACT
CONNECTIONS
U2
DEVICE DECOUPLING
6
20
NC
DATA-IN
7
19
CLK-IN
VSS
8
18
17
16
GND
VDD
VLOGIC
VPLUS
KEEP CLOCK-OUT AND DATA-OUT
CAPACITANCE TO A MINIMUM
9
CLK-OUT
10
DATA-OUT
C6
0.1µF
C11
0.1µF
C12
0.1µF
C13
0.1µF
ISL54301
SWITCH CONTACT
CONNECTIONS
U3
6
20
NC
DATA-IN
7
19
CLK-IN
VSS
8
18
17
16
GND
VDD
VLOGIC
VPLUS
CLOCK-OUT
DATA-OUT
9
CLK-OUT
10
DATA-OUT
C7
0.1µF
C14
0.1µF
C15
0.1µF
C16
0.1µF
TO ADDITIONAL DEVICES OR SYSTEM CONTROLLER
CLOCK-OUT WILL BE ~10ns PULSE.
CLOCK-OUT AND DATA-OUT SHOULD BE
BUFFERED WHEN LOOPED BACK TO
SYSTEM CONTROLLER.
ISL54301
GND
SWITCH CONTACT
CONNECTIONS
FIGURE 8. ISL54301 SERIAL CASCADE EXAMPLE
FN6591.0
March 18, 2008
11
ISL54301
Typical Performance Curves VLOGIC = 3v, T = +25°C, V = 3v, V = 0V, Unless Otherwise Specified.
A
IH
IL
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
I
= 10mA
VSS = -3V, VPLUS = 3V, VDD = 0V
COM
+85°C
+85°C
+25°C
-40°C
+25°C
-40°C
I
= 10mA
VSS = 0V, VPLUS = 5V, VDD = 3V
COM
4
-3
-2
-1
0
1
2
3
7
9
0
1
2
3
5
V
(V)
V
(V)
COM
COM
FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
5.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
I = 10mA
COM
VSS = 0V, VPLUS = 7V, VDD = 3V
VSS = -3V, VPLUS = 7V, VDD = 0V
I
= 10mA
COM
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
+85°C
+85°C
+25°C
-40°C
+25°C
-40°C
0
1
2
3
4
5
6
7
-3
-2
-1
0
1
2
3
4
5
6
V
(V)
V
(V)
COM
COM
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
5.0
5.0
I
= 10mA
I
= 10mA
VSS = -3V, VPLUS = 9V, VDD = 0V
VSS = 0V, VPLUS = 12V, VDD = 3V
COM
COM
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.0
3.5
3.0
2.5
+85°C
+85°C
2.0
1.5
1.0
0.5
-40°C
-40°C
+25°C
+25°C
-3
-2 -1
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
(V)
8
9
10 11 12
0.0
V
V
(V)
COM
COM
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
FN6591.0
March 18, 2008
12
ISL54301
Typical Performance Curves VLOGIC = 3v, T = +25°C, V = 3v, V = 0V, Unless Otherwise Specified. (Continued)
A
IH
IL
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VSS = -3V, VPLUS = 3V, VDD = 0V
VSS = 0V, VPLUS = 5V, VDD = 3V
-3
-2
-1
0
1
2
3
7
9
0
1
2
3
4
5
V
(V)
V
(V)
COM
COM
FIGURE 15. ON-LEAKAGE vs SWITCH VOLTAGE
FIGURE 16. ON-LEAKAGE vs SWITCH VOLTAGE
5.0
5.0
VSS = 0V, VPLUS = 7V, VDD = 3V
VSS = -3V, VPLUS = 7V, VDD = 0V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
-3
-2
-1
0
1
2
3
4
5
6
V
(V)
V
(V)
COM
COM
FIGURE 18. ON-LEAKAGE vs SWITCH VOLTAGE
FIGURE 17. ON-LEAKAGE vs SWITCH VOLTAGE
5.0
5.0
VSS = 0V, VPLUS = 12V, VDD = 3V
VSS = -3V, VPLUS = 9V, VDD = 0V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
8
9
10 11 12
-3
-2 -1
0
1
2
3
4
5
6
7
8
V
(V)
V
(V)
COM
COM
FIGURE 20. ON-LEAKAGE vs SWITCH VOLTAGE
FIGURE 19. ON-LEAKAGE vs SWITCH VOLTAGE
FN6591.0
March 18, 2008
13
ISL54301
Typical Performance Curves VLOGIC = 3v, T = +25°C, V = 3v, V = 0V, Unless Otherwise Specified. (Continued)
A
IH
IL
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VSS = 0V, VPLUS = 5V, VDD = 3V
VSS = -3V, VPLUS = 3V, VDD = 0V
-3
-2
-1
0
1
2
3
0
1
2
3
4
5
V
(V)
V
(V)
COM
COM
FIGURE 21. OFF-LEAKAGE vs SWITCH VOLTAGE
FIGURE 22. OFF-LEAKAGE vs SWITCH VOLTAGE
10
10
VSS = 0V, VPLUS = 7V, VDD = 3V
VSS = -3V, VPLUS = 7V, VDD = 0V
9
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
-3
-2
-1
0
1
2
3
4
5
6
7
V
(V)
V
(V)
COM
COM
FIGURE 23. OFF-LEAKAGE vs SWITCH VOLTAGE
FIGURE 24. OFF-LEAKAGE vs SWITCH VOLTAGE
10
10
VSS = -3V, VPLUS = 9V, VDD = 0V
VSS = 0V, VPLUS = 12V, VDD = 3V
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10 11 12
-3
-2 -1
0
1
2
3
4
5
6
7
8
9
V
(V)
V
(V)
COM
COM
FIGURE 25. OFF-LEAKAGE vs SWITCH VOLTAGE
FIGURE 26. OFF-LEAKAGE vs SWITCH VOLTAGE
FN6591.0
March 18, 2008
14
ISL54301
Typical Performance Curves VLOGIC = 3v, T = +25°C, V = 3v, V = 0V, Unless Otherwise Specified. (Continued)
A
IH
IL
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
6.0
VSS = -3V, VCOM = VPLUS - 1.0V, VDD = 0V
VSS = 0V, VCOM = VPLUS - 1.0V, VDD = 3V
= 10mA
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
I
= 10mA
I
COM
COM
+25°C
+25°C
+85°C
+85°C
-40°C
-40°C
3.0
4.5
6.0
7.5
9.0
10.5
12.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
VPLUS (V)
VPLUS (V)
FIGURE 28. ON-RESISTANCE vs SUPPLY VOLTAGE
FIGURE 27. ON-RESISTANCE vs SUPPLY VOLTAGE
2.00
17.0
VSS = -3V, VDD = 0V
VSS = -3V, VDD = 0V
1.94
1.88
1.82
1.76
1.70
1.64
1.58
1.52
1.46
1.40
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
+25°C
+85°C
+85°C
+25°C
-40°C
-40°C
2.5
2.7
2.9
VPLUS (V)
3.1
3.3
3.5
3
4
5
6
7
8
9
VPLUS (V)
FIGURE 29. DIGITAL SWITCHING POINT vs SUPPLY
VOLTAGE
FIGURE 30. DEVICE QUIESCENT CURRENT (VPLUS)
60
450
VPLUS = 9V, VSS = -3V, VDD = 0V
400
50
350
300
VPLUS = 9V, VSS = -3V, VDD = 0V
40
VPLUS = 12V, VSS = 0V,
VDD = 3V
250
200
150
100
50
30
VPLUS = 7V, VSS = 0V,
VDD = 3V
20
VPLUS = 9V, VSS = 0V, VDD = 3V
10
0
0
-3 -2 -1
0
1
2
3
4
5
6
7
8
9
-3 -2 -1
0
1
2
3
4
5
6
7
8
9
10 11 12
V
(V)
COM
V
(V)
COM
FIGURE 31. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 32. t
vs VCOM
ON
FN6591.0
March 18, 2008
15
ISL54301
Typical Performance Curves VLOGIC = 3v, T = +25°C, V = 3v, V = 0V, Unless Otherwise Specified. (Continued)
A
IH
IL
0
-10
-20
-30
0
10
20
30
VPLUS = 9V, VSS = 0V, VDD = 3V
VPLUS = 9V, VSS = -3V, VDD = 0V
= 50Ω
VPLUS = 9V, VSS = 0V, VDD = 3V
VPLUS = 9V, VSS = -3V, VDD = 0V
R
R
= 50Ω
L
L
-40
40
-50
-60
50
60
-70
70
-80
80
-90
90
-100
-110
100
110
1k
10k
100k
1M
10M
100M 500M
1k
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 33. CROSSTALK
FIGURE 34. OFF ISOLATION
VPLUS = 9V
VPLUS = 5V TO 9V, VSS = 0V, VDD = 3V
0
-1
-2
-3
-4
-5
-6
-7
-8
GAIN
4.0
CLK_IN
0
3.0
2.5
2.0
1.5
1.0
0.5
0
C
= BOARD CAPACITANCE AND A C
L
T
V
= 0V, V = 3V
DD
SS
C
= 12pF
T
C
= 22pF
= 34pF
= 45pF
T
C
T
C
V
= -3V, V
= 0V
DD
T
SS
R
= 50Ω
L
CLK_OUT
10ns/DIV
V
= 0.2V to 2V
IN
P-P
P-P
10
1
100
600
FREQUENCY (MHz)
FIGURE 36. CLK-IN TO CLK-OUT DELAY
FIGURE 35. FREQUENCY RESPONSE
VPLUS = 5V TO 9V, VSS = 0V, VDD = 3V
VPLUS = 5V TO 9V, VSS = 0V, VDD = 3V
4
0
4
0
CS_PULSE
CLK_IN
4
0
CLK_IN
4
0
DATA_IN TURNING SW1 AND SW3 ON
4
0
DATA_IN TURNING SW1 ON
4
0
DATA_IN TURNING SW2 AND SW4 ON
4
0
DATA_OUT TURNING SW2 AND SW4 ON (PREVIOUS DATA)
10ms/DIV
10ms/DIV
FIGURE 37. SERIAL TIMING OF DATA_IN
FIGURE 38. SERIAL TIMING OF DATA_OUT
FN6591.0
March 18, 2008
16
ISL54301
L20.4x4C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/06
4X
2.0
4.00
0.50
16X
A
6
B
16
20
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
1
15
2 .70 ± 0 . 15
11
5
0.15
(4X)
6
10
0.10 M
C
A B
4
20X 0.25 +0.05 / -0.07
20X 0.4 ± 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
0 . 90 ± 0 . 1
C
BASE PLANE
( 3. 8 TYP )
(
SEATING PLANE
0.08 C
2. 70 )
( 20X 0 . 5 )
SIDE VIEW
5
0 . 2 REF
C
( 20X 0 . 25 )
( 20X 0 . 6)
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
TYPICAL RECOMMENDED LAND PATTERN
Dimensions in () for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6591.0
March 18, 2008
17
相关型号：
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RENESAS
ISL54302IRZ
12V, 1.5? Quad SPST Switch with Latched Parallel Interface; QFN20; Temp Range: -40° to 85°C
RENESAS
ISL54302IRZ-T
12V, 1.5? Quad SPST Switch with Latched Parallel Interface; QFN20; Temp Range: -40° to 85°C
RENESAS
ISL54400IRUZ
DUAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, PDSO10, 2.10 X 1.60 MM, ROHS COMPLIANT, PLASTIC, UTQFN-10
RENESAS
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