ISL54054IHZ-T_技术文档

Ultra Low ON-Resistance, Low Voltage, Single

Supply, Single SPST/1:2 Distribution Analog Switch

ISL54054, ISL54055

Features

• ON-resistance (r ) (Signal Pins Connected)

The Intersil ISL54054 and ISL54055 devices consist of

low ON-resistance, low voltage, bi-directional SPST

analog switches designed to operate from a single +1.8V

to +5.5V supply. These devices have an unique

architecture. They have two signal pins (pin 1 and pin 3)

that are simultaneously connected or disconnected to a

common pin (pin 4) under the control of a single logic

control pin (pin 6). The ISL54054 switches are OFF when

the logic is low and ON when the logic is high. The

ISL54055 switches are ON when the logic is low and OFF

when the logic is high. This architecture allows these

devices to be used as a single SPST switch or as a

distribution switch to distribute a single source to two

different loads.

ON

- V

= +5.0V. . . . . . . . . . . . . . . . . . . . . 0.34Ω

= +3.0V. . . . . . . . . . . . . . . . . . . . . 0.51Ω

= +1.8V. . . . . . . . . . . . . . . . . . . . . 1.1Ω

CC

• r

ON

flatness (+4.5V supply) . . . . . . . . . . . . 0.13Ω

• Single supply operation . . . . . . . . +1.8V to +5.5V

• Fast switching action (+4.5V supply)

- t

. . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns

ON

OFF

• ESD HBM rating. . . . . . . . . . . . . . . . . . . . . . >6kV

• 1.8V logic compatible (+3V supply)

• Available in 6 Ld μTDFN and 6Ld SOT-23 Packages

• Pb-free (RoHS compliant)

SPST operation is achieved by using one of the signal

pins while floating the other signal pin or by externally

connecting the two signal pins together. When both

Applications

signal pins are tied together, the r

reduced by half, from 1Ω to 0.5Ω (when operated with a

5V supply).

of the SPST is

ON

• Battery powered, handheld and portable equipment

- Cellular/mobile phones

Targeted applications include battery powered equipment

- Pagers

that benefit from low r

resistance, excellent r

- Laptops, notebooks, palmtops

ON

flatness, and fast switching speeds (t

= 12ns,

= 12ns). The digital logic input is 1.8V logic

ON

• Portable test and measurement

• Medical equipment

• Audio and video switching

t

OFF

compatible when using a single 2.7V to +3.6V supply

and TTL compatible when the supply is > +3.6V.

The ISL54054 is offered in a 6 Ld

Related Literature

1.2mmx1.0mmx0.5mm μTDFN and 6 Ld SOT-23

packages. The ISL54055 is offered in a 6 Ld

1.2mmx1.0mmx0.5mm μTDFN, alleviating board space

limitations.

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

The ISL54054 has two normally open (NO) switches and

the ISL54055 has two normally closed (NC) switches.

TABLE 1. FEATURES AT A GLANCE

ISL54054

1

ISL54055

1

Number of Switches

SW

NO

NC

1.8V r

ON

1.1Ω

1.8V t

/t

ON OFF

115ns/90ns

0.51Ω

115ns/90ns

0.51Ω

3V r

ON

3V t

5V t

/t

ON OFF

22ns/17ns

0.34Ω

22ns/17ns

0.34Ω

5V r

ON

/t

12ns/12ns

6 Ld μTDFN

ON OFF

6 Ld μTDFN,

Packages

6 Ld SOT-23

October 19, 2009

FN6461.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL54054, ISL54055

Ordering Information

PART NUMBER

PART

TEMP.

RANGE (°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

(Notes 1, 4)

MARKING

ISL54054IRUZ-T (Note 3)

D

-40 to +85

6 Ld μTDFN

Tape and Reel

L6.1.2x1.0A

ISL54054IHZ-T (Note 2)

ISL54055IRUZ-T (Note 3)

NOTES:

4054

E

6 Ld SOT-23

Tape and Reel

MDP0038

6 Ld μTDFN

Tape and Reel

L6.1.2x1.0A

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach

materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free

soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach

materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free

soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.

4. For Moisture Sensitivity Level (MSL), please see device information page for ISL54054, ISL54055. For more information on

MSL please see techbrief TB363.

Pin Configurations (Note 5)

ISL54054

(6 LD μTDFN)

TOP VIEW

ISL54054

(6 LD SOT-23)

TOP VIEW

NO 1

IN

NO 3

6 GND

1

2

3

6

5

4

IN

NO

GND

NO

2

5

4

COM

V+

COM

ISL54055

(6 LD μTDFN)

TOP VIEW

1

2

3

6

5

4

IN

NC

GND

NC

V+

COM

NOTE:

5. Switches Shown for Logic “0” Input.

Pin Descriptions

Truth Table

FUNCTION

System Power Supply Input (+1.8V to +5.5V)

Ground Connection

ISL54054

Both NO

Switches

ISL54055

Both NC

Switches

V+

GND

IN

LOGIC

Digital Control Input

0

1

Off

On

Off

COM

NO

Analog Switch Common Pin

On

Analog Switch Normally Open Pin

Analog Switch Normally Closed Pin

NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.

NC

FN6461.2

October 19, 2009

2

ISL54054, ISL54055

Absolute Maximum Ratings

Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V

Input Voltages

NO, NC, IN (Note 6) . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)

Output Voltages

COM (Note 6) . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)

Continuous Current NO, NC, or COM. . . . . . . . . . . . ±300mA

Peak Current NO, NC, or COM

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . ±600mA

ESD Rating

Thermal Resistance (Typical)

θ

(°C/W) θ (°C/W)

JC

JA

6 Ld μTDFN Package (Note 7) . . . .

6 Ld SOT-23 Package (Note 8). . . .

Maximum Junction Temperature (Plastic Package). . +150°C

Maximum Storage Temperature Range. . . . . -65°C to +150°C

Pb-free reflow profile. . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

175

260

N/A

120

Operating Conditions

V+ (Positive DC Supply Voltage). . . . . . . . . . . 1.8V to 5.5V

Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . 0V to V+

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . >6kV

Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . >200V

Charged Device Model . . . . . . . . . . . . . . . . . . . . .>2.2kV

V

(Digital Logic Input Voltage (IN) . . . . . . . . . . . 0V to V+

IN

Temperature Range. . . . . . . . . . . . . . . . . . -40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact

product reliability and result in failures not covered by warranty.

NOTES:

6. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum

current ratings.

7. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief

JA

TB379 for details.

8. For θ , the “case temp” location is taken at the package top center.

JC

Electrical Specifications - 5V Supply

Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V

INH

(Note 9), Unless Otherwise Specified. Boldface limits apply over the operat-

ing temperature range, -40°C to +85°C.

= 2.4V, V

= 0.8V

INL

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range,

Full

0

-

V+

V

ANALOG

ON-Resistance, r

V+ = 4.5V, I

COM

NC

= 100mA, V

or

25

Full

25

-

0.36

0.49

0.12

0.13

0.85

1.1

-

Ω

ON

(Nx Inputs Connected)

NO

= 0V to V+, (See Figure 4, Note 13)

V

-

r

Flatness, r

V+ = 4.5V, I

= 100mA, V

NO

or

-

Ω

ON

FLAT(ON)

COM

= 0V to V+, (Notes 12, 13)

(Nx Inputs Connected)

V

NC

Full

25

-

Ω

ON-Resistance, r

ON

(Single Nx Input)

V+ = 4.5V, I

= 100mA, V

or

-

Ω

COM

NO

V

= 0V to V+, (See Figure 4, Note 13)

NC

Full

25

-

Ω

r

Flatness, r

V+ = 4.5V, I

= 100mA, V or

NO

0.25

5

-

Ω

ON

FLAT(ON)

COM

= 0V to V+, (Notes 12, 13)

(Single Nx Input)

V

NC

Full

25

-

Ω

NO or NC OFF Leakage

V+ = 5.5V, V

= 0.3V, 5V, V

NO

or

-10

-150

10

150

nA

COM

Current, I

or

V

= 5V, 0.3V

NO(OFF)

NC

Full

-

I

NC(OFF)

COM ON Leakage Current,

V+ = 5.5V, V

= 0.3V, 5V, or V

or

25

-20

9

-

20

nA

COM

NO

I

V

= 0.3V, 5V, or floating

COM(ON)

DYNAMIC CHARACTERISTICS

Turn-ON Time, t V+ = 4.5V, V

NC

Full

-300

300

or V

= 3.0V, R = 50Ω,

25

Full

25

-

12

15

12

15

71

-

ns

pC

ON

NO

NC

L

C = 35pF (See Figure 1)

L

Turn-OFF Time, t

V+ = 4.5V, V

NO

or V

= 3.0V, R = 50Ω,

L

OFF

NC

C = 35pF (See Figure 1)

L

Full

25

Charge Injection, Q

V

= 0V, R = 0Ω, C = 1.0nF

G G L

(See Figure 2)

OFF Isolation

(Nx Inputs Connected)

R = 50Ω, C = 5pF, f = 100kHz,

25

-

74

-

dB

L

V

= 1V

(See Figure 3)

COM

RMS

FN6461.2

October 19, 2009

3

ISL54054, ISL54055

Electrical Specifications - 5V Supply

Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V

(Note 9), Unless Otherwise Specified. Boldface limits apply over the operat-

ing temperature range, -40°C to +85°C. (Continued)

= 2.4V, V

= 0.8V

INL

INH

TEMP

MIN

MAX

PARAMETER

OFF Isolation

(Single Nx Input)

TEST CONDITIONS

(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS

R = 50Ω, C = 5pF, f = 100kHz,

25

-

83

72

-

dB

MHz

pF

L

RMS

V

= 1V

(See Figure 3)

COM

-3dB Bandwidth

(Nx Inputs Connected)

R = 50Ω

L

-3dB Bandwidth

(Single Nx Input)

R = 50Ω

138

30

L

NO or NC OFF Capacitance, f = 1MHz, V

or V

= V

= 0V

NO

NC

COM

C

(Nx Inputs Connected) (See Figure 5)

OFF

COM ON Capacitance,

(Nx Inputs

f = 1MHz, V

62

pF

NO

COM

C

(See Figure 5)

COM(ON)

Connected)

NO or NC OFF Capacitance, f = 1MHz, V

NO

OFF

or V

= V

= 0V

25

-

16

89

-

pF

NC

COM

C

(Single Nx Input)

(See Figure 5)

COM ON Capacitance,

f = 1MHz, V

NO

(Single Nx Input) (See Figure 5)

COM

C

COM(ON)

POWER SUPPLY CHARACTERISTICS

Power Supply Range

Full

25

1.8

-

5.5

0.5

1.0

0.5

1.4

V

Positive Supply Current, I+ V+ = 5.5V, V = 0V or V+

IN

(μTDFN)

-

μA

Full

25

Positive Supply Current, I+ V+ = 5.5V, V = 0V or V+

IN

(SOT-23)

Full

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

INL

Full

-

0.8

-

V

Input Voltage High, V

2.4

-1

INH

, I

Input Current, I

V+ = 5.5V, V = 0V or V+

IN

1

μA

INH INL

Electrical Specifications - 3V Supply

Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, V

INH

(Note 9), Unless Otherwise Specified. Boldface limits apply over the operat-

= 1.4V, V

= 0.5V

INL

ing temperature range, -40°C to +85°C.

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range,

Full

0

-

V+

V

ANALOG

ON-Resistance, r

V+ = 2.7V, I

COM

NC

= 100mA, V

or

25

Full

25

-

0.57

0.73

0.2

1.3

1.6

0.4

0.65

1.0

0.4

0.5

1.7

2.0

0.6

0.7

Ω

ON

(Nx Inputs Connected)

NO

= 0V to V+, (See Figure 4, Note 13)

V

r

Flatness, r

V+ = 2.7V, I

= 100mA, V

NO

or

ON

FLAT(ON)

COM

= 0V to V+, (Notes 12, 13)

(Nx Inputs Connected)

V

NC

Full

25

ON-Resistance, r

ON

(Single Nx Input)

V+ = 2.7V, I

= 100mA, V

NO

or

COM

V

= 0V to V+, (See Figure 4, Note 13)

NC

Full

25

r

Flatness, r

V+ = 2.7V, I

= 100mA, V

or

NO

ON

FLAT(ON)

COM

= 0V to V+, (Notes 12, 13)

(Single Nx Input)

V

NC

DYNAMIC CHARACTERISTICS

Turn-ON Time, t V+ = 2.7V, V

Full

or V

NC

= 1.5V, R = 50Ω,

25

Full

25

-

22

25

17

20

-

ns

ON

NO

C = 35pF (See Figure 1)

L

Turn-OFF Time, t

V+ = 2.7V, V

NO

L

or V = 1.5V, R = 50Ω,

NC L

OFF

C = 35pF (See Figure 1)

Full

FN6461.2

October 19, 2009

4

ISL54054, ISL54055

Electrical Specifications - 3V Supply

Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, V

(Note 9), Unless Otherwise Specified. Boldface limits apply over the operat-

= 1.4V, V

= 0.5V

INL

INH

ing temperature range, -40°C to +85°C. (Continued)

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

= 0V, R = 0Ω, C = 1.0nF

(See Figure 2)

(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS

Charge Injection, Q

V

25

-

42

74

83

30

62

-

pC

dB

pF

G

L

OFF Isolation

(Nx Inputs Connected)

R = 50Ω, C = 5pF, f = 100kHz,

L

RMS

V

= 1V

(See Figure 3)

COM

OFF Isolation

(Single Nx Input)

R = 50Ω, C = 5pF, f = 100kHz,

L

RMS

V

= 1V

(See Figure 3)

COM

NO or NC OFF Capacitance, f = 1MHz, V

or V

= V

= 0V

NO

NC

COM

C

(Nx Inputs Connected) (See Figure 5)

OFF

COM ON Capacitance,

(Nx Inputs

f = 1MHz, V

= V

NO

NC

COM

C

(See Figure 5)

COM(ON)

Connected)

NO or NC OFF Capacitance, f = 1MHz, V

NO

OFF

or V

= V

= 0V

25

-

16

89

-

pF

NC

COM

C

(Single Nx Input)

(See Figure 5)

COM ON Capacitance,

f = 1MHz, V

NO

(Single Nx Input) (See Figure 5)

COM

C

COM(ON)

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Full

-

0.5

-

V

INL

Input Voltage High, V

1.4

-1

INH

, I

Input Current, I

V+ = 3.6V, V = 0V or V+

IN

1

μA

INH INL

Electrical Specifications - 1.8V Supply

Test Conditions: V+ = +1.8V, GND = 0V, V

INH

Unless Otherwise Specified. Boldface limits apply over the operating tem-

= 1.8V, V

= 0V (Note 9),

INL

perature range, -40°C to +85°C.

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range,

Full

0

-

V+

V

ANALOG

ON-Resistance, r

V+ = 1.8V, I

= 100mA, V

or

= 0V to V+, Pins 1 and 3 connected,

25

-

1.1

1.3

-

Ω

ON

(Nx Inputs Connected)

COM

NO

V

NC

(See Figure 4, Note 13)

Full

ON-Resistance, r

ON

V+ = 1.8V, I

= 100mA, V

or

25

-

2.3

-

Ω

COM NO

(Single Nx Input)

DYNAMIC CHARACTERISTICS

Turn-ON Time, t V+ = 1.8V, V

V

= 0V to V+ (See Figure 4, Note 13)

NC

Full

2.53

or V

NC

= 1.5V, R = 50Ω,

25

Full

25

-

115

246

90

-

ns

pC

ON

NO

C = 35pF (See Figure 1)

L

Turn-OFF Time, t

OFF

V+ = 1.8V, V

NO

or V = 1.5V, R = 50Ω,

NC L

C = 35pF (See Figure 1)

L

Full

25

192

22

Charge Injection, Q

NOTES:

V

= 0V, R = 0Ω,C = 1.0nF

G G L

(See Figure 2)

9. V = input voltage to perform proper function.

IN

10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this

data sheet.

11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established

by characterization and are not production tested.

12. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal

range.

13. Limits established by characterization and are not production tested.

FN6461.2

October 19, 2009

5

ISL54054, ISL54055

Test Circuits and Waveforms

V+

V

t < 20ns

r

t < 20ns

f

INH

C

LOGIC

INPUT

50%

V

INL

t

V

OFF

OUT

NO OR NC

IN

SWITCH

INPUT

COM

SWITCH

INPUT

V

NO

0V

V

OUT

90%

C

L

35pF

R

50Ω

LOGIC

INPUT

L

GND

SWITCH

OUTPUT

t

ON

Logic input waveform is inverted for switches that have the

opposite logic sense.

Repeat test for all switches. C includes fixture and stray capacitance.

L

R

L

----------------------------

L

V

= V

OUT

(NO or NC)

R

+ r

(ON)

FIGURE 1A. MEASUREMENT POINTS

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

V+

C

SWITCH

OUTPUT

ΔV

V

OUT

R

OUT

G

COM

NO OR NC

GND

V

OUT

V

INH

ON

LOGIC

INPUT

V

IN

G

OFF

C

L

V

INL

LOGIC

INPUT

Q = ΔV

x C

L

OUT

FIGURE 2A. MEASUREMENT POINTS

FIGURE 2B. TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

V+

C

r

= V /100mA

1

ON

SIGNAL

GENERATOR

NO OR NC

V

NX

100mA

IN

0V OR V+

V

OR V

INH

INL

IN

V

1

COM

ANALYZER

GND

R

L

FIGURE 3. OFF ISOLATION TEST CIRCUIT

FIGURE 4. r TEST CIRCUIT

ON

FN6461.2

October 19, 2009

6

ISL54054, ISL54055

Test Circuits and Waveforms(Continued)

V+

C

V

NO OR NC

OR V

INH

IN

INL

IMPEDANCE

ANALYZER

COM

GND

FIGURE 5. CAPACITANCE TEST CIRCUIT

To prevent forward biasing these diodes, V+ must be

applied before any input signals, and the input signal

voltages must remain between V+ and GND. If these

conditions cannot be guaranteed, then one of the

following two protection methods should be employed.

Detailed Description

The Intersil ISL54054 and ISL54055 devices consist of

low ON-resistance, low voltage, bi-directional analog

switches designed to operate from a single +1.8V to

+5.5V supply. With a single supply of 5V the typical

ON-resistance is only 0.34Ω, with a typical turn-on and

Logic inputs can easily be protected by adding a 1kΩ

resistor in series with the input (see Figure 6). The

resistor limits the input current below the threshold

that produces permanent damage, and the sub-

microamp input current produces an insignificant

voltage drop during normal operation.

turn-off time of: t

= 12ns, t = 12ns. The

ON

OFF

devices are especially well suited for portable battery

powered equipment due to its low operating supply

voltage (1.8V), low power consumption (5.5μW), low

leakage currents (300nA max) and the tiny μTDFN

and SOT-23 packages.

This method is not acceptable for the signal path

inputs. Adding a series resistor to the switch input

These devices have an unique architecture. They have

two signal pins (pin 1 and pin 3) that are

defeats the purpose of using a low r

switch.

ON

simultaneously connected or disconnected to a single

common pin (pin 4) under the control of a single logic

control pin (pin 6). The ISL54054 switches are OFF

when the logic is low and ON when the logic is high.

The ISL54055 are ON when the logic is low and OFF

when the logic is high. This architecture allows these

devices to be used as a single SPST switch or as a

distribution switch to distribute a single source to two

different loads.

Connecting schottky diodes to the signal pins (as

shown in Figure 6) will shunt the fault current to the

supply or to ground, thereby protecting the switch.

These schottky diodes must be sized to handle the

expected fault current.

OPTIONAL

SCHOTTKY

DIODE

V+

OPTIONAL

SPST operation is achieved by using one of the Nx

signal pins while floating the other Nx signal pin or by

externally connecting the two Nx signal pins together.

PROTECTION

RESISTOR

IN

V

X

When both signal pins are tied together, the r

SPST is reduced by half, from 1Ω to 0.5Ω (when

of the

V

ON

NX

COM

operated with a 5V supply).

GND

The ISL54054 is a normally open (NO) SPST analog

switch. The ISL54055 is a normally closed (NC) SPST

analog switch.

OPTIONAL

SCHOTTKY

DIODE

Supply Sequencing and Overvoltage

Protection

FIGURE 6. OVERVOLTAGE PROTECTION

With any CMOS device, proper power supply

sequencing is required to protect the device from

excessive input currents, which might permanently

damage the IC. All I/O pins contain ESD protection

diodes from the pin to V+ and to GND (see Figure 6).

FN6461.2

October 19, 2009

7

ISL54054, ISL54055

Power-Supply Considerations

High-Frequency Performance

The construction of the ISL54054 and the ISL54055 is

typical of most single supply CMOS analog switches in

that they have two supply pins: V+ and GND. V+ and

GND drive the internal CMOS switches and set their

analog voltage limits. Unlike switches with a 4.5V

maximum supply voltage, the ISL54054 and the

ISL54055’s 5.5V maximum supply voltage provides

plenty of room for the 10% tolerance of 4.5V supplies,

as well as room for overshoot and noise spikes.

In 50Ω systems, the ISL54054 and the ISL54055 have a

-3dB bandwidth of 72MHz with Nx pins connected and

138MHz for a single Nx input (see Figure 20). The

frequency response is very consistent over a wide V+

range, and for varying analog signal levels.

An OFF switch acts like a capacitor and passes higher

frequencies with less attenuation, resulting in signal

feedthrough from a switch’s input to its output. Off

isolation is the resistance to this feedthrough.

Figure 21 details the high off isolation rejection

provided by this family. At 100kHz, off isolation in 50Ω

systems is about 74dB with Nx pins connected and

83dB with a single Nx input, decreasing approximately

20dB per decade as frequency increases. Higher load

impedances decrease off isolation rejection due to the

voltage divider action of the switch OFF impedance and

the load impedance.

The minimum recommended supply voltage is 1.8V. It

is important to note that the input signal range,

switching times, and on-resistance degrade at lower

supply voltages. Refer to the “Electrical Specifications”

tables starting on page 3 and “Typical Performance

Curves” on page 8 for details.

V+ and GND also power the internal logic and level

shiftier. The level shiftier converts the input logic levels

to switched V+ and GND signals to drive the analog

switch gate terminals.

Leakage Considerations

Reverse ESD protection diodes are internally connected

between each analog-signal pin and both V+ and GND.

One of these diodes conducts if any analog signal

exceeds V+ or GND.

This family of switches cannot be operated with bipolar

supplies, because the input switching point becomes

negative in this configuration.

Virtually all the analog leakage current comes from the

ESD diodes to V+ or GND. Although the ESD diodes on

a given signal pin are identical and therefore fairly well

balanced, they are reverse biased differently. Each is

biased by either V+ or GND and the analog signal. This

means their leakages will vary as the signal varies. The

difference in the two diode leakages to the V+ and

GND pins constitutes the analog-signal-path leakage

current. All analog leakage current flows between each

pin and one of the supply terminals, not to the other

switch terminal. This is why both sides of a given

switch can show leakage currents of the same or

opposite polarity. There is no connection between the

analog signal paths and V+ or GND.

Logic-Level Thresholds

This switch family is 1.8V logic compatible (0.5V and

1.4V) over a supply range of 2.5V to 5V (see

Figure 19). At 5V the V level is about 1.38V. This is

IH

still below the 1.8V CMOS guaranteed high output

minimum level of 1.4V, but noise margin is reduced. At

1.8V operation the V level is around 0.1V and can

IL

only be used in 1.8V applications with minimal ground

bounce.

The digital input stages draw supply current whenever

the digital input voltage is not at one of the supply

rails. Driving the digital input signals from GND to V+

with a fast transition time minimizes power dissipation.

Typical Performance Curves T = +25°C, Unless Otherwise Specified

A

1.4

1.2

I

= 100mA

V+ = 1.8V

= 100mA

COM

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

I

COM

1.2

1.0

0.8

0.6

0.4

0.2

V+ = 1.8V

+85°C

+25°C

-40°C

V+ = 2.7V

V+ = 4.5V

V+ = 3V

V+ = 5V

0

1

2

3

4

5

0

0.5

1.0

(V)

1.5

1.8

V

(V)

V

COM

FIGURE 7. ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE (NX PINS CONNECTED)

FIGURE 8. ON-RESISTANCE vs SWITCH VOLTAGE

(NX PINS CONNECTED)

FN6461.2

October 19, 2009

8

ISL54054, ISL54055

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

V+ = 5V

= 100mA

V+ = 3V

= 100mA

I

COM

+85°C

+25°C

-40°C

0.05

0

0.5

1.0

1.5

(V)

2.0

2.5

3.0

0

1

2

3

4

5

V

(V)

COM

FIGURE 9. ON-RESISTANCE VS SWITCH VOLTAGE

(NX PINS CONNECTED)

FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE

(NX PINS CONNECTED)

3.0

2.3

V+ = 1.8V

I

= 100mA

COM

I

= 100mA

COM

2.1

1.9

1.7

1.5

1.3

1.1

0.9

2.5

2.0

1.5

1.0

0.5

V+ = 1.8V

+85°C

+25°C

-40°C

V+ = 2.7V

V+ = 3V

V+ = 4.5V

0.7

0.5

V+ = 5V

0

0.5

1.0

(V)

1.5

1.8

0

1

2

3

4

5

V

(V)

V

COM

FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE (SINGLE NX INPUT)

FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE

(SINGLE NX INPUT)

1.1

1.6

V+ = 5V

V+ = 3V

I

= 100mA

COM

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

I

= 100mA

COM

1.4

1.2

1.0

0.8

0.6

0.4

+85°C

+25°C

+85°C

+25°C

-40°C

0

0.5

1.0

1.5

2.0

2.5

3.0

0

1

2

3

4

5

V

(V)

V

(V)

COM

FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE

(SINGLE NX INPUT)

FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE

(SINGLE NX INPUT)

FN6461.2

October 19, 2009

9

ISL54054, ISL54055

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

200

180

160

140

120

100

80

30

25

20

15

10

5

-40°C

+25°C

+85°C

+25°C

60

40

-40°C

2.5

20

0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

1.5

2.0

3.0

3.5

4.0

4.5

5.0

5.5

V+ (V)

FIGURE 15. TURN ON TIME vs SUPPLY VOLTAGE

(ISL54054)

FIGURE 16. TURN OFF TIME vs SUPPLY VOLTAGE

(ISL54054)

250

30

-40°C

200

25

+85°C

150

20

+25°C

25°C

100

15

-40°C

10

85°C

50

0

1.5

5

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

V+ (V)

FIGURE 17. TURN ON TIME vs SUPPLY VOLTAGE

(ISL54055)

FIGURE 18. TURN OFF TIME vs SUPPLY VOLTAGE

(ISL54055)

V+ = 5V

1.6

1.4

1.2

V

INH

1.0

0.8

0

SINGLE NX INPUT

V

INL

-3

0.6

0.4

NX PINS CONNECTED

-6

-9

0.2

0

R

V

= 50Ω

IN

L

= 0.2V

TO 2.8V

P-P

0.1k

1M

10M

FREQUENCY (Hz)

100M

500M

1.5

2.0

2.5

3.0

3.5

V+ (V)

4.0

4.5

5.0

5.5

FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY

VOLTAGE

FIGURE 20. FREQUENCY RESPONSE

FN6461.2

October 19, 2009

10

ISL54054, ISL54055

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

10

V+ = 1.8V TO 5.5V

140

R

= 50Ω

20

30

L

V

= 1V

IN

P-P

120

100

80

V+ = 5V

40

50

Nx PINS CONNECTED

60

40

20

0

70

V+ = 3V

80

SINGLE Nx INPUT

90

100

110

V+ = 1.8V

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

(V)

1k

10k

100k

1M

10M

100M 500M

V

COM

FREQUENCY (Hz)

FIGURE 21. OFF ISOLATION

FIGURE 22. CHARGE INJECTION vs SWITCH VOLTAGE

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

TRANSISTOR COUNT:

57

PROCESS:

Submicron CMOS

FN6461.2

October 19, 2009

11

ISL54054, ISL54055

Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)

L6.1.2x1.0A

A

E

B

6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

NOMI-

PIN 1

D

REFERENCE

SYMBOL

MIN

0.45

-

NAL

MAX

0.55

0.05

NOTES

2X

0.10C

A

A1

A3

b

0.50

-

TOP VIEW

0.127 REF

-

DETAIL A

A1 A3

0.15

0.95

1.15

0.20

0.25

1.05

1.25

5

0.10C

0.08C

D

1.00

-

A

7X

E

1.20

-

C

e

0.40 BSC

-

SEATING

PLANE

SIDE VIEW

L

0.30

0.40

0.35

0.40

0.50

-

L1

N

0.45

-

4X

e

DETAIL B

6

3

-

2

5X

L

1

3

Ne

θ

3

L1

0

12

4

Rev. 2 8/06

NOTES:

6

4

1. Dimensioning and tolerancing conform to ASME Y14.5-

1994.

b 6X

0.10 C A B

2. N is the number of terminals.

0.05C

NOTE 3

BOTTOM VIEW

3. Ne refers to the number of terminals on E side.

4. All dimensions are in millimeters. Angles are in degrees.

0.1x45°

CHAMFER

5. Dimension b applies to the metallized terminal and is

measured between 0.15mm and 0.30mm from the

terminal tip.

6. The configuration of the pin #1 identifier is optional, but

must be located within the zone indicated. The pin #1

identifier may be either a mold or mark feature.

A3

A1

7. Maximum package warpage is 0.05mm.

8. Maximum allowable burrs is 0.076mm in all directions.

9. JEDEC Reference MO-255.

DETAIL A

DETAIL B PIN 1 LEAD

10. For additional information, to assist with the PCB Land

Pattern Design effort, see Intersil Technical Brief TB389.

1.00

1.40

0.20

0.30

0.35

0.45

0.20

0.40

10

LAND PATTERN

FN6461.2

October 19, 2009

12

ISL54054, ISL54055

SOT-23 Package Family

MDP0038

e1

D

SOT-23 PACKAGE FAMILY

A

MILLIMETERS

SOT23-5

6

4

N

SYMBOL

SOT23-6

1.45

0.10

1.14

0.40

0.14

2.90

2.80

1.60

0.95

1.90

0.45

0.60

6

TOLERANCE

MAX

A

A1

A2

b

1.45

0.10

1.14

0.40

0.14

2.90

2.80

1.60

0.95

1.90

0.45

0.60

5

±0.05

E1

E

±0.15

2

3

±0.05

0.15

2X

C

D

c

±0.06

1

2

3

0.20

2X

C

D

Basic

5

e

E

Basic

E1

e

Basic

0.20

C

A-B

D

M

B

b

NX

Basic

e1

L

Basic

±0.10

L1

N

Reference

Rev. F 2/07

0.15

2X

C

A-B

1

3

D

NOTES:

C

1. Plastic or metal protrusions of 0.25mm maximum per side are not

included.

A2

SEATING

PLANE

2. Plastic interlead protrusions of 0.25mm maximum per side are not

included.

A1

0.10

NX

C

3. This dimension is measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Index area - Pin #1 I.D. will be located within the indicated zone

(SOT23-6 only).

6. SOT23-5 version has no center lead (shown as a dashed line).

(L1)

H

A

GAUGE

PLANE

0.25

c

+3°

-0°

L

0°

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications

at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by

Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any

patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6461.2

October 19, 2009

13


型号：	ISL54054IHZ-T
厂家：	Intersil
描述：	Ultra Low ON-Resistance, Low Voltage, Single Supply, Single SPST/1:2 Distribution Analog Switch 超低导通电阻，低电压，单电源，单路SPST / 1 ： 2的分布模拟开关开关光电二极管
文件：	总13页 (文件大小：501K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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