ISL54056_技术文档

ISL54056

®

Data Sheet

October 30, 2006

FN6357.1

Ultra Low ON-Resistance, +1.65V to +4.5V,

Single Supply, Quad SPDT (Dual DPDT)

Analog Switch

Features

• Pb-Free Plus Anneal Available (RoHS Compliant)

• Pin Compatible Replacement for the NLAS3799 and

NLAS3799L

The Intersil ISL54056 device is a low ON-resistance, low

voltage, bidirectional, Quad SPDT (Dual DPDT) analog

switch designed to operate from a single +1.65V to +4.5V

supply. Targeted applications include battery powered

• ON Resistance (R

)

ON

- V+ = +4.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.39Ω

- V+ = +3.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45Ω

- V+ = +1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65Ω

equipment that benefit from low R

(0.39Ω) and fast

= 16ns). The digital logic

ON

switching speeds (t

ON

= 30ns, t

OFF

input is 1.8V logic-compatible when using a single +3V supply.

With a supply voltage of 4.2V and logic high voltage of 2.85V

at both logic inputs, the part draws only 12µA max of ICC

current.

• R

Matching between Channels . . . . . . . . . . . . . . . . 0.05Ω

Flatness Across Signal Range . . . . . . . . . . . . . . . 0.05Ω

ON

• R

• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V

• Low Power Consumption (PD) . . . . . . . . . . . . . . . . <0.68μW

• Fast Switching Action (V+ = +4.3V)

Cell phones, for example, often face ASIC functionality

limitations. The number of analog input or GPIO pins may be

limited and digital geometries are not well suited to analog

switch performance. This part may be used to “mux-in”

additional functionality while reducing ASIC design risk. The

ISL54056 is offered in small form factor package, alleviating

board space limitations.

- t

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns

ON

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns

OFF

• Break-Before-Make

• 1.8V Logic Compatible (+3V supply)

• Low ICC Current when VinH is not at the V+ Rail

• Available in 16 Ld 2.6x1.8x0.5mm µTQFN

The ISL54056 consists of four SPDT switches. It is configured

as a dual double-pole/double-throw (DPDT) device with two

logic control inputs that control two SPDT switches each. The

configuration can be used as a dual differential 2-to-1

multiplexer/demultiplexer. The ISL54056 is pin compatible

with the NLAS3799 and NLAS3799L.

• ESD HBM Rating

- COM Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9kV

- All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV

TABLE 1. FEATURES AT A GLANCE

ISL54056

Applications

• Battery Powered, Handheld, and Portable Equipment

- Cellular/Mobile Phones

Number of Switches

SW

4

Quad SPDT (Dual DPDT)

- Pagers

4.3V R

ON

0.39Ω

- Laptops, Notebooks, Palmtops

4.3V t /t

ON OFF

30ns/16ns

• Portable Test and Measurement

• Medical Equipment

3.0V R

ON

0.45Ω

• Audio and Video Switching

3.0V t /t

ON OFF

34ns/18ns

1.8V R

ON

0.65Ω

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

1.8V t /t

ON OFF

48ns/23ns

Package

16 Ld 2.6x1.8x0.5mm µTQFN

• Application Note AN557 “Recommended Test Procedures

for Analog Switches”

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL54056

Truth Table

Pinouts (Note 1)

ISL54056 (µTQFN)

LOGIC

NC SW

ON

NO SW

OFF

TOP VIEW

0

1

OFF

ON

NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.

NC4

COM3

NO3

Pin Descriptions

V+

NO1

FUNCTION

System Power Supply Input (+1.65V to +4.5V)

Ground Connection

GND

NC2

V+

COM1

GND

IN

Digital Control Input

COM

NO

Analog Switch Common Pin

Analog Switch Normally Open Pin

Analog Switch Normally Closed Pin

NOTE:

NC

1. Switches Shown for Logic “0” Input.

Ordering Information

PART NUMBER

PART MARKING

TEMP. RANGE (°C)

-40 to 85

PACKAGE

PKG. DWG. #

ISL54056IRUZ-T (Note)

GAA

16 Ld Thin μQFN Tape and Reel (Pb-free) L16.2.6x1.8A

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN6357.1

October 30, 2006

2

ISL54056

Absolute Maximum Ratings

Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V

Input Voltages

NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)

Output Voltages

COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V)

Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA

Peak Current NO, NC, or COM

Thermal Resistance (Typical, Note 3)

θ

(°C/W)

93

JA

μTQFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package). . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

(Lead Tips Only)

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA

ESD Rating:

Operating Conditions

Temperature Range

ISL54056IRUZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

HBM COM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>9kV

X

HBM NO , NC , IN , V+, GND . . . . . . . . . . . . . . . . . . . . . . .>6kV

X

MM COM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>700V

X

MM NO , NC , IN , V+, GND . . . . . . . . . . . . . . . . . . . . . . .>300V

X

CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.

3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications - 4.3V Supply

Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V

unless otherwise specified

= 1.6V, V

= 0.5V (Note 4),

INH

INL

TEMP (NOTE 5)

(NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

25

0

V+

V

Ω

ON Resistance, R

V+ = 3.9V, I

= 100mA, V

or V

= 0V to V+

= Voltage at

= 0V to V+

0.4

ON

COM

(See Figure 5)

NO

NC

Full

25

0.45

0.05

0.06

0.05

Ω

R

Matching Between Channels, V+ = 3.9V, I

= 100mA, V

(Note 7)

ON

or V

Ω

ON

ΔR

COM

NO

NC

max R

ON

Full

25

Ω

R

Flatness, R

V+ = 3.9V, I

(Note 6)

= 100mA, V

or V

NC

Ω

ON

FLAT(ON)

COM

NO

Full

25

Ω

NO or NC OFF Leakage Current,

or I

V+ = 4.5V, V

= 0.3V, 3V, V

NO

or V

NC

= 3V, 0.3V

-70

-165

-70

70

165

70

nA

COM

I

NO(OFF)

NC(OFF)

Full

25

COM ON Leakage Current,

V+ = 4.5V, V

= 0.3V, 3V, or V

or V

= 0.3V, 3V

NC

COM

NO

I

COM(ON)

Full

-165

165

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

V+ = 3.9V, V

or V

= 3.0V, R = 50Ω, C = 35pF

25

Full

25

33

38

16

21

3

ns

ON

NO

(See Figure 1)

NC

L

Turn-OFF Time, t

V+ = 3.9V, V

= 3.0V, R = 50Ω, C = 35pF

L L

OFF

NO

(See Figure 1)

Full

Break-Before-Make Time Delay, t

V+ = 4.5V, V

= 3.0V, R = 50Ω, C = 35pF

L L

D

NO

(See Figure 3)

Charge Injection, Q

OFF Isolation

C

R

= 1.0nF, V = 0V, R = 0Ω (See Figure 2)

25

248

65

pC

dB

L

G

= 50Ω, C = 5pF, f = 100kHz, V

= 1V

L

COM

RMS

(See Figure 4)

Crosstalk (Channel-to-Channel)

Total Harmonic Distortion

R

= 50Ω, C = 5pF, f = 100kHz, V

= 1V

25

-85

dB

%

L

COM

RMS

(See Figure 6)

f = 20Hz to 20kHz, V

= 2V , R = 600Ω

P-P

0.008

COM

L

FN6357.1

October 30, 2006

3

ISL54056

Electrical Specifications - 4.3V Supply

Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V

unless otherwise specified (Continued)

= 1.6V, V

= 0.5V (Note 4),

(NOTE 5)

INH

INL

TEMP (NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

NO or NC OFF Capacitance, C

f = 1MHz, V

or V

= V

= 0V (See Figure 7)

25

38

pF

OFF

NO

NC

COM

COM ON Capacitance, C

25

102

COM(ON)

NC

POWER SUPPLY CHARACTERISTICS

Power Supply Range

Full

25

1.65

4.5

0.15

1.4

V

Positive Supply Current, I+

V+ = +4.5V, V = 0V or V+

IN

μA

Full

25

Positive Supply Current, I+

V+ = +4.2V, V = 2.85V

IN

12

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Full

0.5

V

INL

Input Voltage High, V

1.6

INH

Input Current, I , I

INH INL

V+ = 4.5V, V = 0V or V+

IN

-0.5

μA

NOTES:

4. V = input voltage to perform proper function.

IN

5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.

7. R

matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron

ON

value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4.

Electrical Specifications - 3V Supply

Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V

INH

unless otherwise specified

= 1.4V, V

= 0.5V (Note 4),

(NOTE 5)

INL

TEMP (NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

25

0

V+

V

Ω

ON Resistance, R

V+ = 2.7V, I

= 100mA, V

or V

= 0V to V+

= Voltage at

= 0V to V+

0.45

0.05

0.07

0.55

0.65

0.12

0.15

ON

COM

(See Figure 5)

NO

NC

Full

25

Ω

R

Matching Between Channels, V+ = 2.7V, I

= 100mA, V

(Note 7)

ON

or V

Ω

ON

ΔR

COM

NO

NC

max R

ON

Full

25

Ω

R

Flatness, R

V+ = 2.7V, I

(Note 6)

= 100mA, V

or V

NC

Ω

ON

FLAT(ON)

COM

NO

Full

25

Ω

NO or NC OFF Leakage Current,

or I

V+ = 3.3V, V

= 0.3V, 3V, V

NO

or V

NC

= 3V, 0.3V

1.1

30

nA

COM

I

NO(OFF)

NC(OFF)

Full

25

COM ON Leakage Current,

V+ = 3.3V, V

or Floating

= 0.3V, 3V, or V

NO

or V

= 0.3V, 3V,

1.5

45

COM

NC

I

COM(ON)

Full

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

V+ = 2.7V, V

or V

= 1.5V, R = 50Ω, C = 35pF

25

Full

25

34

39

18

23

3

ns

ON

NO

(See Figure 1)

NC

L

Turn-OFF Time, t

V+ = 2.7V, V

= 1.5V, R = 50Ω, C = 35pF

L L

OFF

NO

(See Figure 1)

Full

Break-Before-Make Time Delay, t

V+ = 3.3V, V

= 1.5V, R = 50Ω, C = 35pF

L L

D

NO

(See Figure 3)

FN6357.1

October 30, 2006

4

ISL54056

Electrical Specifications - 3V Supply

Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V

unless otherwise specified (Continued)

= 1.4V, V

= 0.5V (Note 4),

(NOTE 5)

INH

INL

TEMP (NOTE 5)

PARAMETER

TEST CONDITIONS

= 1.0nF, V = 0V, R = 0Ω (See Figure 2)

(°C)

MIN

TYP

MAX

UNITS

Charge Injection, Q

OFF Isolation

C

R

25

126

65

pC

dB

L

G

= 50Ω, C = 5pF, f = 100kHz, V

= 1V

25

L

COM

RMS

(See Figure 4)

Crosstalk (Channel-to-Channel)

Total Harmonic Distortion

R

= 50Ω, C = 5pF, f = 100kHz, V

= 1V

25

-85

dB

L

COM

RMS

(See Figure 6)

f = 20Hz to 20kHz, V

= 2V , R = 600Ω

P-P

25

0.012

38

%

pF

COM

L

NO or NC OFF Capacitance, C

f = 1MHz, V

or V

= V

= 0V (See Figure 7)

OFF

NO

NC

COM

COM ON Capacitance, C

= V

102

COM(ON)

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+

V+ = 3.6V, V = 0V or V+

IN

25

0.021

0.72

μA

Full

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Full

0.5

V

INL

Input Voltage High, V

1.4

INH

Input Current, I

, I

V+ = 3.6V, V = 0V or V+

IN

-0.5

0.5

μA

INH INL

Electrical Specifications - 1.8V Supply

Test Conditions: V+ = +1.65V to +2V, GND = 0V, V

unless otherwise specified

= 1.0V, V

= 0.4V (Note 4),

INL

INH

TEMP (NOTE 5)

(NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

25

0

V+

0.8

V

Ω

ON Resistance, R

V+ = 1.8V, I

= 100mA, V

or V = 0V to V+

NC

0.65

ON

COM

(See Figure 5)

NO

Full

0.85

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

V+ = 1.65V, V

or V

= 1.0V, R = 50Ω, C = 35pF

25

Full

25

50

55

25

30

8

ns

ON

NO

(See Figure 1)

NC

L

Turn-OFF Time, t

V+ = 1.65V, V

= 1.0V, R = 50Ω, C = 35pF

L L

OFF

NO

(See Figure 1)

Full

Break-Before-Make Time Delay, t

Charge Injection, Q

V+ = 2.0V, V

or V

= 1.0V, R = 50Ω, C = 35pF

NC L L

D

NO

(See Figure 3)

C

= 1.0nF, V = 0V, R = 0Ω (See Figure 2)

25

48

pC

L

G

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Full

0.4

0.5

V

INL

Input Voltage High, V

1.0

INH

Input Current, I

, I

V+ = 2.0V, V = 0V or V+

IN

-0.5

μA

INH INL

FN6357.1

October 30, 2006

5

ISL54056

Test Circuits and Waveforms

V+

C

LOGIC

INPUT

50%

0V

NO

0V

t

V

OFF

OUT

NO or NC

IN

SWITCH

INPUT

COM

SWITCH

INPUT

V

OUT

90%

C

L

35pF

R

50Ω

LOGIC

INPUT

L

GND

SWITCH

OUTPUT

t

ON

Repeat test for all switches. C includes fixture and stray

L

Logic input waveform is inverted for switches that have the opposite

logic sense.

capacitance.

R

L

------------------------------

V

= V

OUT

(NO or NC)

R

+ R

(ON)

L

FIGURE 1A. MEASUREMENT POINTS

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

V+

C

SWITCH

OUTPUT

V

OUT

R

G

ΔV

COM

OUT

NO or NC

V

OUT

V+

0V

V

ON

GND

IN

G

LOGIC

INPUT

C

L

OFF

LOGIC

INPUT

Q = ΔV

x C

L

OUT

FIGURE 2B. TEST CIRCUIT

FIGURE 2A. MEASUREMENT POINTS

FIGURE 2. CHARGE INJECTION

V+

C

V+

0V

NO

LOGIC

INPUT

V

OUT

NX

COM

NC

C

35pF

R

50Ω

L

IN

GND

90%

LOGIC

INPUT

SWITCH

OUTPUT

V

OUT

0V

t

D

C

includes fixture and stray capacitance.

L

FIGURE 3A. MEASUREMENT POINTS

FIGURE 3. BREAK-BEFORE-MAKE TIME

FIGURE 3B. TEST CIRCUIT

FN6357.1

October 30, 2006

6

ISL54056

Test Circuits and Waveforms (Continued)

V+

C

R

= V /100mA

1

ON

SIGNAL

GENERATOR

NO or NC

V

NX

IN

0V or V+

100mA

IN

V

1

COM

ANALYZER

GND

R

L

FIGURE 4. OFF ISOLATION TEST CIRCUIT

FIGURE 5. R

TEST CIRCUIT

ON

V+

C

V+

C

SIGNAL

GENERATOR

50Ω

NO or NC

COM

NO or NC

IN

1

0V or V+

IN

0V or V+

IMPEDANCE

ANALYZER

COM

NC or NO

COM

ANALYZER

N.C.

GND

R

L

FIGURE 6. CROSSTALK TEST CIRCUIT

FIGURE 7. CAPACITANCE TEST CIRCUIT

Figure 8). To prevent forward biasing these diodes, V+ must

be applied before any input signals, and the input signal

voltages must remain between V+ and GND.

Detailed Description

The ISL54056 is a bidirectional, quad single pole/double

throw (SPDT) analog switch that offers precise switching

capability from a single 1.65V to 4.5V supply with low

on-resistance (0.39Ω) and high speed operation

If these conditions cannot be guaranteed, then precautions

must be implemented to prohibit the current and voltage at

the logic pin and signal pins from exceeding the maximum

ratings of the switch. The following two methods can be used

to provided additional protection to limit the current in the

event that the voltage at a signal pin or logic pin goes below

ground or above the V+ rail.

(t

= 30ns, t = 16ns). The device is especially well

ON

OFF

suited for portable battery powered equipment due to its low

operating supply voltage (1.65V), low power consumption

(6.3µW max), low leakage currents (165nA max), and the tiny

µTQFN package. The ultra low on-resistance and Ron

flatness provide very low insertion loss and distortion to

applications that require signal reproduction.

Logic inputs can be protected by adding a 1kΩ resistor in

series with the logic input (see Figure 8). The resistor limits

the input current below the threshold that produces

permanent damage, and the sub-microamp input current

produces an insignificant voltage drop during normal

operation.

Supply Sequencing and Overvoltage Protection

With any CMOS device, proper power supply sequencing is

required to protect the device from excessive input currents

which might permanently damage the IC. All I/O pins contain

ESD protection diodes from the pin to V+ and to GND (see

FN6357.1

October 30, 2006

7

ISL54056

This method is not acceptable for the signal path inputs.

Adding a series resistor to the switch input defeats the

the digital input signals from GND to V+ with a fast transition

time minimizes power dissipation.

purpose of using a low R

switch. Connecting schottky

ON

The ISL54056 has been designed to minimize the supply

current whenever the digital input voltage is not driven to the

supply rails (0V to V+). For example driving the device with

2.85V logic (0V to 2.85V) while operating with a 4.2V supply

the device draws only 12μA of current (see Figure 16 for

diodes to the signal pins as shown in Figure 8 will shunt the

fault current to the supply or to ground thereby protecting the

switch. These schottky diodes must be sized to handle the

expected fault current.

V

= 2.85V).

IN

OPTIONAL

SCHOTTKY

DIODE

High-Frequency Performance

In 50Ω systems, the ISL54056 has a -3dB bandwidth of

104MHz (see Figure 21). The frequency response is very

consistent over a wide V+ range, and for varying analog

signal levels.

V+

OPTIONAL

PROTECTION

RESISTOR

IN

V

X

V

NX

COM

An OFF switch acts like a capacitor and passes higher

frequencies with less attenuation, resulting in signal

feedthrough from a switch’s input to its output. Off Isolation is

the resistance to this feedthrough, while Crosstalk indicates

the amount of feedthrough from one switch to another.

Figure 22 details the high Off Isolation and Crosstalk

rejection provided by this part. At 100kHz, Off Isolation is

about 65dB in 50Ω systems, decreasing approximately 20dB

per decade as frequency increases. Higher load

GND

OPTIONAL

SCHOTTKY

DIODE

FIGURE 8. OVERVOLTAGE PROTECTION

Power-Supply Considerations

impedances decrease Off Isolation and Crosstalk rejection

due to the voltage divider action of the switch OFF

impedance and the load impedance.

The ISL54056 construction is typical of most single supply

CMOS analog switches, in that they have two supply pins:

V+ and GND. V+ and GND drive the internal CMOS

switches and set their analog voltage limits. Unlike switches

with a 4V maximum supply voltage, the ISL54056 4.7V

maximum supply voltage provides plenty of room for the

10% tolerance of 4.3V supplies, as well as room for

overshoot and noise spikes.

Leakage Considerations

Reverse ESD protection diodes are internally connected

between each analog-signal pin and both V+ and GND. One of

these diodes conducts if any analog signal exceeds V+ or

GND.

Virtually all the analog leakage current comes from the ESD

diodes to V+ or GND. Although the ESD diodes on a given

signal pin are identical and therefore fairly well balanced,

they are reverse biased differently. Each is biased by either

V+ or GND and the analog signal. This means their leakages

will vary as the signal varies. The difference in the two diode

leakages to the V+ and GND pins constitutes the analog-

signal-path leakage current. All analog leakage current flows

between each pin and one of the supply terminals, not to the

other switch terminal. This is why both sides of a given

switch can show leakage currents of the same or opposite

polarity. There is no connection between the analog signal

paths and V+ or GND.

The minimum recommended supply voltage is 1.65V. It is

important to note that the input signal range, switching times,

and on-resistance degrade at lower supply voltages. Refer

to the electrical specification tables and “Typical

Performance” curves for details.

V+ and GND also power the internal logic and level shiftiers.

The level shiftiers convert the input logic levels to switched

V+ and GND signals to drive the analog switch gate

terminals.

This family of switches cannot be operated with bipolar

supplies, because the input switching point becomes

negative in this configuration.

Logic-Level Thresholds

This switch family is 1.8V CMOS compatible (0.5V and 1.4V)

over a supply range of 3.0V to 4.5V (see Figure 14). At 3.0V

the V level is about 0.53V. This is still above the 1.8V

IL

CMOS guaranteed low output maximum level of 0.5V, but

noise margin is reduced.

The digital input stages draw supply current whenever the

digital input voltage is not at one of the supply rails. Driving

FN6357.1

October 30, 2006

8

ISL54056

Typical Performance Curves T = +25°C, unless otherwise specified

A

0.4

0.39

0.38

0.37

0.36

0.35

0.34

0.33

0.32

0.46

0.45

0.44

0.43

0.42

0.41

0.4

I = 100mA

COM

I

= 100mA

COM

V+ = 2.7V

V+ = 3V

0.39

0.38

0.37

0.36

V+ = 3.9V

V+ = 3.3V

V+ = 4.3V

V+ = 4.5V

3

0

1

2

4

5

0

0.5

1

1.5

2

2.5

3

3.5

V

(V)

V

(V)

COM

FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

FIGURE 10. ON RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

0.45

0.8

V+ = 4.3V

= 100mA

I

= 100mA

COM

I

COM

V+ = 1.65V

V+ = 1.8V

0.4

0.35

0.3

0.7

0.6

0.5

0.4

+85°C

+25°C

-40°C

V+ = 2V

0.25

0

0.5

1

1.5

2

0

1

2

3

4

5

V

(V)

V

(V)

COM

FIGURE 11. ON RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE

0.55

0.5

V+ = 3.3V

= 100mA

V+ = 2.7V

I = 100mA

COM

I

COM

0.5

0.45

0.4

0.45

0.4

+85°C

+25°C

-40°C

+85°C

+25°C

0.35

0.3

0.35

0.3

-40°C

0

0.5

1

1.5

(V)

2

2.5

3

0

0.5

1

1.5

2

2.5

3

3.5

V

(V)

V

COM

FIGURE 13. ON RESISTANCE vs SWITCH VOLTAGE

FIGURE 14. ON RESISTANCE vs SWITCH VOLTAGE

FN6357.1

October 30, 2006

9

ISL54056

Typical Performance Curves T = +25°C, unless otherwise specified (Continued)

A

200

0.7

V+ = 1.8V

= 100mA

+85°C

+25°C

V+ = 4.2V

I

COM

Sweeping Both Logic Inputs

0.65

0.6

150

100

50

-40°C

0.55

0.5

0.45

0.4

0

1

2

3

4

5

0.35

V

(V)

IN1&2

0

0.5

1

1.5

2

V

(V)

COM

FIGURE 15. ON RESISTANCE vs SWITCH VOLTAGE

FIGURE 16. SUPPLY CURRENT vs VLOGIC VOLTAGE

1

250

0.9

200

150

100

50

0.8

0.7

0.6

0.5

0.4

0.3

0.2

V

INH

V

INL

V+ = 4.3V

0

V+ = 1.8V

V+ = 3V

-50

-100

0

1

2

3

4

5

1.5

2

2.5

3

3.5

4

4.5

V

(V)

V+ (V)

COM

FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE

250

FIGURE 18. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE

40

35

30

200

150

100

25

+85°C

20

+25°C

+85°C

-40°C

50

0

-40°C

15

10

1

1.5

2

2.5

V+ (V)

3

3.5

4

4.5

1.5

2

2.5

V+ (V)

3

3.5

4

4.5

1

FIGURE 19. TURN-ON TIME vs SUPPLY VOLTAGE

FIGURE 20. TURN-OFF TIME vs SUPPLY VOLTAGE

FN6357.1

October 30, 2006

10

ISL54056

Typical Performance Curves T = +25°C, unless otherwise specified (Continued)

A

-10

10

20

30

40

50

60

70

80

90

V+ = 4.3V

V+ = 3V

-20

0

GAIN

-30

-20

-40

-50

0

PHASE

ISOLATION

-60

-70

-80

-90

20

40

60

CROSSTALK

80

R

= 50Ω

= 0.2V

100

L

-100

-110

100

110

V

to 2V

P-P P-P

IN

1M

10M

100M

600M

1k

10k

100k

1M

10M

100M 500M

FREQUENCY (Hz)

FIGURE 21. FREQUENCY RESPONSE

FIGURE 22. CROSSTALK AND OFF ISOLATION

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

TRANSISTOR COUNT:

228

PROCESS:

Si Gate CMOS

FN6357.1

October 30, 2006

11

ISL54056

Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)

L16.2.6x1.8A

D

A

B

16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

6

INDEX AREA

SYMBOL

MIN

0.45

NOMINAL

MAX

0.55

NOTES

N

E

A

A1

A3

b

0.50

-

2X

0.10 C

1 2

-

0.05

-

2X

0.10 C

0.127 REF

-

TOP VIEW

0.15

2.55

1.75

0.20

2.60

1.80

0.40 BSC

0.40

0.50

16

0.25

2.65

1.85

5

D

-

0.10 C

E

-

C

A

0.05 C

SEATING PLANE

e

-

L

0.35

0.45

0.55

-

A1

L1

N

-

SIDE VIEW

2

Nd

Ne

θ

4

3

e

4

3

PIN #1 ID

L1

1 2

0

-

12

4

NX L

Rev. 4 8/06

NOTES:

5

NX b

16X

(DATUM B)

(DATUM A)

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

0.10 M C A B

0.05 M C

3. Nd and Ne refer to the number of terminals on D and E side,

respectively.

BOTTOM VIEW

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

C

L

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

(A1)

NX (b)

5

L

7. Maximum package warpage is 0.05mm.

8. Maximum allowable burrs is 0.076mm in all directions.

9. JEDEC Reference MO-255.

e

SECTION "C-C"

TERMINAL TIP

C C

10. For additional information, to assist with the PCB Land Pattern

Design effort, see Intersil Technical Brief TB389.

3.00

1.80

1.40

0.90

1.40

2.20

0.40

0.20

0.40

0.50

10

LAND PATTERN

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6357.1

October 30, 2006

12


型号：	ISL54056
厂家：	Intersil
描述：	Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch 超低导通电阻， + 1.65V至+ 4.5V单电源，四路单刀双掷（ DPDT双）模拟开关开关光电二极管
文件：	总12页 (文件大小：281K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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