ISL54056_07 [INTERSIL]
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch; 超低导通电阻, + 1.65V至+ 4.5V单电源,四路单刀双掷( DPDT双)模拟开关型号: | ISL54056_07 |
厂家: | Intersil |
描述: | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch |
文件: | 总12页 (文件大小:281K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL54056
®
Data Sheet
August 15, 2007
FN6357.4
Ultra Low ON-Resistance, +1.65V to +4.5V,
Single Supply, Quad SPDT (Dual DPDT)
Analog Switch
Features
• Pin Compatible Replacement for the NLAS3799 and
NLAS3799L
The Intersil ISL54056 device is a low ON-resistance, low
voltage, bidirectional, Quad SPDT (Dual DPDT) analog
switch designed to operate from a single +1.65V to +4.5V
supply. Targeted applications include battery powered
• ON-Resistance (r
)
ON
- V+ = +4.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.39Ω
- V+ = +3.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45Ω
- V+ = +1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65Ω
equipment that benefit from low r
(0.39Ω) and fast
ON
• r
Matching between Channels . . . . . . . . . . . . . . . . . 0.05Ω
Flatness Across Signal Range . . . . . . . . . . . . . . . 0.05Ω
switching speeds (t
= 30ns, t
= 16ns). The digital logic
ON
ON
ON
OFF
input is 1.8V logic-compatible when using a single +3V supply.
With a supply voltage of 4.2V and logic high voltage of 2.85V
at both logic inputs, the part draws only 12µA max of ICC
current.
• r
• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V
• Low Power Consumption (PD) . . . . . . . . . . . . . . . . <0.68μW
• Fast Switching Action (V+ = +4.3V)
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL54056 is offered in small form factor package, alleviating
board space limitations.
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns
OFF
• Break-Before-Make
• 1.8V Logic Compatible (+3V supply)
• Low ICC Current when VinH is not at the V+ Rail
• Available in 16 Ld 2.6mmx1.8mmx0.5mm µTQFN
The ISL54056 consists of four SPDT switches. It is configured
as a dual double-pole/double-throw (DPDT) device with two
logic control inputs that control two SPDT switches each. The
configuration can be used as a dual differential 2-to-1
multiplexer/demultiplexer. The ISL54056 is pin compatible
with the NLAS3799 and NLAS3799L.
• ESD HBM Rating
- COM Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9kV
- All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
• Pb-Free Available (RoHS Compliant)
TABLE 1. FEATURES AT A GLANCE
ISL54056
Applications
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
Number of Switches
SW
4
Quad SPDT (Dual DPDT)
- Pagers
4.3V r
ON
0.39Ω
- Laptops, Notebooks, Palmtops
4.3V t /t
ON OFF
30ns/16ns
• Portable Test and Measurement
• Medical Equipment
3.0V r
ON
0.45Ω
• Audio and Video Switching
3.0V t /t
ON OFF
34ns/18ns
1.8V r
ON
0.65Ω
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
1.8V t /t
ON OFF
48ns/23ns
Package
16 Ld 2.6x1.8x0.5mm µTQFN
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54056
Truth Table
Pinouts (Note 1)
ISL54056
(16 LD µTQFN)
TOP VIEW
LOGIC
NC SW
ON
NO SW
OFF
0
1
OFF
ON
NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
Pin Descriptions
NC4
COM3
NO3
PIN
FUNCTION
System Power Supply Input (+1.65V to +4.5V)
Ground Connection
V+
NO1
V+
GND
NC2
GND
IN
COM1
Digital Control Input
COM
NO
Analog Switch Common Pin
Analog Switch Normally Open Pin
Analog Switch Normally Closed Pin
NC
NOTE:
1. Switches Shown for Logic “0” Input.
Ordering Information
PART NUMBER
PART MARKING
TEMP. RANGE (°C)
PACKAGE
16 Ld μTQFN Tape and Reel (Pb-free)
PKG. DWG. #
L16.2.6x1.8A
ISL54056IRUZ-T* (Note)
GAA
-40 to +85
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6357.4
August 15, 2007
2
ISL54056
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Input Voltages
NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
Thermal Resistance (Typical)
θ
(°C/W)
93
JA
μTQFN Package (Note 3) . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA
ESD Rating
Operating Conditions
Temperature Range
ISL54056IRUZ . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Human Body Model (COM ) . . . . . . . . . . . . . . . . . . . . . . . . .>9kV
X
Human Body Model (NO , NC , IN , V+, GND) . . . . . . . . . .>6kV
X
X
X
Machine Model (COM ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .>700V
X
Machine Model (NO , NC , IN , V+, GND). . . . . . . . . . . . .>300V
X
X
X
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V
Unless Otherwise Specified.
= 1.6V, V
= 0.5V (Note 4),
INL
INH
TEMP
(°C)
MIN
(Notes 5, 8)
MAX
PARAMETER
TEST CONDITIONS
TYP
(Notes 5, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
V+
0.55
0.65
0.12
0.15
0.15
0.15
70
V
Ω
ON-Resistance, r
V+ = 3.9V, I
COM
(See Figure 5)
= 100mA, V
or V = 0V to V+
NC
0.4
ON
NO
Full
25
0.45
0.05
0.06
0.05
0.05
Ω
r
Matching Between Channels, V+ = 3.9V, I
COM
= 100mA, V
NO
(Note 7)
or V
NC
= Voltage at
Ω
ON
Δr
max r
ON
ON
Full
25
Ω
r
Flatness, r
V+ = 3.9V, I
(Note 6)
= 100mA, V
or V = 0V to V+
NC
Ω
ON
FLAT(ON)
COM
NO
Full
25
Ω
NO or NC OFF Leakage Current,
or I
V+ = 4.5V, V
= 0.3V, 3V, V
NO
or V
NC
= 3V, 0.3V
-70
-165
-70
nA
nA
nA
nA
COM
I
NO(OFF)
NC(OFF)
Full
25
165
70
COM ON Leakage Current,
V+ = 4.5V, V
= 0.3V, 3V, or V
NO
or V
= 0.3V,
NC
COM
I
3V
COM(ON)
Full
-165
165
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 3.9V, V
or V
= 3.0V, R = 50Ω,
25
Full
25
33
38
16
21
3
ns
ns
ns
ns
ns
ON
NO
NC
L
C
= 35pF (See Figure 1)
L
Turn-OFF Time, t
V+ = 3.9V, V
or V
= 3.0V, R = 50Ω,
NC L
OFF
NO
= 35pF (See Figure 1)
C
L
Full
Full
Break-Before-Make Time Delay, t
V+ = 4.5V, V
or V
NC
= 3.0V, R = 50Ω, C
L
=
D
NO
35pF (See Figure 3)
L
Charge Injection, Q
OFF Isolation
C
R
= 1.0nF, V = 0V, R = 0Ω (See Figure 2)
25
25
248
65
pC
dB
L
L
G
G
= 50Ω, C = 5pF, f = 100kHz, V
= 1V
L
COM
RMS
(See Figure 4)
Crosstalk (Channel-to-Channel)
Total Harmonic Distortion
R
= 50Ω, C = 5pF, f = 100kHz, V
= 1V
25
25
-85
dB
%
L
L
COM
RMS
(See Figure 6)
f = 20Hz to 20kHz, V
= 2V , R = 600Ω
P-P
0.008
COM
L
FN6357.4
August 15, 2007
3
ISL54056
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V
Unless Otherwise Specified. (Continued)
= 1.6V, V
= 0.5V (Note 4),
INL
INH
TEMP
(°C)
MIN
(Notes 5, 8)
MAX
PARAMETER
TEST CONDITIONS
TYP
38
(Notes 5, 8) UNITS
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= V
= 0V (See Figure 7)
= 0V (See Figure 7)
25
25
pF
pF
OFF
NO
NC
NC
COM
COM ON Capacitance, C
102
COM(ON)
NO
COM
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
25
1.65
4.5
0.15
1.4
V
Positive Supply Current, I+
V+ = +4.5V, V = 0V or V+
IN
μA
μA
μA
Full
25
Positive Supply Current, I+
V+ = +4.2V, V = 2.85V
IN
12
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
0.5
0.5
V
V
INL
Input Voltage High, V
1.6
INH
Input Current, I
, I
V+ = 4.5V, V = 0V or V+
IN
-0.5
μA
INH INL
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V
Unless Otherwise Specified.
= 1.4V, V
= 0.5V (Note 4),
INL
INH
TEMP
(°C)
MIN
(Notes 5, 8)
MAX
(Notes 5, 8) UNITS
PARAMETER
TEST CONDITIONS
TYP
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
V+
V
Ω
ON-Resistance, r
V+ = 2.7V, I
COM
(See Figure 5)
= 100mA, V
or V = 0V to V+
NC
0.45
0.05
0.07
0.55
0.65
0.12
0.15
0.15
0.15
ON
NO
Full
25
Ω
r
Matching Between Channels, V+ = 2.7V, I
COM
= 100mA, V
NO
or V
NC
= Voltage at
Ω
ON
Δr
max r
(Note 7)
ON
ON
Full
25
Ω
r
Flatness, r
V+ = 2.7V, I
(Note 6)
= 100mA, V
or V = 0V to V+
NC
Ω
ON
FLAT(ON)
COM
NO
Full
25
Ω
NO or NC OFF Leakage Current,
or I
V+ = 3.3V, V
= 0.3V, 3V, V
NO
or V
NC
= 3V, 0.3V
1.1
30
nA
nA
nA
nA
COM
I
NO(OFF)
NC(OFF)
Full
25
COM ON Leakage Current,
V+ = 3.3V, V
= 0.3V, 3V, or V
or V
= 0.3V,
NC
1.5
45
COM
NO
I
3V, or Floating
COM(ON)
Full
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 2.7V, V
or V
= 1.5V, R = 50Ω,
25
Full
25
34
39
18
23
3
ns
ns
ns
ns
ns
ON
NO
NC
L
C
= 35pF (See Figure 1)
L
Turn-OFF Time, t
V+ = 2.7V, V
or V
= 1.5V, R = 50Ω,
NC L
OFF
NO
= 35pF (See Figure 1)
C
L
Full
Full
Break-Before-Make Time Delay, t
V+ = 3.3V, V
or V
= 1.5V, R = 50Ω, C
L
=
D
NO
35pF (See Figure 3)
NC
L
Charge Injection, Q
OFF Isolation
C
R
= 1.0nF, V = 0V, R = 0Ω (See Figure 2)
25
25
126
65
pC
dB
L
L
G
G
= 50Ω, C = 5pF, f = 100kHz, V
= 1V
L
COM
RMS
(See Figure 4)
Crosstalk (Channel-to-Channel)
Total Harmonic Distortion
R
= 50Ω, C = 5pF, f = 100kHz, V
= 1V
25
25
-85
dB
%
L
L
COM
RMS
(See Figure 6)
f = 20Hz to 20kHz, V
= 2V , R = 600Ω
P-P
0.012
COM
L
FN6357.4
August 15, 2007
4
ISL54056
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V
Unless Otherwise Specified. (Continued)
= 1.4V, V
= 0.5V (Note 4),
INL
INH
TEMP
(°C)
MIN
(Notes 5, 8)
MAX
(Notes 5, 8) UNITS
PARAMETER
TEST CONDITIONS
TYP
38
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= V
= 0V (See Figure 7)
= 0V (See Figure 7)
25
25
pF
pF
OFF
NO
NO
NC
NC
COM
COM
COM ON Capacitance, C
102
COM(ON)
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 3.6V, V = 0V or V+
25
0.021
0.72
μA
μA
IN
Full
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
0.5
V
V
INL
Input Voltage High, V
1.4
INH
Input Current, I
, I
V+ = 3.6V, V = 0V or V+
IN
-0.5
0.5
μA
INH INL
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2V, GND = 0V, V
Unless Otherwise Specified.
= 1.0V, V
= 0.4V (Note 4),
INL
INH
TEMP
(°C)
MIN
(Notes 5, 8)
MAX
PARAMETER
TEST CONDITIONS
TYP
(Notes 5, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
V+
0.8
V
Ω
Ω
ON-Resistance, r
V+ = 1.8V, I
= 100mA, V
or V = 0V to V+
NC
0.65
ON
COM
(See Figure 5)
NO
Full
0.85
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 1.65V, V
or V
= 1.0V, R = 50Ω,
25
Full
25
50
55
25
30
8
ns
ns
ns
ns
ns
ON
NO
NO
NC
NC
L
C
= 35pF (See Figure 1)
L
Turn-OFF Time, t
V+ = 1.65V, V
or V
= 1.0V, R = 50Ω,
L
OFF
C
= 35pF (See Figure 1)
L
Full
Full
Break-Before-Make Time Delay, t
Charge Injection, Q
V+ = 2.0V, V
NO
(See Figure 3)
or V
= 1.0V, R = 50Ω, C = 35pF
NC L L
D
C
= 1.0nF, V = 0V, R = 0Ω (See Figure 2)
25
48
pC
L
G
G
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
0.4
0.5
V
V
INL
Input Voltage High, V
1.0
INH
Input Current, I , I
INH INL
V+ = 2.0V, V = 0V or V+
IN
-0.5
μA
NOTES:
4. V = input voltage to perform proper function.
IN
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
7. r
matching between channels is calculated by subtracting the channel with the highest max r
value from the channel with lowest max r
ON ON
ON
value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4.
8. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
FN6357.4
August 15, 2007
5
ISL54056
Test Circuits and Waveforms
V+
V+
C
LOGIC
INPUT
50%
0V
NO
0V
t
V
OFF
OUT
NO or NC
IN
SWITCH
INPUT
COM
SWITCH
INPUT
V
V
OUT
90%
90%
C
L
35pF
R
50Ω
LOGIC
INPUT
L
GND
SWITCH
OUTPUT
t
ON
Repeat test for all switches. C includes fixture and stray
L
Logic input waveform is inverted for switches that have the opposite
logic sense.
capacitance.
R
L
-----------------------
V
= V
OUT
(NO or NC)
R
+ r
ON
L
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
SWITCH
OUTPUT
V
OUT
R
G
ΔV
COM
OUT
NO or NC
V
OUT
V+
0V
V
ON
ON
GND
IN
G
LOGIC
INPUT
C
L
OFF
LOGIC
INPUT
Q = ΔV
x C
L
OUT
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
C
V+
0V
NO
LOGIC
INPUT
V
V
OUT
NX
COM
NC
C
R
L
L
50Ω
35pF
IN
GND
90%
LOGIC
INPUT
SWITCH
OUTPUT
V
OUT
0V
t
D
C
includes fixture and stray capacitance.
L
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE TIME
FIGURE 3B. TEST CIRCUIT
FN6357.4
August 15, 2007
6
ISL54056
Test Circuits and Waveforms (Continued)
V+
V+
C
C
r
= V /100mA
1
ON
SIGNAL
GENERATOR
NO OR NC
NO OR NC
V
NX
IN
0V OR V+
0V OR V+
100mA
IN
V
1
COM
COM
ANALYZER
GND
GND
R
L
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. r
TEST CIRCUIT
ON
V+
C
V+
C
SIGNAL
GENERATOR
50Ω
NO OR NC
COM
NO OR NC
IN
1
0V OR V+
IN
0V OR V+
IMPEDANCE
ANALYZER
COM
NC OR NO
COM
ANALYZER
NC
GND
GND
R
L
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can
be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from
the V+ power supply to ground. This will result in a
significant amount of current flow in the IC, which can
potentially create a latch-up state or permanently damage
the IC. The external V+ resistor limits the current during this
over-stress situation and has been found to prevent latch-up
or destructive damage for many overvoltage transient
events.
Detailed Description
The ISL54056 is a bidirectional, quad single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 4.5V supply with low
ON-resistance (0.39Ω) and high speed operation
(t
= 30ns, t = 16ns). The device is especially well
ON
OFF
suited for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(6.3µW max), low leakage currents (165nA max), and the tiny
µTQFN package. The ultra low ON-resistance and r
flatness provide very low insertion loss and distortion to
applications that require signal reproduction.
ON
Under normal operation the sub-microamp I
current of the
DD
IC produces an insignificant voltage drop across the 100Ω
series resistor resulting in no impact to switch operation or
performance.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil
recommends adding a 100Ω resistor in series with the V+
power supply pin of the ISL54056 IC (see Figure 8).
FN6357.4
August 15, 2007
7
ISL54056
V+
C
OPTIONAL
SCHOTTKY
DIODE
OPTIONAL
PROTECTION
RESISTOR
V+
100Ω
OPTIONAL
PROTECTION
RESISTOR
NOx
NCx
IN
V
X
COMx
V
NX
COM
INx
GND
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
FIGURE 9. OVERVOLTAGE PROTECTION
Power-Supply Considerations
Supply Sequencing and Overvoltage Protection
The ISL54056 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4.7V maximum supply voltage, the ISL54056 5.5V
maximum supply voltage provides plenty of room for the
10% tolerance of 4.3V supplies, as well as room for
overshoot and noise spikes.
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 9). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
The minimum recommended supply voltage is 1.65V. It is
important to note that the input signal range, switching times,
and ON-resistance degrade at lower supply voltages. Refer to
the “Electrical Specifications” table on page 5 and “Typical
Performance Curves” on page 9 for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
Logic inputs can be protected by adding a 1kΩ resistor in series
with the logic input (see Figure 9). The resistor limits the input
current below the threshold that produces permanent damage,
and the sub-microamp input current produces an insignificant
voltage drop during normal operation.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch. Connecting Schottky
diodes to the signal pins as shown in Figure 9 will shunt the
fault current to the supply or to ground thereby protecting the
switch. These Schottky diodes must be sized to handle the
expected fault current.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 3.0V to 4.5V (see Figure 19). At 3.0V
the V level is about 0.53V. This is still above the 1.8V
IL
CMOS guaranteed low output maximum level of 0.5V, but
noise margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
The ISL54056 has been designed to minimize the supply
current whenever the digital input voltage is not driven to the
supply rails (0V to V+). For example driving the device with
2.85V logic (0V to 2.85V) while operating with a 4.2V supply
the device draws only 12μA of current (see Figure 17 for
V
= 2.85V).
IN
FN6357.4
August 15, 2007
8
ISL54056
High-Frequency Performance
Leakage Considerations
In 50Ω systems, the ISL54056 has a -3dB bandwidth of
104MHz (see Figure 22). The frequency response is very
consistent over a wide V+ range, and for varying analog
signal levels.
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off isolation is
the resistance to this feedthrough, while crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 23 details the high off isolation and crosstalk rejection
provided by this part. At 100kHz, off isolation is about 65dB
in 50Ω systems, decreasing approximately 20dB per decade
as frequency increases. Higher load impedances decrease
off isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load
impedance.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog signal
path leakage current. All analog leakage current flows between
each pin and one of the supply terminals, not to the other
switch terminal. This is why both sides of a given switch can
show leakage currents of the same or opposite polarity.
There is no connection between the analog signal paths and
V+ or GND.
Typical Performance Curves T = +25°C, unless otherwise specified
A
0.40
0.39
0.38
0.37
0.36
0.35
0.34
0.33
0.32
0.46
0.45
0.44
0.43
0.42
0.41
0.40
0.39
0.38
0.37
0.36
I
= 100mA
I
= 100mA
COM
COM
V+ = 2.7V
V+ = 3V
V+ = 3.9V
V+ = 4.3V
V+ = 3.3V
V+ = 4.5V
3
0
1
2
4
5
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
V
(V)
V
COM
COM
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.45
0.8
V+ = 4.3V
= 100mA
I
= 100mA
COM
I
COM
V+ = 1.65V
V+ = 1.8V
0.40
0.35
0.30
0.25
0.7
0.6
0.5
0.4
+85°C
+25°C
V+ = 2V
-40°C
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
V
(V)
V
(V)
COM
COM
FIGURE 12. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
FN6357.4
August 15, 2007
9
ISL54056
Typical Performance Curves T = +25°C, unless otherwise specified (Continued)
A
0.50
0.45
0.40
0.35
0.30
0.55
0.50
0.45
0.40
0.35
0.30
V+ = 2.7V
= 100mA
V+ = 3.3V
= 100mA
I
COM
I
COM
+85°C
+25°C
+85°C
+25°C
-40°C
-40°C
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
V
V
COM
COM
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
0.70
200
V+ = 1.8V
= 100mA
+85°C
+25°C
V+ = 4.2V
SWEEPING BOTH LOGIC INPUTS
I
COM
0.65
0.60
0.55
0.50
0.45
0.40
0.35
150
100
50
-40°C
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
V V (V)
V
(V)
IN1, IN 2
COM
FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 17. SUPPLY CURRENT vs VLOGIC VOLTAGE
250
200
150
100
1.0
0.9
0.8
V
INH
0.7
0.6
0.5
0.4
0.3
0.2
V
INL
50
V+ = 4.3V
0
V+ = 1.8V
V+ = 3V
-50
-100
0
1
2
3
4
5
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
4.5
V
(V)
COM
FIGURE 18. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FN6357.4
August 15, 2007
10
ISL54056
Typical Performance Curves T = +25°C, unless otherwise specified (Continued)
A
250
200
150
100
50
40
35
30
25
20
15
10
+85°C
-40°C
+25°C
+25°C
4.0
+85°C
-40°C
0
1.0
1.5
2.0
2.5
3.0
3.5
4.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V+ (V)
V+ (V)
FIGURE 20. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 21. TURN-OFF TIME vs SUPPLY VOLTAGE
-10
-20
-30
-40
-50
-60
-70
-80
-90
10
V+ = 3V
GAIN
V+ = 4.3V
20
30
40
50
60
70
80
90
0
-20
0
PHASE
ISOLATION
20
40
60
CROSSTALK
80
-100
-110
100
110
R
= 50Ω
= 0.2V
100
L
V
to 2V
P-P P-P
IN
1M
10M
100M
600M
1k
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 22. FREQUENCY RESPONSE
FIGURE 23. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
228
PROCESS:
Si Gate CMOS
FN6357.4
August 15, 2007
11
ISL54056
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
L16.2.6x1.8A
D
A
B
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
6
INDEX AREA
SYMBOL
MIN
0.45
NOMINAL
MAX
0.55
NOTES
N
E
A
A1
A3
b
0.50
-
2X
0.10 C
1 2
-
-
0.05
-
2X
0.10 C
0.127 REF
-
TOP VIEW
0.15
2.55
1.75
0.20
2.60
1.80
0.40 BSC
0.40
0.50
16
0.25
2.65
1.85
5
D
-
0.10 C
E
-
C
A
0.05 C
SEATING PLANE
e
-
L
0.35
0.45
0.45
0.55
-
A1
L1
N
-
SIDE VIEW
2
Nd
Ne
θ
4
3
e
4
3
PIN #1 ID
L1
1 2
0
-
12
4
NX L
Rev. 4 8/06
NOTES:
5
NX b
16X
(DATUM B)
(DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
0.10 M C A B
0.05 M C
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
BOTTOM VIEW
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
C
L
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
(A1)
NX (b)
5
L
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
e
SECTION "C-C"
TERMINAL TIP
C C
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
3.00
1.80
1.40
0.90
1.40
2.20
0.40
0.20
0.20
0.40
0.50
10
LAND PATTERN
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6357.4
August 15, 2007
12
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