ISL28248FUZ [INTERSIL]
4.5MHz, Single Dual and Quad Precision Rail-to-Rail Input-Output (RRIO) Op Amps with Very Low Input Bias Current; 4.5MHz ，单路双路和四路精密轨到轨输入输出（ RRIO ）运算放大器具有极低的输入偏置电流
| 型号： | ISL28248FUZ |
| 厂家： | 
Intersil |
| 描述： | 4.5MHz, Single Dual and Quad Precision Rail-to-Rail Input-Output (RRIO) Op Amps with Very Low Input Bias Current |
| 文件： | 总20页 (文件大小：937K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL28148, ISL28248, ISL28448
®
Data Sheet
March 13, 2008
FN6337.2
4.5MHz, Single Dual and Quad Precision
Rail-to-Rail Input-Output (RRIO) Op Amps
with Very Low Input Bias Current
Features
• 4.5MHz gain bandwidth product
• 900µA supply current (per amplifier)
• 1.8mV maximum offset voltage
• 1pA typical input bias current
• Down to 2.4V single supply operation
• Rail-to-rail input and output
The ISL28148, ISL28248 and ISL28448 are 4.5MHz
low-power single, dual and quad operational amplifiers. The
parts are optimized for single supply operation from 2.4V to
5.5V, allowing operation from one lithium cell or two Ni-Cd
batteries.
The single, dual and quad feature an Input Range
Enhancement Circuit (IREC) which enables them to maintain
CMRR performance for input voltages greater than the
positive supply. The input signal is capable of swinging
0.25V above the positive supply and to 100mV below the
negative supply with only a slight degradation of the CMRR
performance. The output operation is rail-to-rail.
• Enable pin (ISL28148 SOT-23 package only)
• -40°C to +125°C operation
• Pb-free (RoHS compliant)
Applications
• Low-end audio
The parts draw minimal supply current (900µA per amplifier)
while meeting excellent DC accuracy, AC performance,
noise and output drive specifications. The ISL28148 features
an enable pin that can be used to turn the device off and
reduce the supply current to a maximum of 16µA. Operation
is guaranteed over -40°C to +125°C temperature range.
• 4mA to 20mA current loops
• Medical devices
• Sensor amplifiers
• ADC buffers
• DAC output amplifiers
Ordering Information
PACKAGE
PART NUMBER
ISL28148FHZ-T7* (Note 1)
PART MARKING
(Pb-free)
6 Ld SOT-23 (Tape and Reel)
6 Ld SOT-23 (Tape and Reel)
6 Ld WLCSP (1.5mmx1.0mm)
8 Ld SOIC
PKG. DWG. #
MDP0038
GABT
GABT
178Z
ISL28148FHZ-T7A* (Note 1)
MDP0038
W3x2.6C
MDP0027
MDP0027
MDP0043
MDP0043
MDP0044
MDP0044
Coming Soon, ISL28148FIZ-T7 (Note 2)
Coming Soon, ISL28248FBZ (Note 1)
Coming Soon, ISL28248FBZ-T7* (Note 1)
Coming Soon, ISL28248FUZ (Note 1)
Coming Soon, ISL28248FUZ-T7* (Note 1)
Coming Soon, ISL28448FVZ (Note 1)
Coming Soon, ISL28448FVZ-T7* (Note 1)
28248BZ
28248BZ
8248Z
8248Z
MXZ
8 Ld SOIC (Tape and Reel)
8 Ld MSOP
8 Ld MSOP (Tape and Reel)
14 Ld TSSOP
MXZ
14 Ld TSSOP (Tape and Reel)
*Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
2. These Intersil Pb-free WLCSP and BGA packaged products products employ special Pb-free material sets; molding compounds/die attach
materials and SnAgCu - e1 solder ball terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free WLCSP and BGA packaged products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007, 2008. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL28148, ISL28248, ISL28448
Pinouts
ISL28148
(6 LD SOT-23)
TOP VIEW
OUT
V-
1
2
3
6
5
4
V+
EN
IN-
+
-
IN+
ISL28148
(6 LD WLCSP)
TOP VIEW
1
2
A
NC
V +
IN -
OUT
V -
B
C
IN +
ISL28248
(8 LD SOIC)
TOP VIEW
ISL28248
(8 LD MSOP)
TOP VIEW
OUT_A
IN-_A
IN+_A
V-
1
2
3
4
8
7
6
5
V+
OUT_A
IN-_A
IN+_A
V-
1
2
3
4
8
7
6
5
V+
OUT_B
IN-_B
IN+_B
OUT_B
IN-_B
IN+_B
-
+
- +
+
-
+ -
ISL28448
(14 LD TSSOP)
TOP VIEW
OUT_A
IN-_A
IN+_A
V+
1
2
3
4
5
6
7
14 OUT_D
13 IN-_D
12 IN+_D
11 V-
-
+
+
-
IN+_B
IN-_B
OUT_B
10 IN+_C
+
-
+ -
9
8
IN-_C
OUT_C
FN6337.2
March 13, 2008
2
ISL28148, ISL28248, ISL28448
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/μs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Rating
Thermal Resistance (Typical, Note 3)
θ
(°C/W)
JA
6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . .
6 Ld WLCSP Package . . . . . . . . . . . . . . . . . . . . . . .
8 Ld SO Package. . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . .
14 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
230
130
125
175
115
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V+ = 5V, V- = 0V,V
= 2.5V, R = Open, T = +25°C unless otherwise specified.
L A
Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data
CM
established by characterization.
MIN
MAX
PARAMETER
DESCRIPTION
Input Offset Voltage
CONDITIONS
(Note 4)
TYP
(Note 4) UNIT
0
V
-1.8
1.8
mV
OS
-2
2
-0.1
0.03
±5
CSP package
-1.0
-1.2
1.0
1.2
ΔV
Input Offset Voltage vs Temperature
Input Offset Current
µV/°C
pA
OS
---------------
ΔT
I
-35
35
OS
T
= -40°C to +85°C
-80
80
A
I
Input Bias Current
-30
±1
30
pA
B
T
= -40°C to +85°C
-80
80
A
CSP package
-40
±1
30
-90
80
CMIR
Common-Mode Voltage Range
Common-Mode Rejection Ratio
Guaranteed by CMRR
0
5
V
CMRR
V
V
V
V
= 0V to 5V
75
70
98
98
dB
CM
PSRR
Power Supply Rejection Ratio
Large Signal Voltage Gain
= 2.4V to 5.5V
80
75
dB
+
A
= 0.5V to 4.5V, R = 100kΩ to V
CM
200
150
580
V/mV
VOL
O
O
L
= 0.5V to 4.5V, R = 1kΩ to V
50
3
V/mV
mV
L
CM
V
Maximum Output Voltage Swing
Output low, R = 100kΩ to V
CM
6
OUT
L
8
Output low, R = 1kΩ to V
50
70
110
mV
V
L
CM
Output high, R = 100kΩ to V
4.994
4.99
4.998
4.95
L
CM
Output high, R = 1kΩ to V
4.93
V
L
CM
4.89
FN6337.2
March 13, 2008
3
ISL28148, ISL28248, ISL28448
Electrical Specifications V+ = 5V, V- = 0V,V
= 2.5V, R = Open, T = +25°C unless otherwise specified.
L A
Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data
CM
established by characterization. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 4)
TYP
(Note 4) UNIT
I
I
Quiescent Supply Current, Enabled
0.7
0.4
0.9
1.1
1.4
mA
S,ON
Quiescent Supply Current, Disabled
Short-Circuit Output Source Current
Short-Circuit Output Sink Current
ISL28148 SOT-23 package only
10
75
68
14
16
µA
S,OFF
I +
R
R
= 10Ω to V
= 10Ω to V
48
45
mA
mA
O
L
L
CM
CM
I -
50
O
45
V
V
V
Supply Operating Range
EN Pin High Level
V+ to V-
2.4
2
5.5
0.8
V
V
SUPPLY
ENH
ISL28148 SOT-23 package only
ISL28148 SOT-23 package only
EN Pin Low Level
V
ENL
I
EN Pin Input High Current
V
= V+,ISL28148 SOT-23 package
1
1.5
1.6
µA
ENH
EN
only
I
EN Pin Input Low Current
V
= V-, ISL28148 SOT-23 package only
EN
12
25
nA
ENL
30
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
A
R
= 100, R = 100kΩ, R = 1kΩ,
4.5
13
MHz
MHz
V
F
G
= 10kΩ to V
L
CM
Unity Gain
Bandwidth
-3dB Bandwidth
A
=1, R = 0Ω, V
= 10mV
,
P-P
V
F
OUT
= 10kΩ to V
CM
R
L
e
Input Noise Voltage Peak-to-Peak
Input Noise Voltage Density
Input Noise Current Density
f = 0.1Hz to 10Hz
2
28
µV
PP
N
f
f
= 1kHz
= 1kHz
nV/√Hz
pA/√Hz
dB
O
i
0.016
85
N
O
CMRR @ 60Hz Input Common Mode Rejection Ratio
V
= 1V , R = 10kΩ to V
P-P CM
CM
L
PSRR- @
120Hz
Power Supply Rejection Ratio (V )
V , V = ±1.2V and ±2.5V,
-82
dB
-
+
-
V
= 1V , R = 10kΩ to V
P-P
SOURCE
L
CM
CM
PSRR+ @
120Hz
Power Supply Rejection Ratio (V )
V , V = ±1.2V and ±2.5V
-100
dB
+
+
-
V
= 1V , R = 10kΩ to V
P-P
SOURCE
L
TRANSIENT RESPONSE
SR
t , t , Large
Slew Rate
±4
V/µs
ns
Rise Time, 10% to 90%, V
A
= +2,
V
= 3V , R = R = 10kΩ
P-P
530
r
f
OUT
V
OUT
G
F
Signal
RL = 10kΩ to V
CM
Fall Time, 90% to 10%, V
A
RL
= +2,
V
= 3V , R = R = 10kΩ
530
50
50
5
ns
ns
ns
µs
µs
OUT
V
OUT
= 10kΩ to V
P-P
G
F
CM
t , t , Small
Rise Time, 10% to 90%, V
A
= +2,
V
= 10mV
=
,
r
f
OUT
V
OUT
= R = RL
P-P
10kΩ to V
CM
Signal
R
G
F
Fall Time, 90% to 10%, V
A
= +2,
V
= 10mV
,
P-P
OUT
V
OUT
= R = RL = 10kΩ to V
CM
R
G
F
t
Enable to Output Turn-on Delay Time, 10%
EN to 10% V , (ISL28148)
= 5V to 0V, A = +2,
EN V
R
EN
= R = RL = 1k to V
OUT
Enable to Output Turn-off Delay Time, 10%
EN to 10% V , (ISL28148)
G
F
CM
V
R
= 0V to 5V, A = +2,
0.2
EN
V
= R = RL = 1k to V
OUT
G
F CM
NOTE:
4. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
FN6337.2
March 13, 2008
4
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V = 2.5V, R = Open
CM
L
15
10
5
1
0
V
= 100mV
= 50mV
= 10mV
OUT
-1
-2
-3
-4
-5
-6
-7
-8
-9
R = R = 100k
f
g
V
R = R = 10k
OUT
OUT
f
g
V
V
= 1V
0
OUT
V
R
= 5V
= 1k
+
L
L
-5
R = R = 1k
V
R
= 5V
= 1k
f
g
+
L
L
C
= 16.3pF
= +2
-10
A
V
C
= 16.3pF
= +1
V
= 10mV
OUT
P-P
10k
A
V
-15
100
1k
10k
100k
1M
10M
100M
1k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. GAIN vs FREQUENCY vs FEEDBACK RESISTOR
FIGURE 2. GAIN vs FREQUENCY vs V
R = 1k
L
OUT,
VALUES R /R
f
g
1
0
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
V
= 100mV
= 50mV
OUT
V
= 100mV
= 50mV
= 10mV
-1
-2
-3
-4
-5
-6
-7
-8
-9
OUT
OUT
V
V
V
OUT
OUT
= 10mV
V
OUT
= 1V
V
V
= 1V
OUT
OUT
V
= 5V
= 10k
V
= 5V
= 100k
+
L
L
+
L
L
R
C
A
R
C
A
= 16.3pF
= +1
= 16.3pF
= +1
V
V
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 4. GAIN vs FREQUENCY vs V
70
, R = 100k
OUT
FIGURE 3. GAIN vs FREQUENCY vs V
1
, R = 10k
OUT
L
L
R
= 1k
A
= 1, R = INF, R = 0
L
V
V
g f
A
= 1001
V
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
A
= 10, R = 1k, R = 9.09k
g f
60
50
40
30
20
10
0
A
= 101, R = 1k, R = 100k
V
g f
R
= 10k
L
A = 1001, R = 1k, R = 1M
V g f
A
= 101
V
R
= 100k
L
V
C
R
V
= 5V
+
L
L
= 16.3pF
= 10k
A
= 10
V
= 10mV
OUT
P-P
V
V
= 5V
+
= 10mV
= 16.3pF
= +1
OUT
P-P
A
= 1
V
C
L
A
V
-10
100
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. GAIN vs FREQUENCY vs R
FIGURE 6. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
L
FN6337.2
March 13, 2008
5
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V = 2.5V, R = Open (Continued)
CM
L
1
0
8
7
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
C
C
C
= 51.7pF
= 43.7pF
= 37.7pF
L
L
V
= 5V
-1
-2
-3
-4
-5
-6
-7
-8
-9
+
L
V
= 2.4V
+
C
= 26.7pF
= 16.7pF
= 4.7pF
L
R
C
A
= 10k
L
L
V
R
= 5V
= 1k
= +1
+
C
L
= 16.3pF
= +1
L
C
L
V
A
V
V
= 10mV
V
= 10mV
OUT
P-P
OUT
P-P
10k
100k
1M
FREQUENCY (Hz)
10M
100M
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 7. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FIGURE 8. GAIN vs FREQUENCY vs C
L
10
0
20
0
-10
-20
-30
-40
-50
PSRR-
PSRR+
-20
-40
-60
-80
-100
-120
V
= 2.4V, 5V
= 1k
V , V = ±1.2V
+
L
L
+
-
R
C
A
-60
-70
-80
-90
R
= 1k
L
L
= 16.3pF
= +1
C
A
= 16.3pF
= +1
V
V
V
= 1V
V
= 1V
CM
P-P
CM
P-P
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. CMRR vs FREQUENCY; V = 2.4V AND 5V
+
FIGURE 10. PSRR vs FREQUENCY, V , V = ±1.2V
+
-
20
0
1000
100
10
PSRR-
PSRR+
-20
-40
V = 5V
+
R =1k R =1k
f
g
A
= +2
V
-60
V , V = ±2.5V
+
-
R
= 1k
-80
L
L
C
A
= 16.3pF
= +1
-100
V
V
= 1V
P-P
CM
-120
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 12. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY
FIGURE 11. PSRR vs FREQUENCY V , V = ±2.5V
+
-
FN6337.2
March 13, 2008
6
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V = 2.5V, R = Open (Continued)
CM
L
0.1
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
V
= 5V
+
R =1k R =1k
f
g
A
= +2
V
R
= 10k
A = 10k
V
V
C
= 5V
= 16.3pF
= 10
L
+
L
R
R = 100k
g
f
0.01
1
10
100
1k
10k
100k
0
1
2
3
4
5
6
7
8
9
10
TIME (s)
FREQUENCY (Hz)
FIGURE 13. INPUT CURRENT NOISE DENSITY vs FREQUENCY
FIGURE 14. INPUT VOLTAGE NOISE 0.1Hz TO 10Hz
0.025
2.0
1.5
1.0
0.5
0.020
0.015
0.010
0
V , V = ±2.5V
V , V = ±2.5V
+
-
+
-
-0.5
-1.0
-1.5
-2.0
R
= 1k
R
= 1k
L
L
L
L
g
C
= 16.3pF
C
R
A
= 16.3pF
R = R = 10k
= R = 10k
g
f
f
A
OUT
= 2
= 2
V
V
OUT
V
= 10mV
V
= 3V
P-P
6
P-P
0
1
2
3
4
5
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
TIME (µs)
FIGURE 15. LARGE SIGNAL STEP RESPONSE
3.5
FIGURE 16. SMALL SIGNAL STEP RESPONSE
1.2
1.0
0.8
0.6
0.4
0.2
0
V
OUT
V
EN
3.0
2.5
2.0
1.5
1.0
0.5
0
V
R
= 5V
= R = 10k
+
g
L
f
C
= 16.3pF
= +2
A
V
V
= 1V
P-P
OUT
R
= 10k
L
-0.2
90 100
-0.5
0
10
20
30
40
50
60
70
80
TIME (µs)
FIGURE 17. ISL28148 ENABLE TO OUTPUT RESPONSE
FN6337.2
March 13, 2008
7
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V = 2.5V, R = Open (Continued)
CM
L
100
80
800
600
400
200
0
V = 5V
+
V
R
= 5V
= OPEN
+
L
R
= OPEN
L
60
R
= 100k, R = 100
g
R = 100k, R = 100
f
f
g
40
A = +1k
A
= +1k
V
V
20
0
-20
-40
-60
-80
-100
-200
-400
-600
-800
-1
0
1
2
3
4
5
6
-1
0
1
2
3
4
5
6
V
(V)
V
(V)
CM
CM
FIGURE 19. INPUT BIAS CURRENT vs COMMON MODE
INPUT VOLTAGE
FIGURE 18. INPUT OFFSET VOLTAGE vs COMMON MODE
INPUT VOLTAGE
1.2
10.5
MAX
9.5
1.1
MAX
8.5
1.0
MEDIAN
7.5
MEDIAN
0.9
6.5
0.8
MIN
MIN
5.5
0.7
0.6
4.5
3.5
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 20. SUPPLY CURRENT ENABLED vs TEMPERATURE
FIGURE 21. SUPPLY CURRENT DISABLED vs
V , V = ±2.5V
TEMPERATURE V , V = ±2.5V
+
-
+
-
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
MAX
MAX
MEDIAN
MEDIAN
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
MIN
MIN
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 22. V
vs TEMPERATURE V = 0V, V , V = ±2.75V
IN
FIGURE 23. V
vs TEMPERATURE V = 0V, V , V = ±2.5V
IN
OS
+
-
OS
+
-
FN6337.2
March 13, 2008
8
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V = 2.5V, R = Open (Continued)
CM
L
2.0
1.5
1.0
0.5
0
1.5
1
MAX
MAX
0.5
0
MEDIAN
MEDIAN
-0.5
-1.0
-1.5
-2.0
-0.5
-1
MIN
MIN
-1.5
-40
-20
V
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 25. CSP PACKAGE V
vs TEMPERATURE V = 0V,
IN
FIGURE 24.
vs TEMPERATURE V = 0V, V , V = ±1.2V
OS
OS
IN
+
-
V , V = ±2.75V
+
-
1.5
1
1.5
1
MAX
MAX
0.5
0
0.5
0
MEDIAN
MEDIAN
-0.5
-1
-0.5
-1
MIN
MIN
-1.5
-1.5
-40
-40
-20
0
20
40
60
80
100 120
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 27. CSP PACKAGE V vs TEMPERATURE V = 0V,
OS IN
FIGURE 26. CSP PACKAGE V
OS
vs TEMPERATURE V = 0V,
IN
V , V = ±1.2V
V , V = ±2.5V
+
-
+
-
300
250
200
150
100
50
250
200
150
100
50
MAX
MAX
MEDIAN
MEDIAN
MIN
MIN
0
0
-50
-40
-50
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 29. I
- vs TEMPERATURE V , V = ±1.2V
BIAS
FIGURE 28.
I
- vs TEMPERATURE V , V = ±2.5V
BIAS
+
-
+
-
FN6337.2
March 13, 2008
9
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V = 2.5V, R = Open (Continued)
CM
L
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
MAX
MEDIAN
MAX
MEDIAN
MIN
MIN
0
0
-50
-50
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (C)
Temperature (C)
FIGURE 31. CSP PACKAGE I
V , V = ±1.2V
- vs TEMPERATURE
FIGURE 30. CSP PACKAGE I
V , V = ±2.5V
- vs TEMPERATURE
BIAS
BIAS
+
-
+
-
10
0
20
10
MAX
MEDIAN
MIN
-10
-20
-30
-40
-50
-60
-70
0
MAX
-10
-20
-30
-40
-50
-60
MEDIAN
MIN
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 32. I
vs TEMPERATURE V , V = ±2.5V
+ -
FIGURE 33. I
80
vs TEMPERATURE V , V = ±1.2V
OS
OS
+
-
1750
1550
1350
1150
950
70
60
50
40
30
20
MAX
MAX
MEDIAN
MIN
MEDIAN
750
550
MIN
350
150
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 35. A
V
vs TEMPERATURE R = 1k, V , V = ±2.5V,
L + -
FIGURE 34. A
V
vs TEMPERATURE R = 100k, V , V = ±2.5V,
L + -
VOL
= -2V TO +2V
VOL
= -2V TO +2V
O
O
FN6337.2
March 13, 2008
10
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V = 2.5V, R = Open (Continued)
CM
L
140
130
120
110
100
90
140
130
120
110
100
90
MAX
MAX
MEDIAN
MIN
MEDIAN
MIN
80
80
70
-40
70
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 36. CMRR vs TEMPERATURE V
= -2.5V TO +2.5V,
FIGURE 37. PSRR vs TEMPERATURE V V = ±1.2V TO ±2.75V
CM
+,
-
V
V = ±2.5V
-
+,
4.9994
4.9992
4.9990
4.9988
4.9986
4.9984
4.9982
4.970
4.965
4.960
4.955
4.950
4.945
4.940
MAX
MAX
MEDIAN
MEDIAN
MIN
MIN
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 39. V
HIGH vs TEMPERATURE R = 100k,
L
OUT
FIGURE 38. V
HIGH vs TEMPERATURE R = 1k,
L
OUT
V , V = ±2.5V
+
-
V , V = ±2.5V
+
-
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
75
70
65
60
55
50
45
40
MAX
MAX
MEDIAN
MEDIAN
MIN
MIN
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 41. V
LOW vs TEMPERATURE R = 100k,
L
FIGURE 40. V
LOW vs TEMPERATURE R = 1k,
L
OUT
V , V = ±2.5V
OUT
V , V = ±2.5V
+
-
+
-
FN6337.2
March 13, 2008
11
ISL28148, ISL28248, ISL28448
Typical Performance Curves V+ = 5V, V- = 0V, V = 2.5V, R = Open (Continued)
CM
L
-50
-55
-60
-65
-70
-75
-80
-85
95
90
85
80
75
70
65
60
MAX
MIN
MAX
MEDIAN
MEDIAN
MIN
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 43. - OUTPUT SHORT CIRCUIT CURRENT vs
TEMPERATURE V = -2.55V, R = 10,
FIGURE 42. + OUTPUT SHORT CIRCUIT CURRENT vs
TEMPERATURE V = -2.55V, R = 10,
IN
L
IN
L
V , V = ±2.5V
V , V = ±2.5V
+
-
+
-
Pin Descriptions
ISL28248
(8 Ld SO)
ISL28148
ISL28148
ISL28448
(6 Ld SOT-23)
6 Ld WLCSP (8 Ld MSOP)
(14 Ld TSSOP)
PIN NAME
FUNCTION
Not connected
inverting input
EQUIVALENT CIRCUIT
NC
4
C1
IN-
2 (A)
6 (B)
2 (A)
6 (B)
9 (C)
13 (D)
IN-_A
IN-_B
IN-_C
IN-_D
V+
IN-
IN+
V-
Circuit 1
3
2
C2
IN+
Non-inverting
input
(See circuit 1)
3 (A)
5 (B)
3 (A)
5 (B)
10 (C)
12 (D)
IN+_A
IN+_B
IN+_C
IN+_D
B2
4
11
V-
Negative supply
V+
V-
CAPACITIVELY
COUPLED
ESD CLAMP
Circuit 2
V+
1
A2
OUT
Output
1 (A)
7 (B)
1 (A)
7 (B)
8 (C)
14 (D)
OUT_A
OUT_B
OUT_C
OUT_D
OUT
V-
Circuit 3
6
B1
8
4
V+
Positive supply
(See circuit 2)
FN6337.2
March 13, 2008
12
ISL28148, ISL28248, ISL28448
Pin Descriptions (Continued)
ISL28248
(8 Ld SO)
ISL28148
ISL28148
ISL28448
(6 Ld SOT-23)
6 Ld WLCSP (8 Ld MSOP)
(14 Ld TSSOP)
PIN NAME
FUNCTION
EQUIVALENT CIRCUIT
EN
V+
5
-
Chip enable
EN
V-
Circuit 4
NC
A1
Connect pin to
the most
Negative Supply
Results of Over-Driving the Output
Applications Information
Caution should be used when over-driving the output for long
periods of time. Over-driving the output can occur in two ways:
Introduction
The ISL28148, ISL28248 and ISL28448 are single, dual and
quad channel CMOS rail-to-rail input, output (RRIO)
micropower precision operational amplifiers. The parts are
designed to operate from single supply (2.4V to 5.5V) or dual
supply (±1.2V to ±2.75V). The parts have an input common
mode range that extends 0.25V above the positive rail and
100mV below the negative supply rail. The output operation
can swing within about 3mV of the supply rails with a 100kΩ
load.
1. The input voltage times the gain of the amplifier exceeds the
supply voltage by a large value or
2. The output current required is higher than the output stage
can deliver. These conditions can result in a shift in the Input
Offset Voltage (V ) as much as 1µV/hr. of exposure under
OS
these condition.
IN+ and IN- Input Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. They also contain
back-to-back diodes across the input terminals (“Pin
Descriptions” table - Circuit 1 on page 12). For applications
where the input differential voltage is expected to exceed
0.5V, an external series resistor must be used to ensure the
input currents never exceed 5mA (Figure 44).
Rail-to-Rail Input
Many rail-to-rail input stages use two differential input pairs,
a long-tail PNP (or PFET) and an NPN (or NFET). Severe
penalties have to be paid for this circuit topology. As the
input signal moves from one supply rail to another, the
operational amplifier switches from one input pair to the
other causing drastic changes in input offset voltage and an
undesired change in magnitude and polarity of input offset
current.
-
V
R
OUT
IN
V
R
IN
+
L
The parts achieve input rail-to-rail operation without
sacrificing important precision specifications and degrading
distortion performance. The devices’ input offset voltage
exhibits a smooth behavior throughout the entire
common-mode input range. The input bias current vs the
common-mode voltage range gives us an undistorted
behavior from typically 100mV below the negative rail and
0.25V higher than the V+ rail.
FIGURE 44. INPUT CURRENT LIMITING
Enable/Disable Feature
The ISL28148 offers an EN pin that disables the device
when pulled up to at least 2.0V. In the disabled state (output
in a high impedance state), the part consumes typically 10µA
at room temperature. By disabling the part, multiple
Rail-to-Rail Output
A pair of complementary MOS devices are used to achieve
the rail-to-rail output swing. The NMOS sinks current to
swing the output in the negative direction. The PMOS
sources current to swing the output in the positive direction.
The devices’ with a 100kΩ load will swing to within 3mV of
the positive supply rail and within 3mV of the negative supply
rail.
ISL28148 parts can be connected together as a MUX. In this
configuration, the outputs are tied together in parallel and a
channel can be selected by the EN pin. The loading effects
of the feedback resistors of the disabled amplifier must be
considered when multiple amplifier outputs are connected
together. Note that feed through from the IN+ to IN- pins
occurs on any Mux Amp disabled channel where the input
differential voltage exceeds 0.5V (e.g., active channel
V
= 1V, while disabled channel V = GND), so the mux
IN
OUT
FN6337.2
March 13, 2008
13
ISL28148, ISL28248, ISL28448
implementation is best suited for small signal applications. If
large signals are required, use series IN+ resistors, or large
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input
impedance and low offset voltage, care should be taken in
the circuit board layout. The PC board surface must remain
clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
will reduce surface moisture and provide a humidity barrier,
reducing parasitic resistance on the board. When input
leakage current is a concern, the use of guard rings around
the amplifier inputs will further reduce leakage currents.
Figure 46 shows a guard ring example for a unity gain
amplifier that uses the low impedance amplifier output at the
same voltage as the high impedance input to eliminate
surface leakage. The guard ring does not need to be a
specific width, but it should form a continuous loop around
both inputs. For further reduction of leakage currents,
components can be mounted to the PC board using Teflon
standoff insulators.
value R , to keep the feed through current low enough to
F
minimize the impact on the active channel. See “Limitations
of the Differential Input Protection” on page 14 for more
details.The EN pin also has an internal pull-down. If left
open, the EN pin will pull to the negative rail and the device
will be enabled by default. When not used, the EN pin should
either be left floating or connected directly to the V- pin.
Limitations of the Differential Input Protection
If the input differential voltage is expected to exceed 0.5V, an
external current limiting resistor must be used to ensure the
input current never exceeds 5mA. For non-inverting unity gain
applications the current limiting can be via a series IN+ resistor,
or via a feedback resistor of appropriate value. For other gain
configurations, the series IN+ resistor is the best choice, unless
the feedback (R ) and gain setting (R ) resistors are both
F
G
sufficiently large to limit the input current to 5mA.
.
Large differential input voltages can arise from several
sources:
V+
HIGH IMPEDANCE INPUT
IN
• During open loop (comparator) operation. Used this way,
the IN+ and IN- voltages don’t track, so differentials arise.
• When the amplifier is disabled but an input signal is still
present. An R or R to GND keeps the IN- at GND, while
L
G
the varying IN+ signal creates a differential voltage. Mux
Amp applications are similar, except that the active
FIGURE 46. GUARD RING EXAMPLE FOR UNITY GAIN
AMPLIFIER
channel V
determines the voltage on the IN- terminal.
OUT
Current Limiting
• When the slew rate of the input pulse is considerably
faster than the op amp’s slew rate. If the V can’t keep
These devices have no internal current-limiting circuitry. If
the output is shorted, it is possible to exceed the Absolute
Maximum Rating for output current or power dissipation,
potentially resulting in the destruction of the device.
OUT
up with the IN+ signal, a differential voltage results, and
visible distortion occurs on the input and output signals. To
avoid this issue, keep the input slew rate below 4.8V/μs, or
use appropriate current limiting resistors.
Power Dissipation
Large (>2V) differential input voltages can also cause an
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power-supply
conditions. It is therefore important to calculate the
increase in disabled I
.
CC
Using Only One Channel
maximum junction temperature (T
) for all applications
JMAX
If the application does not use all channels, then the user
must configure the unused channel(s) to prevent them from
oscillating. The unused channel(s) will oscillate if the input
and output pins are floating. This will result in higher than
expected supply currents and possible noise injection into
the channel being used. The proper way to prevent this
oscillation is to short the output to the negative input and
ground the positive input (as shown in Figure 45).
to determine if power supply voltages, load conditions, or
package type need to be modified to remain in the safe
operating area. These parameters are related in Equation 1:
T
= T
+ (θ xPD
)
MAXTOTAL
(EQ. 1)
JMAX
MAX
JA
where:
• P
is the sum of the maximum power
DMAXTOTAL
dissipation of each amplifier in the package (PD
)
MAX
-
• PD
MAX
for each amplifier can be calculated as shown in
Equation 2:
+
V
OUTMAX
R
L
----------------------------
PD
= 2*V × I
+ (V - V ) ×
OUTMAX
MAX
S
SMAX
S
FIGURE 45. PREVENTING OSCILLATIONS IN UNUSED
CHANNELS
(EQ. 2)
FN6337.2
March 13, 2008
14
ISL28148, ISL28248, ISL28448
where:
• T
= Maximum ambient temperature
MAX
• θ = Thermal resistance of the package
JA
• PD
= Maximum power dissipation of 1 amplifier
MAX
• V = Supply voltage (Magnitude of V and V )
S
+
-
• I
= Maximum supply current of 1 amplifier
MAX
• V
OUTMAX
= Maximum output voltage swing of the
application
• R = Load resistance
L
FN6337.2
March 13, 2008
15
ISL28148, ISL28248, ISL28448
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
MILLIMETERS
SOT23-5
6
4
N
SYMBOL
SOT23-6
1.45
0.10
1.14
0.40
0.14
2.90
2.80
1.60
0.95
1.90
0.45
0.60
6
TOLERANCE
MAX
A
A1
A2
b
1.45
0.10
1.14
0.40
0.14
2.90
2.80
1.60
0.95
1.90
0.45
0.60
5
±0.05
E1
E
±0.15
2
3
±0.05
0.15
2X
C
D
c
±0.06
1
2
3
0.20
2X
C
D
Basic
5
e
E
Basic
E1
e
Basic
0.20
C
A-B
D
M
B
b
NX
Basic
e1
L
Basic
±0.10
L1
N
Reference
Reference
Rev. F 2/07
0.15
2X
C
A-B
1
3
D
NOTES:
C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
A2
SEATING
PLANE
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
A1
0.10
NX
C
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
6. SOT23-5 version has no center lead (shown as a dashed line).
(L1)
H
A
GAUGE
PLANE
0.25
c
+3°
-0°
L
0°
FN6337.2
March 13, 2008
16
ISL28148, ISL28248, ISL28448
Wafer Level Chip Scale Package (WLCSP)
W3x2.6C
3x2 ARRAY 6 BALL WAFER LEVEL CHIP SCALE PACKAGE
E
SYMBOL
MILLIMETERS
0.51 Min, 0.55 Max
0.225 ±0.015
0.305 ±0.013
Φ0.323 ±0.025
0.955 ±0.020
0.50 BASIC
A
A
A
1
D
2
PIN 1 ID
b
D
TOP VIEW
D
1
E
1.455 ±0.020
1.00 BASIC
E
1
e
0.50 BASIC
SD
SE
0.25 BASIC
A
2
A
0.00 BASIC
A
1
Rev. 3 03/08
b
NOTES:
1. All dimensions are in millimeters.
SIDE VIEW
E1
e
SE
2
1
SD
D
1
b
C
B
A
BOTTOM VIEW
FN6337.2
March 13, 2008
17
ISL28148, ISL28248, ISL28448
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN6337.2
March 13, 2008
18
ISL28148, ISL28248, ISL28448
Mini SO Package Family (MSOP)
MDP0043
0.25 M C A B
A
MINI SO PACKAGE FAMILY
D
(N/2)+1
MILLIMETERS
N
SYMBOL
MSOP8
1.10
0.10
0.86
0.33
0.18
3.00
4.90
3.00
0.65
0.55
0.95
8
MSOP10
1.10
0.10
0.86
0.23
0.18
3.00
4.90
3.00
0.50
0.55
0.95
10
TOLERANCE
Max.
NOTES
A
A1
A2
b
-
±0.05
-
E
E1
PIN #1
I.D.
±0.09
-
+0.07/-0.08
±0.05
-
c
-
D
±0.10
1, 3
1
B
(N/2)
E
±0.15
-
E1
e
±0.10
2, 3
Basic
-
e
H
C
L
±0.15
-
SEATING
PLANE
L1
N
Basic
-
Reference
-
M
C A B
b
0.08
0.10 C
Rev. D 2/07
N LEADS
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
0.25
L
DETAIL X
A1
3° ±3°
FN6337.2
March 13, 2008
19
ISL28148, ISL28248, ISL28448
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
0.25 M C A B
D
A
(N/2)+1
MILLIMETERS
N
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
PIN #1 I.D.
E
E1
±0.05
+0.05/-0.06
+0.05/-0.06
±0.10
0.20 C B A
2X
1
(N/2)
c
N/2 LEAD TIPS
B
D
TOP VIEW
E
Basic
E1
e
±0.10
Basic
0.05
H
e
L
±0.15
C
L1
Reference
Rev. F 2/07
SEATING
PLANE
NOTES:
0.10 M C A B
b
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.10 C
N LEADS
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6337.2
March 13, 2008
20
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