ISL28248FUZ-T7 [RENESAS]
4.5MHz, Single and Dual Precision Rail-to-Rail Input-Output Op Amps with Very Low Input Bias Current;
| 型号： | ISL28248FUZ-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4.5MHz, Single and Dual Precision Rail-to-Rail Input-Output Op Amps with Very Low Input Bias Current 放大器 光电二极管 |
| 文件： | 总17页 (文件大小：1177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL28148, ISL28248
4.5MHz, Single and Dual Precision Rail-to-Rail Input-Output Op Amps with Very
Low Input Bias Current
FN6337
Rev 5.00
January 22, 2016
The ISL28148, ISL28248 are 4.5MHz low-power single and
Features
dual operational amplifiers. The parts are optimized for single
supply operation from 2.4V to 5.5V, allowing operation from
one lithium cell or two Ni-Cd batteries.
• 4.5MHz gain bandwidth product
• 900µA supply current (per amplifier)
• 1.8mV maximum offset voltage (ISL28248)
• 1pA typical input bias current
The single and dual feature an Input Range Enhancement
Circuit (IREC), which enables them to maintain CMRR
performance for input voltages greater than the positive
supply. The input signal is capable of swinging 0.25V above the
positive supply and to 100mV below the negative supply with
only a slight degradation of the CMRR performance. The
output operation is rail-to-rail.
• Down to 2.4V single supply operation
• Rail-to-rail input and output
• Enable pin (ISL28148 SOT-23 package only)
• -40°C to +125°C operation
The parts draw minimal supply current (900µA per amplifier)
while meeting excellent DC accuracy, AC performance, noise
and output drive specifications. The ISL28148 features an
enable pin that can be used to turn the device off and reduce
the supply current to a maximum of 16µA. Operation is
guaranteed across the -40°C to +125°C temperature range.
• Pb-free (RoHS compliant)
Applications
• Low-end audio
• 4mA to 20mA current loops
• Medical devices
• Sensor amplifiers
• ADC buffers
• DAC output amplifiers
Ordering Information
PART NUMBER
TAPE AND REEL QUANTITY
PACKAGE
PKG.
(Notes 2, 3)
ISL28148FHZ-T7 (Notes 1, 4)
ISL28148FHZ-T7A (Notes 1, 4)
ISL28248FBZ
PART MARKING
GABT
(UNITS)
(RoHS Compliant)
DWG. #
3k
6 Ld SOT-23
P6.064A
GABT
250
6 Ld SOT-23
8 Ld SOIC
P6.064A
M8.15E
28248 FBZ
28248 FBZ
8248Z
ISL28248FBZ-T7 (Note 1)
ISL28248FUZ
1k
8 Ld SOIC
M8.15E
8 Ld MSOP
8 Ld MSOP
M8.118A
M8.118A
ISL28248FUZ-T7 (Note 1)
ISL28148EVAL1Z
8248Z
1.5k
Evaluation Board
Evaluation Board
Evaluation Board
ISL28248MSOPEVAL1Z
ISL28248SOICEVAL1Z
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL28148, ISL28248. For more information on MSL, please see tech
brief TB363.
4. The part marking is located on the bottom of the part.
FN6337 Rev 5.00
January 22, 2016
Page 1 of 17
ISL28148, ISL28248
Pin Configurations
ISL28148
(6 LD SOT-23)
TOP VIEW
ISL28248
(8 LD SOIC)
TOP VIEW
ISL28248
(8 LD MSOP)
TOP VIEW
OUT
V-
1
2
3
6
5
4
V+
EN
IN-
OUT_A
IN-_A
IN+_A
V-
1
2
3
4
8
7
6
5
V+
OUT_A
IN-_A
IN+_A
V-
1
2
3
4
8
7
6
5
V+
OUT_B
IN-_B
IN+_B
OUT_B
IN-_B
IN+_B
-
+
- +
+
-
IN+
+
-
+ -
Pin Descriptions
ISL28248
(8 Ld SOIC)
(8 Ld MSOP)
ISL28148
(6 Ld SOT-23)
PIN NAME
FUNCTION
EQUIVALENT CIRCUIT
4
IN-
inverting input
2 (A)
6 (B)
IN-_A
IN-_B
V+
IN-
IN+
V-
Circuit 1
3
2
IN+
IN+_A
IN+_B
Noninverting input
Negative supply
(See circuit 1)
3 (A)
5 (B)
4
V-
V+
CAPACITIVELY
COUPLED
ESD CLAMP
V-
Circuit 2
V+
1
OUT
Output
1 (A)
7 (B)
OUT_A
OUT_B
OUT
V-
Circuit 3
6
5
8
V+
EN
Positive supply
Chip enable
(See circuit 2)
V+
EN
V-
Circuit 4
FN6337 Rev 5.00
January 22, 2016
Page 2 of 17
ISL28148, ISL28248
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1200V
Thermal Resistance (Typical, Note 5)
(°C/W)
JA
6 Ld SOT-23 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Ld MSOP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
165
120
160
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
5. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications (V ±5V) V = 0V, V = 2.5V, R = Open, TA = +25°C unless otherwise specified. Boldface limits apply
-
CM
L
S
across the operating temperature range, -40°C to +125°C. Temperature data established by characterization.
MIN
MAX
PARAMETER
DESCRIPTION
Input Offset Voltage
TEST CONDITIONS
(Note 6)
TYP
0
(Note 6)
UNIT
mV
V
ISL28148
ISL28248
-2.3
-2.8
2.3
2.8
OS
0
0.03
±5
-1.8
-2.8
1.8
2.8
mV
µV/°C
pA
V
Input Offset Voltage vs Temperature
Input Offset Current
OS
---------------
T
I
-35
35
OS
T
= -40°C to +85°C
-80
80
A
I
Input Bias Current
-30
±1
30
pA
B
T
= -40°C to +85°C
-80
80
A
CMIR
Common-Mode Voltage Range
Common-Mode Rejection Ratio
Guaranteed by CMRR
0
5
V
CMRR
V
V
V
V
= 0V to 5V
75
70
98
98
dB
CM
PSRR
Power Supply Rejection Ratio
Large Signal Voltage Gain
= 2.4V to 5.5V
80
75
dB
+
O
O
A
= 0.5V to 4.5V, R = 100kΩto V
CM
200
150
580
V/mV
VOL
L
= 0.5V to 4.5V, R = 1kΩto V
CM
50
3
V/mV
mV
L
V
Maximum Output Voltage Swing
Output low, R = 100kΩto V
CM
6
OUT
L
8
Output low, R = 1kΩto V
CM
50
4.998
4.95
0.9
70
110
mV
V
L
Output high, R = 100kΩto V
CM
4.994
4.99
L
Output high, R = 1kΩto V
4.93
4.89
V
L
CM
I
I
Quiescent Supply Current, Enabled
Quiescent Supply Current, Disabled
Short-Circuit Output Source Current
Short-Circuit Output Sink Current
Per Amplifier
1.25
1.4
mA
µA
mA
mA
S,ON
ISL28148 SOT-23 package only
10
14
16
S,OFF
I +
R
R
= 10Ωto V
= 10Ωto V
48
45
75
O
L
CM
I -
-68
-48
O
L
CM
-45
V
V
Supply Operating Range
EN Pin High Level
V
to V
-
2.4
2
5.5
V
V
SUPPLY
+
ISL28148 SOT-23 package only
ENH
FN6337 Rev 5.00
January 22, 2016
Page 3 of 17
ISL28148, ISL28248
Electrical Specifications (V ±5V) V = 0V, V = 2.5V, R = Open, TA = +25°C unless otherwise specified. Boldface limits apply
-
CM
L
S
across the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
EN Pin Low Level
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
V
V
ISL28148 SOT-23 package only
0.8
ENL
I
EN Pin Input High Current
V
= V , ISL28148 SOT-23 package only
1
1.5
µA
ENH
EN
+
1.6
I
EN Pin Input Low Current
V
= V , ISL28148 SOT-23 package only
12
25
nA
ENL
EN
-
30
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
A
R
= 100, R = 100kΩR = 1kΩ
4.5
13
MHz
MHz
V
L
f
g
= 10kΩto V
CM
Unity Gain
Bandwidth
-3dB Bandwidth
A
= 1, R = 0ΩV
OUT
= 10mV
,
P-P
V
f
R
= 10kΩto V
L
CM
e
Input Noise Voltage Peak-to-Peak
Input Noise Voltage Density
f = 0.1Hz to 10Hz
2
28
µV
PP
N
f
f
= 1kHz
= 1kHz
nV/Hz
pA/Hz
dB
O
i
Input Noise Current Density
0.016
85
N
O
CMRR at 60Hz
Input Common-Mode Rejection Ratio
V
= 1V , R = 10kΩto V
P-P CM
CM
L
PSRR- At
120Hz
Power Supply Rejection Ratio (V )
V , V = ±1.2V and ±2.5V,
-82
dB
-
+
-
V
= 1V , R = 10kΩto V
P-P
SOURCE
L
CM
PSRR+ At
120Hz
Power Supply Rejection Ratio (V )
V , V = ±1.2V and ±2.5V
-100
dB
+
+
-
V
= 1V , R = 10kΩto V
P-P
SOURCE
L
CM
TRANSIENT RESPONSE
SR Slew Rate
t , t , Large Rise Time, 10% to 90%, V
±4
V/µs
ns
A = +2, V
OUT
= 3V , R = R = 10kΩ
P-P
530
r
f
OUT
V
g
f
Signal
R
= 10kΩto V
L
CM
Fall Time, 90% to 10%, V
A = +2, V
OUT
= 3V , R = R = 10kΩ
P-P
530
50
50
5
ns
ns
ns
µs
µs
OUT
V
g
f
R
= 10kΩto V
L
CM
t , t , Small
Rise Time, 10% to 90%, V
A = +2, V
OUT
= 10mV
,
P-P
r
f
OUT
V
Signal
R
= R = R = 10kΩto V
g
f
L
CM
Fall Time, 90% to 10%, V
A = +2, V
= 10mV
,
OUT
V
OUT
P-P
R
= R = R = 10kΩto V
g
f L CM
t
Enable to Output Turn-On Delay Time, 10%
= 5V to 0V, A = +2,
EN V
EN
EN to 10% V , (ISL28148)
R
= R = R = 1kΩto V
OUT
g
f
L
CM
Enable to Output Turn-Off Delay Time, 10%
V
= 0V to 5V, A = +2,
0.2
EN
V
EN to 10% V , (ISL28148)
R
= R = R = 1kΩ to V
OUT
g
f
L
CM
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN6337 Rev 5.00
January 22, 2016
Page 4 of 17
ISL28148, ISL28248
Typical Performance Curves
V
= 5V, V = 0V, V = 2.5V, R = Open.
+
-
CM
L
15
1
0
10
V
= 100mV
= 50mV
= 10mV
OUT
-1
-2
-3
-4
-5
-6
-7
-8
-9
R = R = 100k
f
g
V
R = R = 10k
OUT
OUT
f
g
5
0
V
V
= 1V
OUT
V
R
= 5V
= 1k
+
-5
L
L
R = R = 1k
V
R
= 5V
= 1k
f
g
+
L
L
C
= 16.3pF
= +2
-10
A
V
C
= 16.3pF
= +1
V
= 10mV
OUT
P-P
10k
A
V
-15
100
1k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES
R /R
FIGURE 2. GAIN vs FREQUENCY vs V
R = 1k
L
OUT,
f
g
1
0
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-1
-2
-3
-4
-5
-6
-7
-8
-9
V
= 100mV
= 50mV
OUT
V
= 100mV
= 50mV
= 10mV
OUT
OUT
V
V
V
OUT
OUT
= 10mV
V
OUT
= 1V
V
V
= 1V
OUT
OUT
V
= 5V
= 10k
V
= 5V
+
L
L
+
R
C
A
R
C
A
= 100k
L
L
= 16.3pF
= +1
= 16.3pF
= +1
V
V
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 4. GAIN vs FREQUENCY vs V
, R = 100k
OUT
FIGURE 3. GAIN vs FREQUENCY vs V
, R = 10k
L
L
OUT
70
60
50
40
30
20
10
0
1
0
A
= 1, R = INF, R = 0
g f
g f
= 101, R = 1k, R = 100k
g f
R
= 1k
V
L
A
= 1001
= 101
V
A
= 10, R = 1k, R = 9.09k
V
A
V
-1
-2
-3
-4
-5
-6
-7
-8
-9
R
= 10k
A
= 1001, R = 1k, R = 1M
L
V
g f
A
V
R
= 100k
L
V
= 5V
+
L
L
C
= 16.3pF
= 10k
A
= 10
V
R
V
= 10mV
OUT
P-P
V
V
= 5V
+
= 10mV
= 16.3pF
= +1
A
= 1
OUT
P-P
V
C
L
A
V
-10
100
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 6. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
FIGURE 5. GAIN vs FREQUENCY vs R
L
FN6337 Rev 5.00
January 22, 2016
Page 5 of 17
ISL28148, ISL28248
Typical Performance Curves
V
= 5V, V = 0V, V = 2.5V, R = Open. (Continued)
+
-
CM
L
1
8
7
6
C
C
= 51.7pF
= 43.7pF
= 37.7pF
L
L
L
0
V
= 5V
+
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-1
-2
-3
-4
-5
-6
-7
-8
-9
C
V
= 2.4V
+
C
= 26.7pF
= 16.7pF
= 4.7pF
L
R
C
A
= 10k
L
L
V
R
= 5V
= 1k
= +1
+
C
L
= 16.3pF
= +1
L
C
L
A
V
V
V
= 10mV
V
= 10mV
OUT
P-P
OUT
P-P
10k
100k
1M
FREQUENCY (Hz)
10M
100M
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 8. GAIN vs FREQUENCY vs C
FIGURE 7. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
L
10
0
20
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
PSRR-
PSRR+
-20
-40
-60
-80
-100
-120
V
= 2.4V, 5V
= 1k
V , V = ±1.2V
+
L
L
+
-
R
C
A
R
= 1k
L
L
= 16.3pF
= +1
C
A
= 16.3pF
= +1
V
V
V
= 1V
V
= 1V
CM
P-P
CM
P-P
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. CMRR vs FREQUENCY; V = 2.4V AND 5V
+
FIGURE 10. PSRR vs FREQUENCY, V , V = ±1.2V
+
-
20
0
1000
100
10
V
= 5V
+
R = 1k R = 1k
f
g
A
= +2
V
PSRR-
PSRR+
-20
-40
-60
-80
-100
-120
V , V = ±2.5V
+
-
R
= 1k
L
L
C
A
= 16.3pF
= +1
V
V
= 1V
P-P
CM
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 12. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY
FIGURE 11. PSRR vs FREQUENCY V , V = ±2.5V
+
-
FN6337 Rev 5.00
January 22, 2016
Page 6 of 17
ISL28148, ISL28248
Typical Performance Curves
V
= 5V, V = 0V, V = 2.5V, R = Open. (Continued)
+
-
CM
L
0
0.1
V
= 5V
+
R = 1k R = 1k
f
g
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
A
= +2
V
R
= 10k
A = 10k
V
V
C
= 5V
= 16.3pF
= 10
L
+
L
R
R = 100k
f
g
0.01
1
10
100
1k
10k
100k
0
1
2
3
4
5
6
7
8
9
10
TIME (s)
FREQUENCY (Hz)
FIGURE 14. INPUT VOLTAGE NOISE 0.1Hz TO 10Hz
FIGURE 13. INPUT CURRENT NOISE DENSITY vs FREQUENCY
0.025
0.020
0.015
0.010
2.0
1.5
1.0
0.5
0
V , V = ±2.5V
V , V = ±2.5V
+
-
+
-
-0.5
-1.0
-1.5
-2.0
R
= 1k
R
= 1k
L
L
L
L
g
C
= 16.3pF
C
R
A
= 16.3pF
R = R = 10k
= R = 10k
g
f
f
A
OUT
= 2
= 2
V
V
OUT
V
= 10mV
V
= 3V
P-P
6
P-P
0
1
2
3
4
5
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
TIME (µs)
FIGURE 15. LARGE SIGNAL STEP RESPONSE
FIGURE 16. SMALL SIGNAL STEP RESPONSE
1.2
1.0
0.8
0.6
0.4
0.2
0
3.5
V
OUT
V
EN
3.0
2.5
2.0
1.5
1.0
0.5
0
V
R
= 5V
= R = 10k
+
g
L
f
C
= 16.3pF
= +2
A
V
V
= 1V
P-P
OUT
R
= 10k
L
-0.2
90 100
-0.5
0
10
20
30
40
50
60
70
80
TIME (µs)
FIGURE 17. ISL28148 ENABLE TO OUTPUT RESPONSE
FN6337 Rev 5.00
January 22, 2016
Page 7 of 17
ISL28148, ISL28248
Typical Performance Curves
V
= 5V, V = 0V, V = 2.5V, R = Open. (Continued)
CM
+
-
L
100
80
800
V
= 5V
= OPEN
V
R
= 5V
= OPEN
+
L
f
+
L
600
400
200
0
R
R
A
60
= 100k, R = 100
g
= +1k
R = 100k, R = 100
f
g
40
A
= +1k
V
V
20
0
-20
-40
-60
-80
-100
-200
-400
-600
-800
-1
0
1
2
3
4
5
6
-1
0
1
2
3
4
5
6
V
(V)
V
(V)
CM
CM
FIGURE 18. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT
VOLTAGE
FIGURE 19. INPUT BIAS CURRENT vs COMMON-MODE INPUT
VOLTAGE
1.2
10.5
MAX
9.5
1.1
MAX
8.5
1.0
MEDIAN
7.5
MEDIAN
0.9
6.5
0.8
MIN
MIN
5.5
0.7
0.6
4.5
3.5
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 20. SUPPLY CURRENT ENABLED vs TEMPERATURE V ,
FIGURE 21. SUPPLY CURRENT DISABLED vs TEMPERATURE V ,
+
+
V = ±2.5V
V = ±2.5V
-
-
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
MAX
MAX
MEDIAN
MEDIAN
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
MIN
MIN
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 22. V vs TEMPERATURE V = 0V, V , V = ±2.75V
FIGURE 23. V vs TEMPERATURE V = 0V, V , V = ±2.5V
OS IN
OS
IN
+
-
+
-
FN6337 Rev 5.00
January 22, 2016
Page 8 of 17
ISL28148, ISL28248
Typical Performance Curves
V
= 5V, V = 0V, V = 2.5V, R = Open. (Continued)
CM
+
-
L
2.0
300
250
200
150
100
50
MAX
1.5
1.0
0.5
MAX
MEDIAN
MEDIAN
0
-0.5
-1.0
MIN
MIN
0
-1.5
-2.0
-50
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 25.
I
- vs TEMPERATURE V , V = ±2.5V
BIAS + -
FIGURE 24.
V
vs TEMPERATURE V = 0V, V , V = ±1.2V
OS
IN
+
-
250
200
150
100
50
10
0
MAX
MEDIAN
MIN
-10
-20
-30
-40
-50
-60
-70
MAX
MEDIAN
MIN
0
-50
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 27. I vs TEMPERATURE V , V = ±2.5V
FIGURE 26. I
- vs TEMPERATURE V , V = ±1.2V
+ -
OS
+
-
BIAS
20
10
1750
1550
1350
1150
950
0
MAX
MEDIAN
-10
-20
-30
-40
-50
-60
MAX
MEDIAN
MIN
MIN
750
550
350
150
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 29. A
vs TEMPERATURE R = 100k, V , V = ±2.5V, V = -
L + - O
FIGURE 28. I vs TEMPERATURE V , V = ±1.2V
OS
VOL
+
-
2V TO +2V
FN6337 Rev 5.00
January 22, 2016
Page 9 of 17
ISL28148, ISL28248
Typical Performance Curves
V
= 5V, V = 0V, V = 2.5V, R = Open. (Continued)
CM
+
-
L
80
140
130
120
110
100
90
MAX
70
60
MAX
MEDIAN
50
40
MEDIAN
MIN
30
80
MIN
20
-40
70
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 31. CMRR vs TEMPERATURE V
±2.5V
= -2.5V TO +2.5V, V V =
FIGURE 30. A
vs TEMPERATURE R = 1k, V , V = ±2.5V, V = -2V
CM
+,
-
VOL
L
+
-
O
TO +2V
140
130
120
110
100
90
4.970
4.965
4.960
4.955
MAX
MAX
MEDIAN
4.950
MEDIAN
MIN
MIN
4.945
80
70
-40
4.940
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 32. PSRR vs TEMPERATURE V V = ±1.2V TO ±2.75V
FIGURE 33. V
OUT
HIGH vs TEMPERATURE R = 1k,
L
+,
-
V , V = ±2.5V
+
-
75
70
65
60
55
50
45
40
4.9994
4.9992
4.9990
4.9988
4.9986
4.9984
4.9982
MAX
MAX
MEDIAN
MEDIAN
MIN
MIN
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 35. V
OUT
LOW vs TEMPERATURE R = 1k,
L
FIGURE 34. V
OUT
HIGH vs TEMPERATURE R = 100k,
L
V , V = ±2.5V
V , V = ±2.5V
+
-
+
-
FN6337 Rev 5.00
January 22, 2016
Page 10 of 17
ISL28148, ISL28248
Typical Performance Curves
V
= 5V, V = 0V, V = 2.5V, R = Open. (Continued)
CM
+
-
L
3.3
3.1
2.9
95
90
85
80
75
70
65
60
MAX
MAX
2.7
2.5
MEDIAN
2.3
MEDIAN
2.1
1.9
MIN
MIN
1.7
1.5
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 37. + OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE
= 2.55V, R = 10, V , V = ±2.5V
FIGURE 36. V
LOW vs TEMPERATURE R = 100k,
L
OUT
V
V , V = ±2.5V
IN
L
+
-
+
-
-50
-55
-60
-65
-70
-75
-80
-85
MAX
MIN
MEDIAN
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 38. - OUTPUT SHORT CIRCUIT CURRENT vs TEMPERATURE V = -2.55V, R = 10, V , V = ±2.5V
IN
L
+
-
FN6337 Rev 5.00
January 22, 2016
Page 11 of 17
ISL28148, ISL28248
Applications Information
-
Introduction
V
R
OUT
IN
V
The ISL28148, ISL28248 are single and dual channel CMOS
rail-to-rail input, output (RRIO) micropower precision operational
amplifiers. The parts are designed to operate from a single
supply (2.4V to 5.5V) or a dual supply (±1.2V to ±2.75V). The
parts have an input common-mode range that extends 0.25V
above the positive rail and 100mV below the negative supply rail.
The output can swing within about 3mV of the supply rails with a
100kΩ load.
R
IN
+
L
FIGURE 39. INPUT CURRENT LIMITING
Enable/Disable Feature
The ISL28148 offers an EN pin that disables the device when
pulled up to at least 2.0V. In the disabled state (output in a high
impedance state), the part consumes typically 10µA at room
temperature. By disabling the part, multiple ISL28148 parts can
be connected together as a MUX. In this configuration, the
outputs are tied together in parallel and a channel can be
selected by the EN pin. The loading effects of the feedback
resistors of the disabled amplifier must be considered when
multiple amplifier outputs are connected together. Note that
feed-through from the IN+ to IN- pins occurs on any Mux Amp
disabled channel where the input differential voltage exceeds
Rail-to-Rail Input
Many rail-to-rail input stages use two differential input pairs, a
long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties
have to be paid for this circuit topology. As the input signal moves
from one supply rail to another, the operational amplifier
switches from one input pair to the other causing drastic changes
in input offset voltage and an undesired change in magnitude
and polarity of input offset current.
0.5V (e.g., active channel V
= 1V, while disabled channel
= GND), so the Mux implementation is best suited for small
OUT
The parts achieve input rail-to-rail operation without sacrificing
important precision specifications and degrading distortion
performance. The devices’ input offset voltage exhibits a smooth
behavior throughout the entire common-mode input range. The
input bias current vs the common-mode voltage range gives us
an undistorted behavior from typically 100mV below the negative
V
IN
signal applications. If large signals are required, use series IN+
resistors, or large value R , to keep the feed-through current low
f
enough to minimize the impact on the active channel. See
“Limitations of the Differential Input Protection” on page 12 for
more details.The EN pin also has an internal pull-down. If left
open, the EN pin will pull to the negative rail and the device will
be enabled by default. When not used, the EN pin should either
be left floating or connected directly to the V- pin.
rail and 0.25V higher than the V rail.
+
Rail-to-Rail Output
A pair of complementary MOS devices are used to achieve the
rail-to-rail output swing. The NMOS sinks current to swing the
output in the negative direction. The PMOS sources current to
swing the output in the positive direction. The devices’ with a
100kΩ load will swing to within 3mV of the positive supply rail and
within 3mV of the negative supply rail.
Limitations of the Differential Input
Protection
If the input differential voltage is expected to exceed 0.5V, an
external current limiting resistor must be used to ensure the input
current never exceeds 5mA. For noninverting unity gain applications
the current limiting can be via a series IN+ resistor, or via a feedback
resistor of appropriate value. For other gain configurations, the
Results of Overdriving the Output
Caution should be used when overdriving the output for long
periods of time. Overdriving the output can occur in two ways:
series IN+ resistor is the best choice, unless the feedback (R ) and
f
gain setting (R ) resistors are both sufficiently large to limit the input
g
1. The input voltage times the gain of the amplifier exceeds the
supply voltage by a large value or
current to 5mA.
Large differential input voltages can arise from several sources:
2. The output current required is higher than the output stage can
deliver. These conditions can result in a shift in the Input Offset
• During open loop (comparator) operation. Used this way, the
IN+ and IN- voltages don’t track, so differentials arise.
Voltage (V ) as much as 1µV/hr. of exposure under these
OS
conditions.
• When the amplifier is disabled but an input signal is still
present. An R or R to GND keeps the IN- at GND, while the
varying IN+ signal creates a differential voltage. Mux Amp
L
g
IN+ and IN- Input Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. They also contain
back-to-back diodes across the input terminals (see “Pin
Descriptions” table - Circuit 1 on page 2). For applications where
the input differential voltage is expected to exceed 0.5V, an
external series resistor must be used to ensure the input currents
never exceed 5mA (Figure 39).
applications are similar, except that the active channel V
determines the voltage on the IN- terminal.
OUT
• When the slew rate of the input pulse is considerably faster
than the op amp’s slew rate. If the V cannot keep up with
OUT
the IN+ signal, a differential voltage results and visible
distortion occurs on the input and output signals. To avoid this
issue, keep the input slew rate below 4.8V/µs, or use
appropriate current limiting resistors.
Large (>2V) differential input voltages can also cause an
increase in disabled I
.
CC
FN6337 Rev 5.00
January 22, 2016
Page 12 of 17
ISL28148, ISL28248
Using Only One Channel
Power Dissipation
If the application does not use all channels, then the user must
configure the unused channel(s) to prevent them from
oscillating. The unused channel(s) will oscillate if the input and
output pins are floating. This will result in higher than expected
supply currents and possible noise injection into the channel
being used. The proper way to prevent this oscillation is to short
the output to the negative input and ground the positive input (as
shown in Figure 40).
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power-supply conditions. It
is therefore important to calculate the maximum junction
temperature (T
) for all applications to determine if power
JMAX
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related in Equation 1:
T
= T
+ xPD
MAXTOTAL
(EQ. 1)
JMAX
MAX
JA
-
Where:
• P
is the sum of the maximum power dissipation of
+
DMAXTOTAL
each amplifier in the package (PD
)
MAX
FIGURE 40. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
• PD
for each amplifier can be calculated as shown in
Equation 2:
MAX
V
OUTMAX
Proper Layout Maximizes Performance
----------------------------
PD
= 2*V I
+ V - V
OUTMAX
MAX
S
SMAX
S
R
L
(EQ. 2)
To achieve the maximum performance of the high input
impedance and low offset voltage, care should be taken in the
circuit board layout. The PC board surface must remain clean
and free of moisture to avoid leakage currents between adjacent
traces. Surface coating of the circuit board will reduce surface
moisture and provide a humidity barrier, reducing parasitic
resistance on the board. When input leakage current is a
concern, the use of guard rings around the amplifier inputs will
further reduce leakage currents. Figure 41 shows a guard ring
example for a unity gain amplifier that uses the low impedance
amplifier output at the same voltage as the high impedance
input to eliminate surface leakage. The guard ring does not need
to be a specific width, but it should form a continuous loop
around both inputs. For further reduction of leakage currents,
components can be mounted to the PC board using Teflon
standoff insulators.
Where:
• T
MAX
= Maximum ambient temperature
• = Thermal resistance of the package
JA
• PD
MAX
= Maximum power dissipation of 1 amplifier
• V = Supply voltage (Magnitude of V and V )
S
+
-
• I
= Maximum supply current of 1 amplifier
MAX
• V
= Maximum output voltage swing of the application
• R = Load resistance
OUTMAX
L
.
V+
HIGH IMPEDANCE INPUT
IN
FIGURE 41. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER
Current Limiting
These devices have no internal current limiting circuitry. If the
output is shorted, it is possible to exceed the absolute maximum
rating for output current or power dissipation, potentially
resulting in the destruction of the device.
FN6337 Rev 5.00
January 22, 2016
Page 13 of 17
ISL28148, ISL28248
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
FN6337.5
CHANGE
January 22, 2016
-Removed part number ISL28448 throughout the datasheet.
-Updated 3rd bullet under Features section.
-Ordering information table on page 1: Added ISL28248MSOPEVAL1Z, ISL28248SOICEVAL1Z.
-Electrical spec table on page 3, Changed VOS limits for the ISL28148: Min from -1.8, -2 to -2.3, -2.8 and Max
from 1.8, 2 to 2.3, 2.8.
Thermal Information table on page 3, changes are:
6ld SOT-23: from 230C/W, to 165C/W
8ld SOIC: from 125C/W, to 120C/W
8ld MSOP: from 175C/W, to 160C/W
- Added revision history and About Intersil verbiage
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2007-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6337 Rev 5.00
January 22, 2016
Page 14 of 17
ISL28148, ISL28248
Package Outline Drawing
P6.064A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0-3°
0.08-0.20
0.95
D
A
6
5
4
PIN 1
INDEX AREA
2.80
3
1.60
3
5
0.15 C D
2x
(0.60)
1
2
3
0.20
2x
C
SEE DETAIL X
END VIEW
0.40 ±0.05
3
B
0.20 M C A-B
D
TOP VIEW
10° TYP
(2 PLCS)
5
0.15 C A-B
2x
2.90
H
1.14 ±0.15
1.45 MAX
C
GAUGE
PLANE
(0.25)
0.10
C
SEATING PLANE
0.05-0.15
(0.60)
SIDE VIEW
DETAIL "X"
4
0.45±0.1
(1.20)
NOTES:
(2.40)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
3.
4. Foot length is measured at reference to guage plane.
Dimension is exclusive of mold flash, protrusions or gate burrs.
This dimension is measured at Datum “H”.
Package conforms to JEDEC MO-178AA.
5.
6.
(0.95)
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
FN6337 Rev 5.00
January 22, 2016
Page 15 of 17
ISL28148, ISL28248
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN6337 Rev 5.00
January 22, 2016
Page 16 of 17
ISL28148, ISL28248
Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
A
3.0±0.1
8
0.25 CAB
4.9±0.15
DETAIL "X"
0.18 ± 0.05
3.0±0.1
1.10 Max
PIN# 1 ID
B
SIDE VIEW 2
1
2
0.65 BSC
TOP VIEW
0.95 BSC
0.86±0.09
GAUGE
PLANE
H
C
0.25
SEATING PLANE
0.10 ± 0.05
0.33 +0.07/ -0.08
0.08 C AB
3°±3°
0.10 C
0.55 ± 0.15
DETAIL "X"
SIDE VIEW 1
5.80
NOTES:
1. Dimensions are in millimeters.
4.40
3.00
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSE Y14.5m-1994.
3.
Plastic or metal protrusions of 0.15mm max per side are not
included.
0.65
0.40
4. Plastic interlead protrusions of 0.25mm max per side are not
included.
1.40
TYPICAL RECOMMENDED LAND PATTERN
5. Dimensions “D” and “E1” are measured at Datum Plane “H”.
6. This replaces existing drawing # MDP0043 MSOP 8L.
FN6337 Rev 5.00
January 22, 2016
Page 17 of 17
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