ISL2110AR4Z_技术文档

ISL2110, ISL2111

®

Data Sheet

July 11, 2006

FN6295.1

100V, 3A/4A Peak, High Frequency

Half-Bridge Drivers

Features

• Drives N-Channel MOSFET Half-Bridge

• SOIC and DFN Package Options

The ISL2110, ISL2111 are 100V, high frequency, half-bridge

N-channel power MOSFET driver ICs. They are based on

the popular HIP2100, HIP2101 half-bridge drivers, but offer

several performance improvements. Peak output pull-up/

pull-down current has been increased to 3A/4A, which

significantly reduces switching power losses and eliminates

the need for external totem-pole buffers in many

• SOIC and DFN Packages Compliant with 100V Conductor

Spacing Guidelines per IPC-2221

• Pb-Free Plus Anneal Available (RoHS Compliant)

• Bootstrap Supply Max Voltage to 114VDC

• On-Chip 1Ω Bootstrap Diode

applications. Also, the low end of the V

operational supply

DD

range has been extended to 8VDC. The ISL2110 has

additional input hysteresis for superior operation in noisy

environments and the inputs of the ISL2111, like those of the

• Fast Propagation Times for Multi-MHz Circuits

• Drives 1nF Load with Typical Rise/Fall Times of 9ns/7.5ns

• CMOS Compatible Input Thresholds (ISL2110)

• 3.3V/TTL Compatible Input Thresholds (ISL2111)

• Independent Inputs Provide Flexibility

ISL2110, can now safely swing to the V

supply rail.

DD

Ordering Information

PART

NUMBER

(Notes 1, 2) MARKING RANGE (°C)

PART

TEMP.

PACKAGE

(Pb-Free)

PKG.

DWG. #

• No Start-Up Problems

• Outputs Unaffected by Supply Glitches, HS Ringing Below

Ground or HS Slewing at High dv/dt

ISL2110ABZ 2110ABZ

-40 to 125 8 Ld SOIC

M8.15

ISL2110AR4Z 2110AR4Z -40 to 125 12 Ld 4x4 DFN L12.4x4A

ISL2111ABZ 2111ABZ -40 to 125 8 Ld SOIC M8.15

• Low Power Consumption

• Wide Supply Voltage Range (8V to 14V)

• Supply Undervoltage Protection

ISL2111AR4Z 2111AR4Z -40 to 125 12 Ld 4x4 DFN L12.4x4A

NOTES:

• 1.6Ω/1Ω Typical Output Pull-Up/Pull-Down Resistance

1. Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak

reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.

Applications

• Telecom Half-Bridge DC/DC Converters

• Telecom Full-Bridge DC/DC Converters

• Two-Switch Forward Converters

• Active-Clamp Forward Converters

• Class-D Audio Amplifiers

2. Add “-T” suffix for Tape and Reel packing option.

Pinouts

ISL2110, ISL2111 (SOIC)

ISL2110, ISL2111 (DFN)

TOP VIEW

1

2

3

4

8

7

6

5

LO

V

DD

V

1

2

3

4

5

6

12

11

10

9

LO

DD

HB

HO

HS

SS

NC

HB

HO

HS

V

SS

LI

NC

LI

HI

EPAD

8

7

HI

NOTE: EPAD = Exposed PAD.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL2110, ISL2111

Application Block Diagram

+12V

+100V

SECONDARY

CIRCUIT

V

DD

HB

DRIVE

HI

HO

HS

LO

HI

LI

PWM

CONTROLLER

DRIVE

LO

ISL2110

ISL2111

REFERENCE

AND

ISOLATION

V

SS

Functional Block Diagram

HB

HO

V

DD

HI

UNDER

VOLTAGE

LEVEL SHIFT

DRIVER

HS

ISL2111

UNDER

VOLTAGE

LO

ISL2111

DRIVER

LI

V

SS

EPAD (DFN Package Only)

*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For

best thermal performance connect the EPAD to the PCB power ground plane.

FN6295.1

July 11, 2006

2

ISL2110, ISL2111

+48V

+12V

SECONDARY

CIRCUIT

ISL2110

ISL2111

PWM

ISOLATION

FIGURE 1. TWO-SWITCH FORWARD CONVERTER

+48V

SECONDARY

CIRCUIT

+12V

ISL2110

ISL2111

PWM

ISOLATION

FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE-CLAMP

FN6295.1

July 11, 2006

3

ISL2110, ISL2111

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

V

- V

(Notes 3, 4) . . . . . . . . -0.3V to 18V

Thermal Resistance (Typical)

θ

(°C/W)

θ (°C/W)

JC

DD, HB

HS

JA

LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . .-0.3V to V

Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . .-0.3V to V

+ 0.3V

DD

HB

SOIC (Note 5) . . . . . . . . . . . . . . . . . . .

DFN (Note 6) . . . . . . . . . . . . . . . . . . . .

95

40

N/A

3

Voltage on HO (Note 4) . . . . . . . . . . . . . . V

- 0.3V to V

HS

Max Power Dissipation at 25°C in Free Air (SOIC, Note 5) . . . . 1.3W

Max Power Dissipation at 25°C in Free Air (DFN, Note 6) . . . . . 3.1W

Storage Temperature Range . . . . . . . . . . . . . . . . . . .-65°C to 150°C

Junction Temperature Range. . . . . . . . . . . . . . . . . . .-55°C to 150°C

Lead Temperature (Soldering 10s - SOIC Lead Tips Only) . . . 300°C

For recommended soldering conditions see Tech Brief TB389.

Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V

Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118V

Average Current in V

to HB Diode . . . . . . . . . . . . . . . . . . 100mA

DD

Maximum Recommended Operating Conditions

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V

DD

Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V

Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V

Voltage on HB . . V + 7V to V + 14V and V

- 1V to V + 100V

HS HS DD

DD

HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.

NOTES:

3. The ISL2110 and ISL2111 are capable of derated operation at supply voltages exceeding 14V. Figure 22 shows the high-side voltage derating

curve for this mode of operation.

4. All voltages referenced to V unless otherwise specified.

SS

5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details.

JA

6. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.

JA

For θ

the “case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details.

JC,

Electrical Specifications

V

= V

= 12V, V = V

SS

= 0V, No Load on LO or HO, Unless Otherwise Specified

HS

DD

HB

T = -40°C to

J

T

= 25°C

125°C

J

PARAMETERS

SYMBOL

TEST CONDITIONS

MIN

TYP MAX

MIN

MAX UNITS

SUPPLY CURRENTS

V

Quiescent Current

Operating Current

I

ISL2110; LI = HI = 0V

ISL2111; LI = HI = 0V

ISL2110; f = 500kHz

ISL2111; f = 500kHz

LI = HI = 0V

-

0.1

0.3

3.4

3.5

0.1

3.4

0.05

1.2

0.25

0.45

5.0

0.15

5.0

1.5

-

0.3

0.55

5.5

0.2

5.5

10

mA

µA

DD

I

DDO

Total HB Quiescent Current

Total HB Operating Current

I

HB

I

f = 500kHz

HBO

HB to V Current, Quiescent

SS

I

LI = HI = 0V; V

HB

= V

= 114V

HBS

HS

= V = 114V

HS

HB to V Current, Operating

SS

I

f = 500kHz; V

-

mA

HBSO

HB

INPUT PINS

Low Level Input Voltage Threshold

V

ISL2110

ISL2111

ISL2110

ISL2111

ISL2110

3.7

4.4

1.8

6.6

1.8

2.2

210

-

3.5

1.2

-

V

IL

1.4

High Level Input Voltage Threshold

Input Voltage Hysteresis

V

-

7.4

2.2

-

7.6

2.4

-

V

IH

-

V

IH

V

-

V

IHYS

Input Pull-down Resistance

R

-

100

500

kΩ

I

UNDER VOLTAGE PROTECTION

V

Rising Threshold

V

6.1

-

6.6

0.6

7.1

-

5.8

-

7.4

-

V

DD

DDR

DDH

Threshold Hysteresis

FN6295.1

July 11, 2006

4

ISL2110, ISL2111

Electrical Specifications

V

= V

= 12V, V = V

SS

= 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)

HS

DD

HB

T = -40°C to

J

T

= 25°C

125°C

J

PARAMETERS

HB Rising Threshold

SYMBOL

TEST CONDITIONS

MIN

5.5

-

TYP MAX

MIN

5.0

-

MAX UNITS

V

6.1

0.6

6.8

-

7.1

-

V

HBR

HBH

HB Threshold Hysteresis

BOOT STRAP DIODE

Low Current Forward Voltage

High Current Forward Voltage

Dynamic Resistance

V

I

= 100µA

= 100mA

-

0.5

0.7

0.6

0.9

1

-

0.7

1

V

Ω

DL

VDD-HB

V

DH

R

1.5

D

LO GATE DRIVER

Low Level Output Voltage

High Level Output Voltage

Peak Pull-Up Current

V

I

= 100mA

-

0.1

0.16

3

0.18

-

0.25

V

A

OLL

OHL

LO

V

= -100mA, V

OHL

= V

- V

0.23

0.3

DD

LO

I

V

= 0V

-

LO

Peak Pull-Down Current

HO GATE DRIVER

I

= 12V

4

OLL

Low Level Output Voltage

High Level Output Voltage

Peak Pull-Up Current

V

I

= 100mA

-

0.1

0.16

3

0.18

-

0.25

V

A

OLH

OHH

HO

V

= -100mA, V

= V - V

HB

0.23

0.3

OHH

HO

I

V

= 0V

-

HO

Peak Pull-Down Current

I

= 12V

4

OLH

Switching Specifications

V

= V

= 12V, V = V = 0V, No Load on LO or HO, Unless Otherwise Specified

SS HS

DD

HB

T

= -40°C

J

T

= 25°C

to 125°C

J

TEST

PARAMETERS

SYMBOL

CONDITIONS

MIN TYP MAX MIN MAX UNITS

Lower Turn-Off Propagation Delay (LI Falling to LO Falling)

Upper Turn-Off Propagation Delay (HI Falling to HO Falling)

Lower Turn-On Propagation Delay (LI Rising to LO Rising)

Upper Turn-On Propagation Delay (HI Rising to HO Rising)

Delay Matching: Upper Turn-Off to Lower Turn-On

Delay Matching: Lower Turn-Off to Upper Turn-On

Either Output Rise Time (10% to 90%)

t

-

32

39

38

8

50

-

60

16

-

ns

µs

ns

LPHL

t

HPHL

t

-

LPLH

-

HPLH

t

1

-

MON

t

6

-

MOFF

t

C = 1nF

9

-

RC

L

Either Output Fall Time (90% to 10%)

t

C = 1nF

-

7.5

0.3

0.19

-

FC

L

Either Output Rise Time (3V to 9V)

t

C = 0.1µF

-

0.4

0.3

-

0.5

0.4

50

-

R

L

Either Output Fall Time (9V to 3V)

t

C = 0.1µF

-

F

L

Minimum Input Pulse Width that Changes the Output

Bootstrap Diode Turn-On or Turn-Off Time

t

-

PW

t

-

10

-

BS

FN6295.1

July 11, 2006

5

ISL2110, ISL2111

Pin Descriptions

SYMBOL

DESCRIPTION

V

Positive supply to lower gate driver. Bypass this pin to V

.

SS

DD

HB

High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin.

Bootstrap diode is on-chip.

HO

HS

High-side output. Connect to gate of high-side power MOSFET.

High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this

pin.

HI

LI

High-side input.

Low-side input.

V

Chip negative supply, which will generally be ground.

Low-side output. Connect to gate of low-side power MOSFET.

Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.

SS

LO

EPAD

Timing Diagrams

LI

HI

HI,

LI

t

,

t

,

HPLH

HPHL

LPHL

LO

HO

LPLH

t

MOFF

MON

HO,

LO

FIGURE 3. PROPAGATION DELAYS

FIGURE 4. DELAY MATCHING

Typical Performance Curves

10

1

0.1

3

.

1 10

10

100

1 10

10

100

FREQUENCY (kHz)

T = -40C

T = 25C

T = -40C

T = 25C

T = 125C

T = 150C

T = 125C

T = 150C

FIGURE 5. ISL2110 IDD OPERATING CURRENT vs

FREQUENCY

FIGURE 6. ISL2111 IDD OPERATING CURRENT vs

FREQUENCY

FN6295.1

July 11, 2006

6

ISL2110, ISL2111

Typical Performance Curves (Continued)

10

1

10

1

0.1

0.01

0.1

0.01

3

.

1 10

.

1 10

10

100

10

100

FREQUENCY (kHz)

T = -40C

T = 25C

T= 25C

T = 125C

T = 150C

T = 125C

T = 150C

FIGURE 7. IHB OPERATING CURRENT vs FREQUENCY

FIGURE 8. IHBS OPERATING CURRENT vs FREQUENCY

200

150

100

50

300

250

200

150

100

50

0

50

100

150

50

0

50

100

150

TEMPERATURE (C)

VDD = VHB = 8V

VDD = VHB = 12V

VDD = VHB = 14V

VDD = VHB = 8V

VDD = VHB = 12V

VDD = VHB = 14V

FIGURE 9. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE

FIGURE 10. LOW LEVEL OUTPUT VOLTAGE vs

TEMPERATURE

0.7

0.65

0.6

6.7

6.5

6.3

6.1

5.9

5.7

5.5

5.3

0.55

0.5

0.45

0.4

50

0

50

100

150

50

0

50

100

150

TEMPERATURE (C)

VDDR

VHBR

VDDH

VHBH

FIGURE 11. UNDERVOLTAGE LOCKOUT THRESHOLD vs

TEMPERATURE

FIGURE 12. UNDERVOLTAGE LOCKOUT HYSTERESIS vs

TEMPERATURE

FN6295.1

July 11, 2006

7

ISL2110, ISL2111

Typical Performance Curves (Continued)

55

50

45

40

35

30

25

55

50

45

40

35

30

25

50

0

50

100

150

50

0

50

100

150

TEMPERATURE (C)

tLPLH

tLPHL

tHPLH

tHPHL

tLPLH

tLPHL

tHPLH

tHPHL

FIGURE 13. ISL2110 PROPAGATION DELAYS vs

TEMPERATURE

FIGURE 14. ISL2111 PROPAGATION DELAYS vs

TEMPERATURE

8

7.5

7

10

9.5

9

8.5

8

6.5

6

7.5

7

6.5

6

5.5

5

4.5

4

5.5

5

4.5

4

50

0

50

100

150

50

0

50

100

150

TEMPERATURE (C)

tMON

tMOFF

FIGURE 15. ISL2110 DELAY MATCHING vs TEMPERATURE

FIGURE 16. ISL2111 DELAY MATCHING vs TEMPERATURE

3.5

3

4.5

4

3.5

3

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

2

4

6

8

10

12

0

2

4

6

8

10

12

VLO, VHO (V)

FIGURE 17. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE

FIGURE 18. PEAK PULL-DOWN CURRENT vs OUTPUT

VOLTAGE

FN6295.1

July 11, 2006

8

ISL2110, ISL2111

Typical Performance Curves (Continued)

120

110

100

90

80

70

60

50

40

30

20

10

0

320

300

280

260

240

220

200

180

160

140

120

100

80

60

40

20

0

5

10

15

20

0

5

10

15

20

VDD, VHB (V)

IDD

IHB

IDD

IHB

FIGURE 19. ISL2110 QUIESCENT CURRENT vs VOLTAGE

FIGURE 20. ISL2111 QUIESCENT CURRENT vs VOLTAGE

1

120

100

80

60

40

20

0

0.1

0.01

3

.

1 10

4

5

6

.

1 10

.

1 10

.

1 10

0.3

0.4

0.5

0.6

0.7

0.8

12

13

14

15

16

FORWARD VOLTAGE (V)

VHS to VSS VOLTAGE (V)

FIGURE 21. BOOTSTRAP DIODE I-V CHARACTERISTICS

FIGURE 22. VHS VOLTAGE vs VDD VOLTAGE

FN6295.1

July 11, 2006

9

ISL2110, ISL2111

Dual Flat No-Lead Plastic Package (DFN)

Micro Lead Frame Plastic Package (MLFP)

L12.4x4A

12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

2X

SYMBOL

MIN

NOMINAL

0.85

MAX

0.90

0.05

0.70

NOTES

0.15

C

A

A1

A2

A3

b

-

0.00

-

D

A

0.01

-

D/2

0.65

-

D1

0.20 REF

0.23

-

D1/2

0.18

2.65

1.43

0.30

2.95

1.73

5, 8

2X

N

0.15

C B

D

4.00 BSC

3.75 BSC

2.80

-

D1

D2

E

-

E1/2

E/2

9

7, 8

E1

E

B

6

4.00 BSC

3.75 BSC

1.58

-

INDEX

AREA

E1

E2

e

-

7, 8

0.15

C B

1

2

3

2X

0.50 BSC

-

TOP VIEW

0.15

C A

k

0.635

0.30

-

2X

0

4X

L

0.40

0.50

8

A2

A

0.10

0.08

C

//

N

12

2

C

Nd

P

6

3

0.24

-

0.42

0.60

12

-

C

A1

A3

SEATING

PLANE

SIDE VIEW

θ

-

Rev. 0 8/03

7

8

NOTES:

D2

1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

2. N is the number of terminals.

(Nd-1)Xe

REF.

D2/2

3. Nd refer to the number of terminals on D.

1

2 3

6

4. All dimensions are in millimeters. Angles are in degrees.

INDEX

AREA

NX k

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

E2

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

E2/2

7

8

4X P

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

N N-1

e

5

NX b

0.10

M

C A

B

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

BOTTOM VIEW

9. COMPLIANT TO JEDEC MO-229-VGGD-2 ISSUE C except for

the L dimension.

C

L

A1

NX b

5

L

C

TERMINAL TIP

e

FOR EVEN TERMINAL/SIDE

FN6295.1

July 11, 2006

10

ISL2110, ISL2111

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

-B-

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

9

SEATING PLANE

A

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-

-A-

3

h x 45°

D

4

-C-

0.050 BSC

1.27 BSC

-

α

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

8

7

NOTES:

0°

8°

0°

8°

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 6/05

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6295.1

July 11, 2006

11


型号：	ISL2110AR4Z
厂家：	Intersil
描述：	100V, 3A/4A Peak, High Frequency Half-Bridge Drivers 100V ， 3A / 4A峰值，高频半桥驱动器驱动器接口集成电路光电二极管
文件：	总11页 (文件大小：224K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL2110AR4Z [INTERSIL]

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