ISL2111BR4Z [INTERSIL]
100V, 3A/4A Peak, High Frequency Half-Bridge Drivers; 100V ， 3A / 4A峰值，高频半桥驱动器
| 型号： | ISL2111BR4Z |
| 厂家： | 
Intersil |
| 描述： | 100V, 3A/4A Peak, High Frequency Half-Bridge Drivers |
| 文件： | 总13页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL2110, ISL2111
Data Sheet
March 8, 2012
FN6295.6
100V, 3A/4A Peak, High Frequency
Half-Bridge Drivers
Features
• Drives N-Channel MOSFET Half-Bridge
• SOIC, DFN and TDFN Package Options
The ISL2110, ISL2111 are 100V, high frequency, half-bridge
N-Channel power MOSFET driver ICs. They are based on
the popular HIP2100, HIP2101 half-bridge drivers, but offer
several performance improvements. Peak output pull-up/
pull-down current has been increased to 3A/4A, which
significantly reduces switching power losses and eliminates
the need for external totem-pole buffers in many
• SOIC, DFN and TDFN Packages Compliant with 100V
Conductor Spacing Guidelines per IPC-2221
• Pb-Free (RoHS Compliant)
• Bootstrap Supply Max Voltage to 114VDC
• On-Chip 1W Bootstrap Diode
applications. Also, the low end of the V
operational supply
DD
range has been extended to 8VDC. The ISL2110 has
additional input hysteresis for superior operation in noisy
environments and the inputs of the ISL2111, like those of the
• Fast Propagation Times for Multi-MHz Circuits
• Drives 1nF Load with Typical Rise/Fall Times of 9ns/7.5ns
• CMOS Compatible Input Thresholds (ISL2110)
• 3.3V/TTL Compatible Input Thresholds (ISL2111)
• Independent Inputs Provide Flexibility
• No Start-Up Problems
ISL2110, can now safely swing to the V
supply rail.
DD
Ordering Information
PART
NUMBER
(Notes 1, 2) MARKING
TEMP
RANGE
(°C)
PART
PACKAGE
(Pb-Free)
PKG.
DWG. #
• Outputs Unaffected by Supply Glitches, HS Ringing Below
Ground or HS Slewing at High dv/dt
ISL2110ABZ 2110 ABZ
-40 to +125 8 Ld SOIC
M8.15
ISL2110AR4Z 211 0AR4Z -40 to +125 12 Ld 4x4 DFN L12.4x4A
ISL2111ABZ 2111 ABZ -40 to +125 8 Ld SOIC M8.15
• Low Power Consumption
• Wide Supply Voltage Range (8V to 14V)
• Supply Undervoltage Protection
ISL2111AR4Z 211 1AR4Z -40 to +125 12 Ld 4x4 DFN L12.4x4A
ISL2111ARTZ 211 1ARTZ -40 to +125 10 Ld 4x4 TDFN L10.4x4
• 1.6W/1W Typical Output Pull-Up/Pull-Down Resistance
ISL2111BR4Z 211 1BR4A -40 to +125 8 Ld 4x4 DFN
NOTES:
L8.4x4
Applications
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
• Telecom Half-Bridge DC/DC Converters
• Telecom Full-Bridge DC/DC Converters
• Two-Switch Forward Converters
• Active-Clamp Forward Converters
• Class-D Audio Amplifiers
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
3. ForMoisture Sensitivity Level(MSL), pleaseseedeviceinformation
page for ISL2110, ISL2111. For more information on MSL please
see techbrief TB363.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2006-2009, 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL2110, ISL2111
Pinouts
ISL2111ARTZ
(10 LD 4x4 TDFN)
TOP VIEW
ISL2110AR4Z, ISL2111AR4Z
(12 LD 4x4 DFN)
TOP VIEW
VDD
LO
1
2
3
4
5
10
9
VDD
NC
NC
HB
HO
HS
1
2
3
4
5
6
12
11
10
9
LO
VSS
NC
NC
LI
HB
HO
HS
NC
VSS
LI
8
EPAD*
7
HI
8
NC
6
7
HI
*EPAD = Exposed PAD
ISL2110ABZ, ISL2111ABZ
(8 LD SOIC)
ISL2111BR4Z
(8 LD 4x4 DFN)
TOP VIEW
TOP VIEW
1
2
3
4
8
7
6
5
LO
VSS
LI
VDD
V
LO
1
2
3
4
8
7
6
DD
HB
HO
HS
HB
HO
HS
V
SS
LI
HI
EPAD*
5
HI
*EPAD = EXPOSED PAD
Application Block Diagram
+12V
+100V
SECONDARY
CIRCUIT
V
DD
HB
DRIVE
HI
HO
HS
LO
HI
PWM
CONTROLLER
DRIVE
LO
LI
ISL2110
ISL2111
REFERENCE
AND
ISOLATION
V
SS
FN6295.6
March 8, 2012
2
ISL2110, ISL2111
Functional Block Diagram
HB
HO
V
DD
HI
UNDER
VOLTAGE
LEVEL SHIFT
DRIVER
HS
ISL2111
UNDER
VOLTAGE
LO
ISL2111
DRIVER
LI
V
SS
EPAD (DFN Package Only)
*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For
best thermal performance connect the EPAD to the PCB power ground plane.
+48V
+12V
SECONDARY
CIRCUIT
ISL2110
ISL2111
PWM
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
ISL2110
ISL2111
PWM
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE-CLAMP
FN6295.6
March 8, 2012
3
ISL2110, ISL2111
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
V
- V
(Notes 4, 5) . . . . . . . . -0.3V to 18V
Thermal Resistance (Typical)
θ
(°C/W)
θ (°C/W)
JC
DD, HB
HS
JA
LI and HI Voltages (Note 5) . . . . . . . . . . . . . . . .-0.3V to V
Voltage on LO (Note 5) . . . . . . . . . . . . . . . . . . .-0.3V to V
+ 0.3V
+ 0.3V
+ 0.3V
DD
DD
HB
8 Ld SOIC (Notes 6, 10). . . . . . . . . . . .
10 Ld TDFN (Notes 7, 8) . . . . . . . . . . .
12 Ld DFN (Notes 7, 8) . . . . . . . . . . . .
8 Ld DFN (Notes 7, 8) . . . . . . . . . . . . .
Max Power Dissipation at +25°C in Free Air
8 Ld SOIC (Notes 6, 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W
10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W
12 Ld DFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W
8 Ld DFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W
Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
95
42
40
40
46
5.5
5.5
4.0
Voltage on HO (Note 5) . . . . . . . . . . . . . . V
- 0.3V to V
HS
Voltage on HS (Continuous) (Note 5) . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118V
Average Current in V
to HB Diode . . . . . . . . . . . . . . . . . . 100mA
DD
Maximum Recommended Operating Conditions
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V
DD
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB. . . . .V +7V to V +14V and V - 1V to V +100V
HS HS DD DD
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. The ISL2110 and ISL2111 are capable of derated operation at supply voltages exceeding 14V. Figure 22 shows the high-side voltage derating
curve for this mode of operation.
5. All voltages referenced to V unless otherwise specified.
SS
6. θ is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details.
JA
7. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
8. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. For θ , the “case temp” location is taken at the package top center.
JC
Electrical Specifications
V
= V = 12V, V = V
HB SS
= 0V, No Load on LO or HO, unless otherwise specified.
HS
DD
T
= +25°C
T = -40°C to +125°C
J
J
MIN
TYP MAX (Note 9)
MAX
(Note 9)
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
UNITS
SUPPLY CURRENTS
V
V
V
V
Quiescent Current
Quiescent Current
Operating Current
Operating Current
I
I
ISL2110; LI = HI = 0V
ISL2111; LI = HI = 0V
ISL2110; f = 500kHz
ISL2111; f = 500kHz
LI = HI = 0V
-
-
-
-
-
-
-
-
0.1
0.3
3.4
3.5
0.1
3.4
0.05
1.2
0.25
0.45
5.0
5.0
0.15
5.0
1.5
-
-
-
-
-
-
-
-
-
0.3
0.55
5.5
5.5
0.2
5.5
10
mA
mA
mA
mA
mA
mA
µA
DD
DD
DD
DD
DD
DD
I
I
DDO
DDO
Total HB Quiescent Current
Total HB Operating Current
I
HB
I
f = 500kHz
HBO
HB to V Current, Quiescent
SS
I
LI = HI = 0V; V
= V
= 114V
HBS
HB
HS
= 114V
HS
HB to V Current, Operating
SS
I
f = 500kHz; V
= V
-
mA
HBSO
HB
INPUT PINS
Low Level Input Voltage Threshold
Low Level Input Voltage Threshold
V
V
ISL2110
ISL2111
ISL2110
ISL2111
ISL2110
3.7
4.4
1.8
6.6
1.8
2.2
210
-
-
3.5
1.2
-
-
-
V
V
IL
IL
1.4
High Level Input Voltage Threshold
High Level Input Voltage Threshold
Input Voltage Hysteresis
V
V
-
-
-
-
7.4
2.2
-
7.6
2.4
-
V
IH
-
V
IH
V
-
V
IHYS
Input Pull-Down Resistance
R
-
100
500
kΩ
I
FN6295.6
March 8, 2012
4
ISL2110, ISL2111
Electrical Specifications
V
= V = 12V, V = V
= 0V, No Load on LO or HO, unless otherwise specified. (Continued)
HS
DD
HB
SS
T
= +25°C
T = -40°C to +125°C
J
J
MIN
TYP MAX (Note 9)
MAX
(Note 9)
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
UNITS
UNDERVOLTAGE PROTECTION
V
V
Rising Threshold
V
V
V
V
6.1
-
6.6
0.6
6.1
0.6
7.1
-
5.8
-
7.4
-
V
V
V
V
DD
DD
DDR
DDH
HBR
HBH
Threshold Hysteresis
HB Rising Threshold
5.5
-
6.8
-
5.0
-
7.1
-
HB Threshold Hysteresis
BOOT STRAP DIODE
Low Current Forward Voltage
High Current Forward Voltage
Dynamic Resistance
V
I
I
I
= 100µA
= 100mA
= 100mA
-
-
-
0.5
0.7
0.7
0.6
0.9
1
-
-
-
0.7
1
V
V
Ω
DL
VDD-HB
VDD-HB
VDD-HB
V
DH
R
1.5
D
LO GATE DRIVER
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
V
I
I
= 100mA
-
-
-
-
0.1
0.16
3
0.18
-
-
-
-
0.25
V
V
A
A
OLL
OHL
OHL
LO
LO
V
= -100mA, V
= V
- V
DD LO
0.23
0.3
OHL
I
V
V
= 0V
-
-
-
-
LO
LO
Peak Pull-Down Current
HO GATE DRIVER
I
= 12V
4
OLL
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
V
I
I
= 100mA
-
-
-
-
0.1
0.16
3
0.18
-
-
-
-
0.25
V
V
A
A
OLH
OHH
OHH
HO
HO
V
= -100mA, V
OHH
= V - V
HB
0.23
0.3
HO
I
V
V
= 0V
-
-
-
-
HO
HO
Peak Pull-Down Current
I
= 12V
4
OLH
Switching Specifications
V
= V
= 12V, V = V = 0V, No Load on LO or HO, unless otherwise specified.
SS HS
DD
HB
T
= -40°C
J
T
= +25°C
to +125°C
J
TEST
CONDITIONS MIN TYP MAX (Note 9) (Note 9) UNITS
MIN MAX
PARAMETERS
SYMBOL
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
Delay Matching: Upper Turn-Off to Lower Turn-On
Delay Matching: Lower Turn-Off to Upper Turn-On
Either Output Rise Time (10% to 90%)
t
-
-
32
32
39
38
8
50
50
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
60
60
60
60
16
16
-
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
LPHL
t
HPHL
t
-
LPLH
t
-
HPLH
t
1
1
-
MON
t
6
-
MOFF
t
C = 1nF
9
-
RC
L
Either Output Fall Time (90% to 10%)
t
C = 1nF
-
7.5
0.3
0.19
-
-
-
FC
L
Either Output Rise Time (3V to 9V)
t
C = 0.1µF
-
0.4
0.3
-
0.5
0.4
50
-
R
L
Either Output Fall Time (9V to 3V)
t
C = 0.1µF
-
F
L
Minimum Input Pulse Width that Changes the Output
Bootstrap Diode Turn-On or Turn-Off Time
t
-
PW
t
-
10
-
BS
FN6295.6
March 8, 2012
5
ISL2110, ISL2111
Pin Descriptions
SYMBOL
DESCRIPTION
V
Positive supply to lower gate driver. Bypass this pin to V
.
SS
DD
HB
High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin.
Bootstrap diode is on-chip.
HO
HS
High-side output. Connect to gate of high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this
pin.
HI
LI
High-side input.
Low-side input.
V
Chip negative supply, which will generally be ground.
Low-side output. Connect to gate of low-side power MOSFET.
No Connect.
SS
LO
NC
EPAD
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
Timing Diagrams
LI
HI
HI, LI
t
t
,
t
t
,
HPLH
HPHL
LPHL
LO
HO
LPLH
t
t
MOFF
MON
HO, LO
FIGURE 3. PROPAGATION DELAYS
FIGURE 4. DELAY MATCHING
Typical Performance Curves
10.0
10.0
T = -40°C
T = +25°C
T = -40°C
T = +25°C
1.0
0.1
1.0
T = +125°C
T = +150°C
T = +125°C
T = +150°C
0.1
.
3
.
3
10k
100k
1 10 k
10k
100k
1 10 k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 6. ISL2111 I
DD
OPERATING CURRENT vs
FIGURE 5. ISL2110 I
OPERATING CURRENT vs
DD
FREQUENCY
FREQUENCY
FN6295.6
March 8, 2012
6
ISL2110, ISL2111
Typical Performance Curves (Continued)
10.0
10.0
T = +150°C
T = -40°C
T = +150°C
1.0
1.0
0.1
T = +25°C
T = -40°C
T = +25°C
0.1
T = +125°C
T = +125°C
0.01
0.01
.
3
.
3
10k
100k
1 10 k
10k
100k
FREQUENCY (Hz)
1 10 k
FREQUENCY (Hz)
FIGURE 7. I
OPERATING CURRENT vs FREQUENCY
FIGURE 8. I
OPERATING CURRENT vs FREQUENCY
HB
HBS
300
250
200
150
100
200
150
100
V
= V
= 14V
HB
DD
V
= V
= 14V
HB
DD
V
= V
= 8V
HB
DD
V
= V
= 8V
HB
DD
V
= V
= 12V
50
DD
HB
V
= V
50
= 12V
HB
DD
50
-50
50
-50
0
100
150
0
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 10. LOW LEVEL OUTPUT VOLTAGE vs
TEMPERATURE
FIGURE 9. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
6.7
6.5
0.70
0.65
V
DDR
V
HBH
6.3
6.1
5.9
5.7
5.5
5.3
0.60
0.55
0.50
0.45
0.40
V
HBR
V
DDH
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 12. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
FIGURE 11. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
FN6295.6
March 8, 2012
7
ISL2110, ISL2111
Typical Performance Curves (Continued)
55
55
50
50
45
40
35
30
25
t
t
LPLH
LPLH
45
40
35
30
25
t
t
HPLH
HPLH
t
LPHL
t
LPHL
t
t
HPHL
50
HPHL
50
-50
0
100
150
-50
0
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 13. ISL2110 PROPAGATION DELAYS vs
TEMPERATURE
FIGURE 14. ISL2111 PROPAGATION DELAYS vs
TEMPERATURE
10.0
9.5
9.0
8.0
7.5
t
t
MON
MON
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
7.0
6.5
6.0
t
MOFF
t
MOFF
5.5
5.0
4.5
4.0
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 15. ISL2110 DELAY MATCHING vs TEMPERATURE
FIGURE 16. ISL2111 DELAY MATCHING vs TEMPERATURE
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
V
, V
LO HO
(V)
V
, V (V)
LO HO
FIGURE 17. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE
FIGURE 18. PEAK PULL-DOWN CURRENT vs OUTPUT
VOLTAGE
FN6295.6
March 8, 2012
8
ISL2110, ISL2111
Typical Performance Curves (Continued)
120
320
300
280
260
240
220
200
180
160
140
120
100
80
110
100
90
80
70
60
50
40
30
20
10
0
I
I
DD
DD
I
HB
I
HB
60
40
20
0
0
5
10
, V
15
20
0
5
10
, V
15
20
V
(V)
V
(V)
DD HB
DD HB
FIGURE 20. ISL2111 QUIESCENT CURRENT vs VOLTAGE
FIGURE 19. ISL2110 QUIESCENT CURRENT vs VOLTAGE
1.00
0.10
0.01
120
100
80
60
40
20
0
.
-3
-4
-5
-6
1 10
.
1 10
.
1 10
.
1 10
12
13
14
15
16
0.3
0.4
0.5
0.6
0.7
0.8
V
TO
V
FORWARD VOLTAGE (V)
VOLTA
GE
(V)
DD
SS
FIGURE 21. BOOTSTRAP DIODE I-V CHARACTERISTICS
FIGURE 22. V
VOLTAGE vs V
VOLTAGE
DD
HS
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FN6295.6
March 8, 2012
9
ISL2110, ISL2111
Package Outline Drawing
L10.4x4
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 1/08
3.2 REF
4.00
A
PIN #1 INDEX AREA
6
8X 0.80 BSC
B
5
1
10X 0 . 40
6
PIN 1
INDEX AREA
4.00
2.60
0.15
(4X)
10
6
0.10 M C A B
C
0.05 M
10 X 0.30
4
TOP VIEW
( 3.00 )
3.00
BOTTOM VIEW
SEE DETAIL "X"
0 .75
( 10 X 0.60 )
C
0.10
C
BASE PLANE
SEATING PLANE
0.08
C
SIDE VIEW
( 3.80)
( 2.60)
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
( 8X 0 . 8 )
( 10X 0 . 30 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6295.6
March 8, 2012
10
ISL2110, ISL2111
Package Outline Drawing
L12.4x4A
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/11
3.2 REF
4.00
A
PIN #1 INDEX AREA
6
10X 0.50 BSC
B
6
1
12X 0 . 45
6
PIN 1
INDEX AREA
4.00
1.58
0.15
(4X)
12
7
0.10 M C A B
C
0.05 M
12 X 0.25
4
TOP VIEW
( 2.80 )
2.80
BOTTOM VIEW
SEE DETAIL "X"
1.00 MAX
( 12 X 0.65 )
C
0.10
BASE PLANE
C
SEATING PLANE
0.08 C
SIDE VIEW
( 3.80)
( 1.58)
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
( 10X 0 . 5 )
( 12X 0 . 25)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6295.6
March 8, 2012
11
ISL2110, ISL2111
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/11
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
AREA
6.20 (0.244)
5.80 (0.228)
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
8°
0°
1
2
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
1
8
SEATING PLANE
0.60 (0.023)
1.27 (0.050)
1.75 (0.069)
1.35 (0.053)
5.00 (0.197)
4.80 (0.189)
2
3
7
6
-C-
4
5
0.25(0.010)
0.10(0.004)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
5.20(0.205)
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN6295.6
March 8, 2012
12
ISL2110, ISL2111
Package Outline Drawing
L8.4x4
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/09
2.4 REF
4.00
A
PIN #1 INDEX AREA
6
6X 0.80 BSC
B
4
1
8X 0 . 40 ± 0.10
6
PIN 1
INDEX AREA
4.00
2.50 ± 0.10
0.15
(4X)
8
5
0.10 M C A B
C
0.05 M
TOP VIEW
( 3.45 )
8 X 0.30
4
3.45 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 .9 ± 0.10
( 8 X 0.60 )
C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
( 3.80)
( 2.50)
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
( 6X 0 . 8 )
( 8X 0 . 30 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6295.6
March 8, 2012
13
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