ISL2111AR4Z [RENESAS]
100V, 3A/4A Peak, High Frequency Half-Bridge Drivers; DFN10, DFN12, DFN8, SOIC8; Temp Range: -40° to 125°C;
| 型号： | ISL2111AR4Z |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 100V, 3A/4A Peak, High Frequency Half-Bridge Drivers; DFN10, DFN12, DFN8, SOIC8; Temp Range: -40° to 125°C 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总15页 (文件大小：754K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL2110, ISL2111
100V, 3A/4A Peak, High Frequency Half-Bridge Drivers
FN6295
Rev.7.00
Mar 16, 2017
The ISL2110, ISL2111 are 100V, high frequency, half-bridge
N-Channel power MOSFET driver ICs. They are based on the
popular HIP2100, HIP2101 half-bridge drivers, but offer
several performance improvements. Peak output
Features
• Drives N-Channel MOSFET half-bridge
• SOIC, DFN, and TDFN package options
pull-up/pull-down current has been increased to 3A/4A, which
significantly reduces switching power losses and eliminates
the need for external totem-pole buffers in many applications.
• SOIC, DFN, and TDFN packages compliant with 100V
conductor spacing guidelines per IPC-2221
• Pb-free (RoHS compliant)
Also, the low end of the V operational supply range has
DD
been extended to 8VDC. The ISL2110 has additional input
hysteresis for superior operation in noisy environments and the
inputs of the ISL2111, like those of the ISL2110, can now
• Bootstrap supply max voltage to 114VDC
• On-chip 1W bootstrap diode
safely swing to the V supply rail.
• Fast propagation times for multi-MHz circuits
• Drives 1nF load with typical rise/fall times of 9ns/7.5ns
• CMOS compatible input thresholds (ISL2110)
• 3.3V/TTL compatible input thresholds (ISL2111)
• Independent inputs provide flexibility
• No start-up problems
DD
Related Literature
• For a full list of related documents, visit our website
- ISL2110, ISL2111 product pages
Applications
• Telecom half-bridge DC/DC converters
• Telecom full-bridge DC/DC converters
• Two-switch forward converters
• Active-clamp forward converters
• Class-D audio amplifiers
• Outputs unaffected by supply glitches, HS ringing below
ground or HS slewing at high dv/dt
• Low power consumption
• Wide supply voltage range (8V to 14V)
• Supply undervoltage protection
• 1.6W/1W typical output pull-up/pull-down resistance
+12V
+100V
SECONDARY
CIRCUIT
V
DD
HB
DRIVE
HI
HO
HS
LO
HI
LI
PWM
CONTROLLER
DRIVE
LO
ISL2110
ISL2111
REFERENCE
AND
ISOLATION
V
SS
FIGURE 1. APPLICATION BLOCK DIAGRAM
FN6295 Rev.7.00
Mar 16, 2017
Page 1 of 15
ISL2110, ISL2111
Functional Block Diagram
HB
HO
V
DD
HI
UNDER
VOLTAGE
LEVEL SHIFT
DRIVER
HS
ISL2111
UNDER
VOLTAGE
LO
ISL2111
DRIVER
LI
V
SS
EPAD (DFN Package Only)
*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best
thermal performance, connect the EPAD to the PCB power ground plane.
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM
FN6295 Rev.7.00
Mar 16, 2017
Page 2 of 15
ISL2110, ISL2111
Application Diagrams
+48V
+12V
SECONDARY
CIRCUIT
ISL2110
ISL2111
PWM
ISOLATION
FIGURE 3. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
ISL2110
ISL2111
PWM
ISOLATION
FIGURE 4. FORWARD CONVERTER WITH AN ACTIVE-CLAMP
Ordering Information
TEMP
PART NUMBER
(Notes 3, 4)
PART
MARKING
RANGE
(°C)
PACKAGE
(RoHS COMPLIANT)
PKG.
DWG. #
ISL2110ABZ (Note 1)
ISL2110AR4Z (Note 2)
ISL2111ABZ (Note 1)
ISL2111AR4Z (Note 2)
ISL2111ARTZ (Note 2)
ISL2111BR4Z (Note 2)
NOTES:
2110 ABZ
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
8 Ld SOIC
M8.15
211 0AR4Z
2111 ABZ
12 Ld 4x4 DFN
8 Ld SOIC
L12.4x4A
M8.15
211 1AR4Z
211 1ARTZ
211 1BR4Z
12 Ld 4x4 DFN
10 Ld 4x4 TDFN
8 Ld 4x4 DFN
L12.4x4A
L10.4x4
L8.4x4
1. Add “-T” for 2.5k unit tape and reel options. Refer to TB347 for details on reel specifications.
2. Add “-T” suffix for 6k unit tape and reel options. Refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL2110, ISL2111. For more information on MSL, see Tech Brief TB363.
FN6295 Rev.7.00
Mar 16, 2017
Page 3 of 15
ISL2110, ISL2111
Pin Configurations
ISL2111ARTZ
ISL2110AR4Z, ISL2111AR4Z
(12 LD 4x4 DFN)
TOP VIEW
(10 LD 4x4 TDFN)
TOP VIEW
VDD
LO
1
2
3
4
5
10
9
VDD
NC
NC
HB
HO
HS
1
2
3
4
5
6
12
11
10
9
LO
VSS
NC
NC
LI
HB
HO
HS
NC
VSS
LI
8
EPAD*
7
HI
8
6
NC
7
HI
*EPAD = EXPOSED PAD
ISL2110ABZ, ISL2111ABZ
(8 LD SOIC)
ISL2111BR4Z
(8 LD 4x4 DFN)
TOP VIEW
TOP VIEW
1
2
3
4
8
7
6
5
LO
VSS
LI
VDD
VDD
LO
1
2
3
4
8
7
6
HB
HO
HS
HB
HO
HS
VSS
LI
HI
EPAD*
5
HI
*EPAD = EXPOSED PAD
Pin Descriptions
SYMBOL
DESCRIPTION
VDD
HB
Positive supply to lower gate driver. Bypass this pin to VSS.
High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap
diode is on-chip.
HO
HS
High-side output. Connect to gate of high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.
HI
High-side input
LI
Low-side input
VSS
LO
Chip negative supply, which will generally be ground.
Low-side output. Connect to gate of low-side power MOSFET.
No connect
NC
EPAD
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
FN6295 Rev.7.00
Mar 16, 2017
Page 4 of 15
ISL2110, ISL2111
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
V
V
(Notes 5, 6) . . . . . . . . . . . . . . . 0.3V to 18V
Thermal Resistance (Typical)
(°C/W)
95
40
39
40
(°C/W)
46
2.5
2.5
4.0
DD, HB - HS
JA
JC
LI and HI Voltages (Note 6) . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V + 0.3V
Voltage on LO (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V + 0.3V
DD
Voltage on HO (Note 6) . . . . . . . . . . . . . . . . . . . . . .V - 0.3V to V + 0.3V
Voltage on HS (Continuous) (Note 6) . . . . . . . . . . . . . . . . . . . . . -1V to 110V
8 Ld SOIC (Notes 7, 10) . . . . . . . . . . . . . . . .
10 Ld TDFN (Notes 8, 9) . . . . . . . . . . . . . . .
12 Ld DFN (Notes 8, 9) . . . . . . . . . . . . . . . .
8 Ld DFN (Notes 8, 9). . . . . . . . . . . . . . . . . .
Max Power Dissipation at +25°C in Free Air
DD
HS
HB
Voltage on HB (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
Average Current in V to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
DD
8 Ld SOIC (Notes 7, 10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W
10 Ld TDFN (Notes 8, 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W
12 Ld DFN (Notes 8, 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W
8 Ld DFN (Notes 8, 9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Maximum Recommended Operating
Conditions
Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V
DD
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . . . . . . . . . .V +7V to V +14V and V - 1V to V +100V
HS HS DD DD
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
5. The ISL2110 and ISL2111 are capable of derated operation at supply voltages exceeding 14V. Figure 24 shows the high-side voltage derating curve
for this mode of operation.
6. All voltages referenced to V unless otherwise specified.
SS
7. is measured with the component mounted on a high-effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
8. is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
9. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
10. For , the “case temp” location is taken at the package top center.
JC
Electrical Specifications
V
= V = 12V, V = V = 0V, no load on LO or HO, unless otherwise specified.
HB SS HS
DD
T = +25°C
T = -40°C to +125°C
J
J
MIN
MAX
MIN
MAX
PARAMETERS
SUPPLY CURRENTS
SYMBOL
TEST CONDITIONS
(Note 11) TYP (Note 11) (Note 11) (Note 11) UNIT
V
V
V
V
Quiescent Current
Quiescent Current
Operating Current
Operating Current
I
I
ISL2110; LI = HI = 0V
ISL2111; LI = HI = 0V
ISL2110; f = 500kHz
ISL2111; f = 500kHz
LI = HI = 0V
-
-
-
-
-
-
-
-
0.10
0.30
3.4
0.25
0.45
5.0
-
-
-
-
-
-
-
-
0.30
0.55
5.5
5.5
0.20
5.5
10
mA
mA
mA
mA
mA
mA
µA
DD
DD
DD
DD
DD
DD
I
I
DDO
DDO
3.5
5.0
Total HB Quiescent Current
Total HB Operating Current
I
0.10
3.4
0.15
5.0
HB
I
I
f = 500kHz
HBO
HB to V Current, Quiescent
SS
LI = HI = 0V; V = V = 114V
HB HS
0.05
1.2
1.50
-
HBS
HB to V Current, Operating
SS
I
f = 500kHz; V = V = 114V
HB HS
-
mA
HBSO
INPUT PINS
Low Level Input Voltage Threshold
Low Level Input Voltage Threshold
High Level Input Voltage Threshold
High Level Input Voltage Threshold
Input Voltage Hysteresis
V
V
ISL2110
ISL2111
ISL2110
ISL2111
ISL2110
3.7
4.4
1.8
6.6
1.8
2.2
210
-
3.5
-
-
V
V
IL
IL
1.4
-
7.4
2.2
-
1.2
V
V
-
-
-
-
-
7.6
2.4
-
V
IH
-
-
V
IH
V
V
IHYS
Input Pull-Down Resistance
R
-
100
500
kΩ
I
FN6295 Rev.7.00
Mar 16, 2017
Page 5 of 15
ISL2110, ISL2111
Electrical Specifications
V
= V = 12V, V = V = 0V, no load on LO or HO, unless otherwise specified. (Continued)
HB SS HS
DD
T = +25°C
T = -40°C to +125°C
J
J
MIN
MAX
MIN
MAX
PARAMETERS
SYMBOL
TEST CONDITIONS
(Note 11) TYP (Note 11) (Note 11) (Note 11) UNIT
UNDERVOLTAGE PROTECTION
V
V
Rising Threshold
V
V
V
6.1
6.6
0.6
6.1
0.6
7.1
5.8
7.4
V
V
V
V
DD
DD
DDR
DDH
HBR
Threshold Hysteresis
-
5.5
-
-
6.8
-
-
5.0
-
-
7.1
-
HB Rising Threshold
HB Threshold Hysteresis
BOOTSTRAP DIODE
V
HBH
Low Current Forward Voltage
High Current Forward Voltage
Dynamic Resistance
V
I
= 100µA
= 100mA
= 100mA
-
-
-
0.5
0.7
0.7
0.6
0.9
1
-
-
-
0.7
1
V
V
DL
VDD-HB
VDD-HB
VDD-HB
V
I
I
DH
R
1.5
Ω
D
LO GATE DRIVER
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
V
I
I
= 100mA
-
-
-
-
0.1
0.16
3
0.18
-
-
-
-
0.25
V
V
A
A
OLL
OHL
OHL
LO
LO
V
= -100mA, V
= 0V
= V - V
DD LO
0.23
0.3
OHL
I
V
V
-
-
-
-
LO
LO
Peak Pull-Down Current
HO GATE DRIVER
I
= 12V
4
OLL
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
V
I
I
= 100mA
-
-
-
-
0.1
0.16
3
0.18
-
-
-
-
0.25
V
V
A
A
OLH
OHH
OHH
HO
HO
V
= -100mA, V
= 0V
= V - V
HB HO
0.23
0.3
OHH
I
V
V
-
-
-
-
HO
HO
Peak Pull-Down Current
I
= 12V
4
OLH
Switching Specifications
V
= V = 12V, V = V = 0V, No Load on LO or HO, unless otherwise specified.
HB SS HS
DD
T = +25°C
T = -40°C to +125°C
J
J
TEST
MIN
MAX
MIN
MAX
PARAMETERS
SYMBOL CONDITIONS (Note 11) TYP (Note 11) (Note 11)
(Note 11)
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
Delay Matching: Upper Turn-Off to Lower Turn-On
Delay Matching: Lower Turn-Off to Upper Turn-On
Either Output Rise Time (10% to 90%)
t
-
-
32
32
39
38
8
50
-
-
-
-
-
-
-
-
-
-
-
-
60
60
60
60
16
16
-
LPHL
t
50
HPHL
t
-
50
LPLH
t
-
50
HPLH
t
1
1
-
-
MON
t
6
-
MOFF
t
C = 1nF
9
-
RC
L
Either Output Fall Time (90% to 10%)
t
C = 1nF
-
7.5
0.3
0.19
-
-
0.4
0.3
-
-
FC
L
Either Output Rise Time (3V to 9V)
t
C = 0.1µF
-
0.5
0.4
50
-
R
L
Either Output Fall Time (9V to 3V)
t
C = 0.1µF
-
F
L
Minimum Input Pulse Width that Changes the Output
Bootstrap Diode Turn-On or Turn-Off Time
NOTE:
t
-
PW
t
-
10
-
BS
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN6295 Rev.7.00
Mar 16, 2017
Page 6 of 15
ISL2110, ISL2111
Timing Diagrams
LI
HI
HI, LI
t
t
,
t
t
,
HPLH
HPHL
LPHL
LO
HO
LPLH
t
t
MOFF
MON
HO, LO
FIGURE 5. PROPAGATION DELAYS
FIGURE 6. DELAY MATCHING
FN6295 Rev.7.00
Mar 16, 2017
Page 7 of 15
ISL2110, ISL2111
Typical Performance Curves
10.0
10.0
1.0
T = -40°C
T = -40°C
T = +25°C
T = +25°C
1.0
T = +125°C
T = +125°C
T = +150°C
T = +150°C
0.1
0.1
.
3
.
3
10k
100k
1 10 k
10k
100k
FREQUENCY (Hz)
1 10 k
FREQUENCY (Hz)
FIGURE 7. ISL2110 I OPERATING CURRENT vs FREQUENCY
DD
FIGURE 8. ISL2111 I OPERATING CURRENT vs FREQUENCY
DD
10.0
10.0
T = +150°C
T = -40°C
T = +150°C
1.0
1.0
T = +25°C
T = -40°C
T = +25°C
0.1
0.1
T = +125°C
T = +125°C
0.01
0.01
.
3
.
3
10k
100k
1 10 k
10k
100k
1 10 k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. I OPERATING CURRENT vs FREQUENCY
HB
FIGURE 10. I
OPERATING CURRENT vs FREQUENCY
HBS
300
250
200
150
100
50
200
150
100
V
= V
= 14V
HB
DD
V
= V
= 14V
HB
DD
V
= V
= 8V
HB
DD
V
= V
= 8V
HB
DD
V
= V
= 12V
50
DD
HB
V
= V
50
= 12V
HB
DD
50
-50
0
100
150
-50
0
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 12. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 11. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
FN6295 Rev.7.00
Mar 16, 2017
Page 8 of 15
ISL2110, ISL2111
Typical Performance Curves (Continued)
6.7
6.5
0.70
0.65
0.60
0.55
0.50
0.45
0.40
V
DDR
V
HBH
6.3
6.1
5.9
5.7
5.5
5.3
V
HBR
V
DDH
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 14. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
FIGURE 13. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
55
55
50
50
45
40
35
30
25
t
t
LPLH
LPLH
45
40
35
30
25
t
t
HPLH
HPLH
t
LPHL
t
LPHL
t
t
HPHL
50
HPHL
50
-50
0
100
150
-50
0
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 15. ISL2110 PROPAGATION DELAYS vs TEMPERATURE
FIGURE 16. ISL2111 PROPAGATION DELAYS vs TEMPERATURE
10.0
9.5
9.0
8.0
7.5
t
t
MON
MON
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
7.0
6.5
6.0
t
MOFF
t
MOFF
5.5
5.0
4.5
4.0
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 17. ISL2110 DELAY MATCHING vs TEMPERATURE
FIGURE 18. ISL2111 DELAY MATCHING vs TEMPERATURE
FN6295 Rev.7.00
Mar 16, 2017
Page 9 of 15
ISL2110, ISL2111
Typical Performance Curves (Continued)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
V
, V
(V)
V
, V
(V)
LO HO
LO HO
FIGURE 20. PEAK PULL-DOWN CURRENT vs OUTPUT VOLTAGE
FIGURE 19. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE
120
320
300
110
100
90
80
70
60
50
40
30
20
10
0
I
I
DD
DD
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
I
HB
I
HB
0
5
10
, V
15
20
0
5
10
, V
15
20
V
(V)
V
(V)
DD HB
DD HB
FIGURE 21. ISL2110 QUIESCENT CURRENT vs VOLTAGE
FIGURE 22. ISL2111 QUIESCENT CURRENT vs VOLTAGE
1.00
0.10
0.01
120
100
80
60
40
20
0
.
-3
-4
-5
-6
1 10
.
1 10
.
1 10
.
1 10
12
13
14
15
16
0.3
0.4
0.5
0.6
0.7
0.8
V
TO
V
FORWARD VOLTAGE (V)
VOLTA
GE
(V)
DD
SS
FIGURE 23. BOOTSTRAP DIODE I-V CHARACTERISTICS
FIGURE 24. V VOLTAGE vs V VOLTAGE
HS DD
FN6295 Rev.7.00
Mar 16, 2017
Page 10 of 15
ISL2110, ISL2111
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
FN6295.7
CHANGE
Mar 16, 2017
Corrected the branding of FG ISL2111BR4Z in the order information table from "211 1BR4A" to "211
1BR4Z".
Added Revision History table and About Intersil information.
Updated L10.4x4 Package Outline Drawing from Rev 1 to Rev 2. Change since Rev 1 is:
“Tiebar note update from ‘Tiebar shown (if present) is a non-functional feature’ to ‘Tiebar shown (if
present) is a non-functional feature and may be located on any of the 4 sides (or ends)’”.
Updated L12.4x4A Package Outline Drawing from Rev 1 to Rev 3. Changes since Rev 1 are:
“Tiebar note update from ‘Tiebar shown (if present) is a non-functional feature’ to ‘Tiebar shown (if
present) is a non-functional feature and may be located on any of the 4 sides (or ends)’”;
“Bottom View changed from ‘3.2 REF’ TO ‘2.5 REF’";
“Typical Recommended Land Pattern changed from ‘3.80’ to ‘3.75’";
“Updated to new POD format by removing table listing dimensions and moving dimensions onto drawing”,
and “Added typical recommended land pattern”.
Updated M8.15 Package Outline Drawing from Rev 3 to Rev 4. Change since Rev 3 is:
“Changed Note 1 from 1982 to 1994“.
Updated L8.4x4 Package Outline Drawing from Rev 0 to Rev 1. Change since Rev 0 is:
“Tiebar note update from ‘Tiebar shown (if present) is a non-functional feature’ to ‘Tiebar shown (if
present) is a non-functional feature and may be located on any of the 4 sides (or ends)’”.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.
For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information
page found at www.intersil.com.
For a listing of definitions and abbreviations of common terms used in our documents, visit: www.intersil.com/glossary.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2006-2017. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6295 Rev.7.00
Mar 16, 2017
Page 11 of 15
ISL2110, ISL2111
For the most recent package outline drawing, see L10.4x4.
Package Outline Drawing
L10.4x4
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 4/15
3.2 REF
4.00
A
PIN #1 INDEX AREA
6
8X 0.80 BSC
B
5
1
10X 0 . 40
6
PIN 1
INDEX AREA
4.00
2.60
0.15
(4X)
10
6
0.10 M C A B
C
0.05 M
TOP VIEW
( 3.00 )
10 X 0.30
4
3.00
BOTTOM VIEW
SEE DETAIL "X"
0 .75
(10 X 0.60)
C
0.10
C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
(3.80)
(2.60)
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
(8X 0.8)
(10X 0.30)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature and may
be located on any of the 4 sides (or ends).
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6295 Rev.7.00
Mar 16, 2017
Page 12 of 15
ISL2110, ISL2111
Package Outline Drawing
For the most recent package outline drawing, see L12.4x4A.
L12.4x4A
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 3/15
2.5 REF
4.00
A
PIN #1 INDEX AREA
6
10X 0.50 BSC
B
6
1
12X 0 . 45
6
PIN 1
INDEX AREA
4.00
1.58
0.15
(4X)
12
7
0.10 M C A B
C
0.05 M
12 X 0.25
4
TOP VIEW
( 2.80 )
2.80
BOTTOM VIEW
SEE DETAIL "X"
1.00 MAX
( 12 X 0.65 )
C
0.10
BASE PLANE
C
SEATING PLANE
0.08 C
SIDE VIEW
0 . 2 REF
( 3.75)
( 1.58)
C
0 . 00 MIN.
0 . 05 MAX.
( 10X 0 . 5 )
( 12X 0 . 25)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature and may
be located on any of the 4 sides (or ends).
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
6.
FN6295 Rev.7.00
Mar 16, 2017
Page 13 of 15
ISL2110, ISL2111
For the most recent package outline drawing, see M8.15.
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
AREA
6.20 (0.244)
5.80 (0.228)
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
8°
0°
1
2
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
1
8
SEATING PLANE
0.60 (0.023)
1.27 (0.050)
1.75 (0.069)
5.00 (0.197)
4.80 (0.189)
2
3
7
6
1.35 (0.053)
-C-
4
5
0.25(0.010)
0.10(0.004)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
5.20(0.205)
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN6295 Rev.7.00
Mar 16, 2017
Page 14 of 15
ISL2110, ISL2111
For the most recent package outline drawing, see L8.4x4.
Package Outline Drawing
L8.4x4
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 03/15
2.4 REF
4.00
A
PIN #1 INDEX AREA
6
6X 0.80 BSC
B
4
1
8X 0 . 40 ± 0.10
6
PIN 1
INDEX AREA
4.00
2.50 ± 0.10
0.15
(4X)
8
5
0.10 M C A B
C
0.05 M
TOP VIEW
( 3.45 )
8 X 0.30
4
3.45 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
0 .9 ± 0.10
( 8 X 0.60 )
C
0.10
BASE PLANE
C
SEATING PLANE
0.08 C
SIDE VIEW
( 3.80)
( 2.50)
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
( 6X 0 . 8 )
( 8X 0 . 30 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature and may
be located on any of the 4 sides (or ends).
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6295 Rev.7.00
Mar 16, 2017
Page 15 of 15
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