ISL21007CFB825Z [INTERSIL]
Precision, Low Noise FGA⑩ Voltage References; 精密，低噪声FGA ™电压基准
| 型号： | ISL21007CFB825Z |
| 厂家： | 
Intersil |
| 描述： | Precision, Low Noise FGA⑩ Voltage References |
| 文件： | 总14页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL21007
®
Data Sheet
April 12, 2007
FN6326.1
Precision, Low Noise FGA™ Voltage
References
Features
• Reference Output Voltage . . . . . . . . . . . . . . .1.25V, 2.50V
• Initial Accuracy. . . . . . . . . . . . . . . . . . . .±0.5mV (B grade)
• Input Voltage Range: . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
• Low Output Voltage Noise . . . . . . 4µVP-P (0.1Hz to 10Hz)
• Supply Current . . . . . . . . . . . . . . . . . . . . . . . .150µA (Max)
• Temperature Coefficient. . . . . . . . . . . . 3ppm/°C (B grade)
• Operating Temperature Range. . . . . . . . .-40°C to +125°C
• Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC
• Pb-Free Plus Anneal Available (RoHS Compliant)
The ISL21007 FGA™ voltage references are extremely low
power, high precision, and low noise voltage references
fabricated on Intersil’s proprietary Floating Gate Analog
technology. The ISL21007 features very low noise (4µVP-P
for 0.1Hz to 10Hz) and very low operating current (150µA,
Max). In addition, the ISL21007 family features guaranteed
initial accuracy as low as ±0.5mV.
This combination of high initial accuracy, low drift, and low
output noise performance of the ISL21007 enables versatile
high performance control and data acquisition applications
with low power consumption.
Applications
Available Options
• High Resolution A/Ds and D/As
• Digital Meters
VOUT
OPTION
(V)
INITIAL
ACCURACY
(mV)
TEMPCO.
(ppm/°C)
PART NUMBER
ISL21007BFB812Z
ISL21007CFB812Z
ISL21007DFB812Z
ISL21007BFB825Z
ISL21007CFB825Z
ISL21007DFB825Z
• Bar Code Scanners
1.250
1.250
1.250
2.500
2.500
2.500
±0.5
±1.0
±2.0
±0.5
±1.0
±2.0
3
5
• Basestations
• Battery Management/Monitoring
• Industrial/Instrumentation Equipment
10
3
5
10
Pinout
ISL21007
(8 LD SOIC)
TOP VIEW
GND or NC
VIN
1
2
3
4
8
7
6
5
DNC
DNC
VOUT
TRIM
DNC
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL21007
Ordering Information
PART NUMBER
VOUT OPTION
(V)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
(Note)
PART MARKING
GRADE
PKG. DWG. #
M8.15
ISL21007BFB812Z
ISL21007CFB812Z
ISL21007DFB812Z
ISL21007BFB825Z
ISL21007CFB825Z
ISL21007DFB825Z
21007BF Z12
21007CF Z12
21007DF Z12
21007BF Z25
21007CF Z25
21007DF Z25
1.250
1.250
1.250
2.500
2.500
2.500
±0.5mV, 3ppm/°C
±1.0mV, 5ppm/°C
±2.0mV, 10ppm/°C
±0.5mV, 3ppm/°C
±1.0mV, 5ppm/°C
±2.0mV, 10ppm/°C
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
M8.15
M8.15
M8.15
M8.15
M8.15
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add “-TK” suffix for tape and reel
FN6326.1
April 12, 2007
2
ISL21007
Pin Descriptions
PIN NUMBER
PIN NAME
GND or NC
VIN
DESCRIPTION
1
Ground Connection
2
Power Supply Input Connection
4
GND
Voltage Reference Output Connection
5
6
TRIM
Allows user trim ±2.5%
VOUT
DNC
Do Not Connect; Internal Connection – Must Be Left Floating
Do Not Connect; Internal Connection - Must Be Left Floating
3, 7, 8
Typical Application Circuit
1
8
GND
VIN
NC
+3V
2
3
4
7
6
5
NC
VOUT
C1
10µF
NC
NC
GND
ISL21007-12, 25
SPI BUS
X79000
1
SCK
2
20
19
18
17
16
15
14
13
12
11
/CS
A0
3
CLR
VCC
VH
A1
4
A2
5
SI
VL
C1
0.001µF
6
SO
7
VREF
VSS
VOUT
VBUF
VFB
/RDY
8
UP
9
LOW NOISE DAC OUTPUT
DOWN
10
OE
FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUBRANGING DAC
FN6326.1
April 12, 2007
3
ISL21007
Absolute Voltage Ratings
Thermal Information
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Max Voltage VIN to Gnd. . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V
Max Voltage VOUT to Gnd (10s). . . . . . . . . . . . . . .-0.5V to VOUT + 1
Voltage on “DNC” pins . . . . No connections permitted to these pins.
Lead Temperature, soldering (10s) . . . . . . . . . . . . . . . . . . . .+260°C
ESD Rating
Continuous Power Dissipation (TA = +70°C) (Note 1)
8 Lead SOIC derate 5.88mW/°C above +70°C . . . . . .
Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
471mW
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600V
Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at
the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Common Electrical Specifications (ISL21007-12, -25)TA = -40°C to +125°C, unless otherwise specified.
PARAMETER
VIN
DESCRIPTION
Input Voltage Range
CONDITIONS
MIN
2.7
TYP
MAX
5.5
+0.5
+1.0
+2.0
3
UNIT
V
VOA
VOUT Accuracy @ TA = +25°C
ISL21007B
ISL21007C
ISL21007D
ISL21007B
ISL21007C
ISL21007D
-0.5
-1.0
-2.0
mV
mV
mV
TC VOUT
Output Voltage Temperature
Coefficient (Note 2)
ppm/°C
ppm/°C
ppm/°C
µA
5
10
IIN
Supply Current
75
TBD
±2.5
120
60
150
ΔVOUT/Δt
Long Term Stability (Note 4)
Trim Range
TA = +25°C
ppm/√1kHrs
%
±2.0
tR
Turn on Settling Time
Ripple Rejection
VOUT = ±0.1%
f = 10kHz
µs
dB
eN
VN
Output Voltage Noise
Broadband Voltage Noise
Noise Density
0.1Hz ≤ f ≤ 10Hz
10Hz ≤ f ≤ 1kHz
f = 1kHz
4
µVP-P
µVRMS
nV/√Hz
2.2
60
Electrical Specifications (ISL21007-12, V
= 1.250V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified.
OUT
PARAMETER
VOUT
DESCRIPTION
Output Voltage
CONDITIONS
MIN
TYP
1.250
100
10
MAX
UNIT
V
ΔVOUT /ΔVIN
ΔVOUT/ΔIOUT
Line Regulation
Load Regulation
2.7V < VIN < 5.5V
700
100
150
µV/V
µV/mA
µV/mA
mA
Sourcing: 0mA ≤ IOUT ≤ 7mA
Sinking: -7mA ≤ IOUT ≤ 0mA
TA = +25°C, VOUT tied to GND
ΔTA = +165°C
20
ISC
Short Circuit Current
40
ΔVOUT/ΔTA
Thermal Hysteresis (Note 3)
50
ppm
FN6326.1
April 12, 2007
4
ISL21007
Electrical Specifications (ISL21007-25, V
= 2.50V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified
OUT
PARAMETER
VOUT
DESCRIPTION
Output Voltage
CONDITIONS
MIN
TYP
2.500
50
MAX
UNIT
V
ΔVOUT /ΔVIN
ΔVOUT/ΔIOUT
Line Regulation
Load Regulation
2.7V < VIN < 5.5V
200
100
150
µV/V
µV/mA
µV/mA
mA
Sourcing: 0mA ≤ IOUT ≤ 5mA
Sinking: -5mA ≤ IOUT ≤ 0mA
TA = +25°C, VOUT tied to GND
ΔTA = +165°C
10
20
ISC
Short Circuit Current
50
ΔVOUT/ΔTA
NOTES:
Thermal Hysteresis (Note 3)
50
ppm
2. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the
temperature range; in this case, -40°C to +125°C = +165°C.
3. Thermal Hysteresis is the change of VOUT measured @ TA = +25°C after temperature cycling over a specified range, ΔTA. VOUT is read initially
at TA = +25°C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25°C. The difference
between the initial VOUT reading and the second VOUT reading is then expressed in ppm. For Δ TA = +165°C, the device under test is cycled
from +25°C to +125°C to -40°C to +25°C.
4. FGA voltage reference long term drift is a logarithmic characteristic. Changes that occur after the first few hundred hours of operation are
significantly smaller with time, asymptotically approaching zero beyond 1,000 hours. Because of this decreasing characteristics, long term drift
is specified in ppm/√1kHrs.
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ)
95
90
85
80
75
70
65
60
120
100
80
60
40
20
0
UNIT 3
+125°C
UNIT 2
UNIT 1
+25°C
-40°C
4.0
2.5
3.0
3.5
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
V
(V)
IN
V
IN
FIGURE 2. IIN vs VIN (3 UNITS)
FIGURE 3. IIN vs VIN OVER TEMPERATURE
1.25015
1.25010
1.25005
1.25000
1.24995
1.24990
1.24985
1.24980
150
100
50
+125°C
UNIT 3
0
+25°C
-50
-40°C
UNIT 2
-100
-150
-200
-250
-300
UNIT 1
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
V
V
IN
IN
FIGURE 5. LINE REGULATION OVER TEMPERATURE
FIGURE 4. LINE REGULATION (3 UNITS)
FN6326.1
April 12, 2007
5
ISL21007
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ) (Continued)
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
1.25010
1.25005
1.25000
1.24995
1.24990
1.24985
1.24980
1.24975
+125°C
+25°C
UNIT 1
UNIT 2
-40°C
UNIT 3
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
-40
-20
0
20
40
60
80
100 120 140
SINKING OUTPUT CURRENT (mA)
SOURCING
TEMPERATURE (°C)
FIGURE 6. LOAD REGULATION OVER TEMPERATURE
FIGURE 7. VOUT vs TEMPERATURE (3 UNITS)
X: 5µs/DIV
X: 5µs/DIV
Y: 500mV/DIV
Y: 500mV/DIV
FIGURE 9. LINE TRANSIENT RESPONSE, 0.001µF LOAD
FIGURE 8. LINE TRANSIENT RESPONSE, NO CAPACITIVE
LOAD
CAPACITANCE
X: 20µs/DIV
Y: 1V/DIV
120
NO LOAD
1nF LOAD
100
80
60
40
20
0
10nF LOAD
V
IN
V
= 1.25V (FOR TYP I )
IN
OUT
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 10. TURN ON TIME
FIGURE 11. Z
vs FREQUENCY
OUT
FN6326.1
April 12, 2007
6
ISL21007
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ) (Continued)
GAIN IS x1000,
NOISE IS 4µV
NO OUTPUT CAPACITANCE
X: 50µs/DIV
p-p
Y: 1V/DIV
+7mA
-7mA
FIGURE 13. LOAD TRANSIENT RESPONSE
FIGURE 12. VOUT NOISE, 0.1Hz to 10Hz
0
V
(DC) = 3V
NO LOAD
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
IN
V
(AC) = 50mV
IN
P-P
1nF LOAD
10nF LOAD
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 14. PSRR vs CAPACITIVE LOADS
FN6326.1
April 12, 2007
7
ISL21007
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ)
100
95
90
85
80
75
70
65
60
120
100
80
60
40
20
0
UNIT 3
+125°C
UNIT 2
UNIT 1
+25°C
-40°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
(V)
IN
IN
FIGURE 15. IIN vs VIN (3 UNITS)
FIGURE 16. IIN vs VIN OVER TEMPERATURE
2.50020
2.50010
2.50000
2.49990
2.49980
2.49970
2.49960
100
50
0
UNIT 1
-50
+25°C
UNIT 2
-100
-150
-200
-250
-300
-350
-400
+125°C
UNIT 3
-40°C
2.5
3.0
3.5
4.0
V
4.5
5.0
5.5
6.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
(V)
V
IN
IN
FIGURE 17. LINE REGULATION (3 UNITS)
+125°C
FIGURE 18. LINE REGULATION OVER TEMPERATURE
2.5003
UNIT 2
0.60
0.40
2.5002
2.5001
2.5000
2.4999
2.4998
2.4997
2.4996
2.4995
2.4994
2.4993
NORMALIZED TO +25°C
UNIT 1
0.20
0.00
-0.20
-0.40
-0.60
-0.80
-1.00
+25°C
-40°C
UNIT 3
-40
-20
0
20
40
60
80
100 120 140
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
TEMPERATURE (°C)
SINKING OUTPUT CURRENT (mA)
SOURCING
FIGURE 20. VOUT vs TEMPERATURE (3 UNITS)
FIGURE 19. LOAD REGULATION OVER TEMPERATURE
FN6326.1
April 12, 2007
8
ISL21007
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ) (Continued)
X: 5µs/DIV
Y: 500mV/DIV
X: 5µs/DIV
Y: 500mV/DIV
FIGURE 21. LINE TRANSIENT RESPONSE, NO CAPACITIVE
LOAD
FIGURE 22. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
X: 20µs/DIV
Y: 1V/DIV
160
1nF LOAD
NO LOAD
140
120
10nF LOAD
100
80
60
40
20
0
V
IN
V
= 2.5V (FOR TYP I )
IN
OUT
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 24. Z
vs FREQUENCY
FIGURE 23. TURN ON TIME
OUT
GAIN IS x1000,
NOISE IS 4µV
P-P
NO OUTPUT CAPACITANCE
X: 50µs/DIV
Y: 500mV/DIV
+5mA
-5mA
FIGURE 25. VOUT NOISE, 0.1Hz to 10Hz
FIGURE 26. LOAD TRANSIENT RESPONSE
FN6326.1
April 12, 2007
9
ISL21007
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ) (Continued)
0
V
(DC) = 3V
NO LOAD
1nF LOAD
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
IN
V
(AC) = 50mV
IN
P-P
10nF LOAD
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 27. PSRR vs CAPACITIVE LOADS
Board Mounting Considerations
Applications Information
For applications requiring the highest accuracy, board
mounting location should be reviewed. The device uses a
plastic SOIC package which will subject the die to mild
stresses when the PC board is heated and cooled and
slightly changes shape. Placing the device in areas subject
to slight twisting can cause degradation of the accuracy of
the reference voltage due to these die stresses. It is normally
best to place the device near the edge of a board, or the
shortest side, as the axis of bending is most limited at that
location. Mounting the device in a cutout also minimizes flex.
Obviously mounting the device on flexprint or extremely thin
PC material will likewise cause loss of reference accuracy.
FGA Technology
The ISL21007 voltage reference uses floating gate
technology to create references with very low drift and
supply current. Essentially the charge stored on a floating
gate cell is set precisely in manufacturing. The reference
voltage output itself is a buffered version of the floating gate
voltage. The resulting reference device has excellent
characteristics which are unique in the industry: very low
temperature drift, high initial accuracy, and almost zero
supply current. Also, the reference voltage itself is not limited
by voltage bandgaps or zener settings, so a wide range of
reference voltages can be programmed (standard voltage
settings are provided, but customer-specific voltages are
available).
Noise Performance and Reduction
The output noise voltage in a 0.1Hz to 10Hz bandwidth is
typically 4µVP-P. The noise measurement is made with a
bandpass filter made of a 1 pole high-pass filter with a corner
frequency at 0.1Hz and a 2-pole low-pass filter with a corner
frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth.
Noise in the 10kHz to 1MHz bandwidth is approximately
40µVP-P with no capacitance on the output. This noise
measurement is made with a 2 decade bandpass filter made
of a 1 pole high-pass filter with a corner frequency at 1/10 of
the center frequency and 1-pole low-pass filter with a corner
frequency at 10 times the center frequency. Load capacitance
up to 1000pF can be added but will result in only marginal
improvements in output noise and transient response. The
output stage of the ISL21007 is not designed to drive heavily
capactive loads, so for load capacitances above 0.001µF the
noise reduction network shown in Figure 28 is recommended.
This network reduces noise significantly over the full
The process used for these reference devices is a floating
gate CMOS process, and the amplifier circuitry uses CMOS
transistors for amplifier and output transistor circuitry. While
providing excellent accuracy, there are limitations in output
noise level and load regulation due to the MOS device
characteristics. These limitations are addressed with circuit
techniques discussed in other sections.
Micropower Operation
The ISL21007 consumes extremely low supply current due
to the proprietary FGA technology. Low noise performance is
achieved using optimized biasing techniques. Supply current
is typically 75µA and noise is 4µVP-P benefitting precision,
low noise portable applications such as handheld meters
and instruments.
Data Converters in particular can utilized the ISL21007 as an
external voltage reference. Low power DAC and ADC
circuits will realize maximum resolution with lowest noise.
bandwidth. Noise is reduced to less than 20µVP-P from 1Hz to
1MHz using this network with a 0.01µF capacitor and a 2kΩ
resistor in series with a 10µF capacitor. Also, transient
response is improved with higher value output capacitor. The
FN6326.1
April 12, 2007
10
ISL21007
0.01µF value can be increased for better load transient
response with little sacrifice in output stability.
V
= 3.0V
IN
V
10µF
IN
V
O
0.1µF
ISL21007
GND
2kΩ
0.01µF
10µF
FIGURE 28. HANDLING HIGH LOAD CAPACITANCE
Turn-On Time
The ISL21007 devices have low supply current and thus the
time to bias up internal circuitry to final values will be longer
than with higher power references. Normal turn-on time is
typically 120µs. This is shown in Figure 10. Circuit design
must take this into account when looking at power up delays
or sequencing.
Temperature Coefficient
The limits stated for temperature coefficient (tempco) are
governed by the method of measurement. The overwhelming
standard for specifying the temperature drift of a reference is to
measure the reference voltage at two temperatures, take the
total variation, (VHIGH – VLOW), and divide by the temperature
extremes of measurement (THIGH – TLOW). The result is
divided by the nominal reference voltage (at T = +25°C) and
multiplied by 106 to yield ppm/°C. This is the “Box” method for
specifying temperature coefficient.
Output Voltage Adjustment
The output voltage can be adjusted up or down by 2.5% by
placing a potentiometer from Vout to ground, and connecting
the wiper to the TRIM pin. The TRIM input is high impedance,
so no series resistance is needed. The resistor in the
potentiometer should be a low tempco (<50ppm/°C) and the
resulting voltage divider should have very low tempco
<5ppm/°C. A digital potentiometer such as the ISL95810
provides a low tempco resistance and excellent resistor and
tempco matching for trim applications.
FN6326.1
April 12, 2007
11
ISL21007
Typical Application Circuits
V
= +5.0V
IN
R = 200Ω
2N2905
V
IN
V
2.5V/50mA
OUT
ISL21007
V
= 2.50V
OUT
0.001µF
GND
FIGURE 29. PRECISION 2.5V 50mA REFERENCE
+2.7 to 5.5V
0.1µF
10µF
V
IN
V
OUT
ISL21007-25
V
= 2.50V
OUT
GND
0.001µF
V
R
CC
V
H
OUT
X9119
SDA
SCL
(UNBUFFERED)
+
–
2-WIRE BUS
EL8178
V
OUT
(BUFFERED)
V
R
L
SS
FIGURE 30. 2.5V FULL SCALE LOW-DRIFT, LOW NOISE, 10-BIT ADJUSTABLE VOLTAGE SOURCE
FN6326.1
April 12, 2007
12
ISL21007
Typical Application Circuits
10µF
+2.7 to 5.5V
0.1µF
V
2.5V ±2.5%
IN
V
OUT
ISL21007-12
TRIM
GND
R
V
H
CC
SDA
SCL
I2C BUS
ISL95810
R
L
V
SS
FIGURE 31. OUTPUT ADJUSTMENT USING THE TRIM PIN
+2.7 to 5.5V
0.1µF
10µF
V
IN
EL8178
+
–
V
SENSE
OUT
V
OUT
ISL21007-12
GND
LOAD
FIGURE 32. KELVIN SENSED LOAD
FN6326.1
April 12, 2007
13
ISL21007
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6326.1
April 12, 2007
14
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