ISL21007CFB830Z [RENESAS]
Precision, Low Noise FGA™ Voltage References; SOIC8; Temp Range: -40° to 125°C;
| 型号： | ISL21007CFB830Z |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Precision, Low Noise FGA™ Voltage References; SOIC8; Temp Range: -40° to 125°C 光电二极管 |
| 文件： | 总20页 (文件大小：1312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL21007
Precision, Low Noise FGA Voltage References
FN6326
Rev.12.00
Jun 9, 2017
The ISL21007 FGA™ voltage references are extremely low
power, high precision, and low noise voltage references
fabricated on Intersil’s proprietary Floating Gate Analog (FGA)
technology. The ISL21007 features very low noise (4.5µVP-P for
0.1Hz to 10Hz) and very low operating current (150µA, Max). In
addition, the ISL21007 family features guaranteed initial
accuracy as low as ±0.5mV.
Features
• Reference Output Voltage . . . .1.250V, 2.048V, 2.500V, 3.000V
• Input Voltage Range
ISL21007-12, 20, 25. . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
ISL21007-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2V to 5.5V
• Low Output Voltage Noise. . . . . . . . 4.5µVP-P (0.1Hz to 10Hz)
• Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 150µA (Max)
• Temperature Coefficient . . . . . . . . . . . . . . 3ppm/°C (B grade)
• Operating Temperature Range. . . . . . . . . . .-40°C to +125°C
• Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC
• Pb-Free (RoHS Compliant)
This combination of high initial accuracy, low drift, and low
output noise performance of the ISL21007 enables versatile
high performance control and data acquisition applications
with low power consumption.
Applications
• High Resolution A/Ds and D/As
• Digital Meters
Related Literature
• For a full list of related documents, visit our website
- ISL21007 product pages
• Bar Code Scanners
• Base Stations
• Battery Management/Monitoring
• Industrial/Instrumentation Equipment
TABLE 1. AVAILABLE OPTIONS
PART
NUMBER
V
OUT OPTION
INITIAL ACCURACY
(mV)
TEMPCO.
(ppm/°C)
(V)
ISL21007BFB812Z
1.250
±0.5
3
(Obsolete. Recommended replacement part ISL21007CFB812Z)
ISL21007CFB812Z
1.250
1.250
2.048
±1.0
±2.0
±0.5
5
10
3
ISL21007DFB812Z
ISL21007BFB820Z
(Obsolete. Recommended replacement part ISL21007CFB820Z)
ISL21007CFB820Z
2.048
2.048
±1.0
±2.0
5
ISL21007DFB820Z
10
(Obsolete. Recommended replacement ISL21007CFB820Z)
ISL21007BFB825Z
2.500
±0.5
3
(Obsolete. Recommended replacement part ISL21007CFB825Z)
ISL21007CFB825Z
ISL21007DFB825Z
2.500
2.500
3.000
±1.0
±2.0
±0.5
5
10
3
ISL21007BFB830Z
(Obsolete. Recommended replacement ISL21007CFB825Z-TK)
ISL21007CFB830Z
(Obsolete. Recommended replacement ISL21007CFB825Z-TK)
3.000
3.000
±1.0
±2.0
5
ISL21007DFB830Z
10
(Obsolete. Recommended replacement ISL21007CFB825Z-TK)
FN6326 Rev.12.00
Jun 9, 2017
Page 1 of 20
ISL21007
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
VOUT OPTION
(V)
TEMP. RANGE
(°C)
PACKAGE
(RoHS COMPLIANT) PKG. DWG. #
MARKING
21007CF Z12
21007DF Z12
21007CF Z20
21007DF Z20
GRADE
ISL21007CFB812Z
1.250
1.250
2.048
2.048
±1.0mV, 5ppm/°C
±2.0mV, 10ppm/°C
±1.0mV, 5ppm/°C
±2.0mV, 10ppm/°C
-40 to +125 8 Ld SOIC
-40 to +125 8 Ld SOIC
-40 to +125 8 Ld SOIC
-40 to +125 8 Ld SOIC
M8.15
M8.15
M8.15
M8.15
ISL21007DFB812Z
ISL21007CFB820Z
ISL21007DFB820Z (Obsolete
recommended replacement
ISL21007CFB820Z)
ISL21007CFB825Z
ISL21007DFB825Z
21007CF Z25
21007DF Z25
21007CF Z30
2.500
2.500
3.000
±1.0mV, 5ppm/°C
±2.0mV, 10ppm/°C
±1.0mV, 5ppm/°C
-40 to +125 8 Ld SOIC
-40 to +125 8 Ld SOIC
-40 to +125 8 Ld SOIC
M8.15
M8.15
M8.15
ISL21007CFB830Z (Obsolete,
recommended replacement
ISL21007CFB825Z-TK)
ISL21007DFB830Z (Obsolete,
recommended replacement
ISL21007CFB825Z-TK)
21007DF Z30
3.000
±2.0mV, 10ppm/°C
-40 to +125 8 Ld SOIC
M8.15
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for 1k unit tape and reel option. Refer to TB347 for details on reel specifications.
3. For Moisture Sensitivity Level (MSL), see device information pages for ISL21007CFB812, ISL21007CFB820, ISL21007CFB825, ISL21007CFB830,
ISL21007DFB812, ISL21007DFB820, ISL21007DFB825, ISL21007DFB830. For more information on MSL, see techbrief TB363.
Pin Configuration
ISL21007
(8 LD SOIC)
TOP VIEW
GND or NC
VIN
1
2
3
4
8
7
6
5
DNC
DNC
DNC
VOUT
TRIM
GND
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
GND or NC
VIN
Ground or No Connection
Power Supply Input Connection
Ground
2
4
5
GND
TRIM
VOUT
DNC
Allows User Trim VOUT ±2.5%
6
Voltage Reference Output Connection
3, 7, 8
Do Not Connect; Internal Connection - Must Be Left Floating
FN6326 Rev.12.00
Jun 9, 2017
Page 2 of 20
ISL21007
Typical Application Circuit
8
1
GND
NC
+3V
7
6
5
VIN
NC
2
3
4
NC
VOUT
C1
10µF
GND
TRIM
ISL21007-12, 20, 25, 30
SPI BUS
X79000
1
20
CS
SCK
2
19
18
17
16
15
14
13
12
11
CLR
VCC
VH
A0
3
A1
4
A2
5
6
SI
VL
C1
0.001µF
SO
VREF
VSS
VOUT
VBUF
VFB
7
RDY
UP
8
LOW NOISE DAC OUTPUT
9
DOWN
OE
10
FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUBRANGING DAC
FN6326 Rev.12.00
Jun 9, 2017
Page 3 of 20
ISL21007
Absolute Voltage Ratings
Thermal Information
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V
Max Voltage VOUT to GND (10s) . . . . . . . . . . . . . . . . . . . . . -0.5V to VOUT + 1
Voltage on “DNC” pins . . . . . . . . . No connections permitted to these pins.
ESD Rating
Thermal Resistance (Typical, Note 5)
JA (°C/W)
113.12
8 Ld SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Power Dissipation (Note 5). . . . . . . . . . . . . . . . . . . .TA = +70°C
8 Ld SOIC Derate 5.88mW/°C above +70°C. . . . . . . . . . . . . . . . . .471mW
Pb-Free Reflow Profile (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600V
Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Recommended Operating Conditions
Temperature Range (Full Range Industrial) . . . . . . . . . . .-40°C to +125°C
Environmental Operating Conditions
X-Ray Exposure (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mRem
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted,
all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
NOTES:
4. Measured with no filtering, distance of 10” from source, intensity set to 55kV and 70mA current, 30s duration. Other exposure levels should be
analyzed for Output Voltage drift effects. See “Applications Information” on page 16.
5. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See tech brief TB379 for details.
6. Post-reflow drift for the ISL21007 devices will range from 100µV to 1.0mV based on experimental results with devices on FR4 double sided boards.
The design engineer must take this into account when considering the reference voltage after assembly.
Common Electrical Specifications (ISL21007-12, -20, -25, -30) TA = -40°C to +125°C, unless otherwise
specified. Boldface limits apply across the operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
SYMBOL
VOA
CONDITIONS
(Note 10) TYP (Note 10)
UNIT
mV
V
OUT Accuracy at TA = +25°C
ISL21007B
ISL21007C
ISL21007D
ISL21007B
ISL21007C
ISL21007D
-0.5
-1.0
-2.0
+0.5
+1.0
+2.0
3
mV
mV
Output Voltage Temperature
Coefficient (Note 7)
TC VOUT
ppm/°C
ppm/°C
ppm/°C
µA
5
10
Supply Current
IIN
75
±2.5
120
60
150
Trim Range
±2.0
%
Turn-On Settling Time
Ripple Rejection
Output Voltage Noise
Broadband Voltage Noise
Noise Density
tR
VOUT = ±0.1%
f = 10kHz
µs
dB
eN
VN
0.1Hz ≤ f ≤10Hz
10Hz ≤ f ≤1kHz
f = 1kHz
4.5
2.2
60
µVP-P
µVRMS
nV/Hz
FN6326 Rev.12.00
Jun 9, 2017
Page 4 of 20
ISL21007
Electrical Specifications (ISL21007-12, V
= 1.250V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise
OUT
specified. Boldface limits apply across the operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
Input Voltage Range
SYMBOL
VIN
CONDITIONS
(Note 10)
TYP
(Note 10)
UNIT
V
2.7
5.5
Output Voltage
Line Regulation
Load Regulation
VOUT
1.250
100
10
V
VOUT /VIN
VOUT/IOUT
2.7V ≤ VIN ≤ 5.5V
700
100
150
µV/V
µV/mA
µV/mA
mA
Sourcing: 0mA ≤ IOUT ≤ 7mA
Sinking: -7mA ≤ IOUT≤ 0mA
TA = +25°C, VOUT tied to GND
TA = +165°C
20
Short-Circuit Current
ISC
40
Thermal Hysteresis (Note 8)
Long Term Stability (Note 9)
VOUT/TA
VOUT/t
50
ppm
ppm
TA = +25°C
100
Electrical Specifications (ISL21007-20, V
= 2.048V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified.
OUT
Boldface limits apply across the operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
Input Voltage Range
SYMBOL
VIN
CONDITIONS
(Note 10)
TYP
(Note 10)
UNIT
V
2.7
5.5
Output Voltage
Line Regulation
Load Regulation
VOUT
2.048
50
V
VOUT /VIN
VOUT/IOUT
2.7V ≤ VIN ≤ 5.5V
200
100
150
µV/V
µV/mA
µV/mA
mA
Sourcing: 0mA ≤ IOUT ≤ 7mA
Sinking: -7mA ≤ IOUT≤ 0mA
TA = +25°C, VOUT tied to GND
TA = +165°C
10
20
Short-Circuit Current
ISC
50
Thermal Hysteresis (Note 8)
Long Term Stability (Note 9)
VOUT/TA
VOUT/t
50
ppm
ppm
TA = +25°C
75
Electrical Specifications (ISL21007-25, V
= 2.500V) VIN = 3.0V, TA = -40°C to +125°C, unless otherwise specified.
OUT
Boldface limits apply across the operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
Input Voltage Range
SYMBOL
VIN
CONDITIONS
(Note 10)
TYP
(Note 10)
UNIT
V
2.7
5.5
Output Voltage
Line Regulation
Load Regulation
VOUT
2.500
50
V
VOUT /VIN
VOUT/IOUT
2.7V ≤ VIN ≤ 5.5V
200
100
150
µV/V
µV/mA
µV/mA
mA
Sourcing: 0mA ≤ IOUT ≤ 5mA
Sinking: -5mA ≤ IOUT≤ 0mA
TA = +25°C, VOUT tied to GND
TA = +165°C
10
20
Short-Circuit Current
ISC
50
Thermal Hysteresis (Note 8)
Long Term Stability (Note 9)
VOUT/TA
VOUT/t
50
ppm
ppm
TA = +25°C
50
FN6326 Rev.12.00
Jun 9, 2017
Page 5 of 20
ISL21007
Electrical Specifications (ISL21007-30, V
= 3.000V) VIN = 5.0V, TA = -40°C to +125°C, unless otherwise specified.
OUT
Boldface limits apply over the operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
Input Voltage Range
SYMBOL
VIN
CONDITIONS
(Note 10)
TYP
(Note 10)
UNIT
V
3.2
5.5
Output Voltage
Line Regulation
Load Regulation
VOUT
3.000
50
V
VOUT /VIN
VOUT/IOUT
3.2V ≤ VIN ≤ 5.5V
200
100
150
µV/V
µV/mA
µV/mA
mA
Sourcing: 0mA ≤ IOUT ≤ 7mA
Sinking: -7mA ≤ IOUT≤ 0mA
TA = +25°C, VOUT tied to GND
TA = +165°C
10
20
Short-Circuit Current
Thermal Hysteresis (Note 8)
Long Term Stability (Note 9)
NOTES:
ISC
50
VOUT/TA
VOUT/t
50
ppm
ppm
TA = +25°C
50
7. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the
temperature range; in this case, -40°C to +125°C = +165°C.
8. Thermal Hysteresis is the change of VOUT measured at TA = +25°C after temperature cycling over a specified range, TA. VOUT is read initially at
TA = +25°C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25°C. The difference between
the initial VOUT reading and the second VOUT reading is then expressed in ppm. For TA = +165°C, the device under test is cycled from +25°C to
+125°C to -40°C to +25°C.
9. Long term drift is logarithmic in nature and diminishes over time. Drift after the first 1000 hours will be approximately 10ppm/(1kHrs).
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ)
95
90
85
80
75
70
65
60
120
100
80
60
40
20
0
UNIT 3
+125°C
UNIT 2
UNIT 1
+25°C
-40°C
2.5
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
IN
IN
FIGURE 2. IIN vs VIN (3 UNITS)
FIGURE 3. IIN vs VIN OVER TEMPERATURE
1.25015
1.25010
1.25005
1.25000
1.24995
1.24990
1.24985
1.24980
150
100
50
+125°C
UNIT 3
0
+25°C
-40°C
-50
UNIT 2
-100
-150
-200
-250
-300
UNIT 1
2.5
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
IN
IN
FIGURE 5. LINE REGULATION OVER TEMPERATURE
FIGURE 4. LINE REGULATION (3 UNITS)
FN6326 Rev.12.00
Jun 9, 2017
Page 6 of 20
ISL21007
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ) (Continued)
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
1.25010
1.25005
1.25000
1.24995
1.24990
1.24985
1.24980
1.24975
+25°C
+125°C
UNIT 1
UNIT 2
-40°C
UNIT 3
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
-40
-20
0
20
40
60
80
100 120 140
SINKING OUTPUT CURRENT (mA)
SOURCING
TEMPERATURE (°C)
FIGURE 6. LOAD REGULATION OVER TEMPERATURE
FIGURE 7. VOUT vs TEMPERATURE (3 UNITS)
X: 200mV/DIV
Y: 10µs/DIV
0
10nF LOAD
100nF LOAD
-20
V = +0.3V
IN
-40
-60
-80
V = -0.3V
IN
1µF LOAD
1nF LOAD
NO LOAD
1.00E+02
-100
1.00E+00
1.00E+04
1.00E+0
FREQUENCY (Hz)
FIGURE 9. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
FIGURE 8. PSRR vs CAPACITIVE LOADS
X: 20µs/DIV
Y: 1V/DIV
X: 200mV/DIV
Y: 10µs/DIV
V = +0.3V
IN
V
IN
V
= 1.25V
OUT
V = -0.3V
IN
FIGURE 10. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
FIGURE 11. TURN-ON TIME
FN6326 Rev.12.00
Jun 9, 2017
Page 7 of 20
ISL21007
Typical Performance Curves (ISL21007-12) (REXT = 100kΩ) (Continued)
GAIN IS x1000,
NOISE IS 4.5µV
P-P
140
1nF
10nF
NO LOAD
120
100
80
60
40
20
0
100nF
1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06
FREQUENCY (Hz)
FIGURE 13. VOUT NOISE, 0.1Hz TO 10Hz
FIGURE 12. ZOUT vs FREQUENCY
NO OUTPUT CAPACITANCE
X: 50µs/DIV
Y: 1V/DIV
+7mA
-7mA
FIGURE 14. LOAD TRANSIENT RESPONSE
FN6326 Rev.12.00
Jun 9, 2017
Page 8 of 20
ISL21007
Typical Performance Curves (ISL21007-20) (REXT = 100kΩ)
95
95
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
UNIT 2
+125°C
-40°C
UNIT 1
+25°C
UNIT 3
3.5
2.7
3.1
3.5
3.9
V
4.3
(V)
4.7
5.1
5.5
2.7
3.1
3.9
4.3
(V)
4.7
5.1
5.5
V
IN
IN
FIGURE 15. IIN vs VIN (3 UNITS)
FIGURE 16. IIN vs VIN OVER TEMPERATURE
2.04815
2.04810
2.04805
2.04800
2.04795
2.04790
2.04815
2.04810
2.04805
2.04800
2.04795
-40°C
UNIT 2
+125°C
UNIT 1
+25°C
UNIT 3
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
IN
IN
FIGURE 17. LINE REGULATION (3 UNITS)
FIGURE 18. LINE REGULATION OVER TEMPERATURE
2.0496
1.6
1.2
2.0492
2.0488
2.0484
2.0480
2.0476
2.0472
+125°C
0.0
0.4
UNIT 2
UNIT 1
-40°C
0.0
-0.4
-0.8
-1.2
+25°C
UNIT 3
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
SINKING OUTPUT CURRENT (mA)
SOURCING
FIGURE 19. LOAD REGULATION OVER TEMPERATURE
FIGURE 20. VOUT vs TEMPERATURE (3 UNITS)
FN6326 Rev.12.00
Jun 9, 2017
Page 9 of 20
ISL21007
Typical Performance Curves (ISL21007-20) (REXT = 100kΩ) (Continued)
X: 200mV/DIV
Y: 10µs/DIV
0
10nF LOAD
100nF LOAD
-20
V = +0.3V
IN
-40
1µF LOAD
-60
V = -0.3V
IN
-80
NO LOAD
-100
1.0E+01
1.0E+03
1.0E+05
FREQUENCY (Hz)
FIGURE 22. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
FIGURE 21. PSRR vs CAPACITIVE LOADS
X: 200mV/DIV
Y: 10µs/DIV
X: 100µs/DIV
Y: 2V/DIV
V = +0.3V
IN
V
IN
V
OUT = 2.048V
V = -0.3V
IN
FIGURE 23. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
FIGURE 24. TURN-ON TIME
GAIN IS x1000,
NOISE IS 4.5µV
P-P
140
1nF
10nF
NO LOAD
120
100
80
60
40
20
0
100nF
1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06
FREQUENCY (Hz)
FIGURE 25.
ZOUT VS FREQUENCY
FIGURE 26. VOUT NOISE, 0.1Hz TO 10Hz
FN6326 Rev.12.00
Jun 9, 2017
Page 10 of 20
ISL21007
Typical Performance Curves (ISL21007-20) (REXT = 100kΩ) (Continued)
X: 20µs/DIV
X: 20µs/DIV
Y: 200mV/DIV
Y: 200mV/DIV
+7mA
+7mA
-7mA
-7mA
FIGURE 27. LOAD TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
FIGURE 28. LOAD TRANSIENT RESPONSE, NO CAPACITIVE LOAD
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ)
100
120
100
80
60
40
20
0
UNIT 3
95
90
85
80
75
70
65
60
+125°C
UNIT 2
UNIT 1
+25°C
-40°C
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
V
(V)
IN
IN
FIGURE 30. IIN vs VIN OVER TEMPERATURE
FIGURE 29. IIN vs VIN (3 UNITS)
2.5002
2.5001
2.5000
2.4999
2.4998
2.4997
2.4996
100
50
UNIT 1
0
-50
+25°C
UNIT 2
-100
-150
-200
-250
-300
-350
-400
+125°C
UNIT 3
-40°C
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
(V)
5.0
5.5
6.0
V
V
IN
IN
FIGURE 31. LINE REGULATION (3 UNITS)
FIGURE 32. LINE REGULATION OVER TEMPERATURE
FN6326 Rev.12.00
Jun 9, 2017
Page 11 of 20
ISL21007
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ) (Continued)
2.5003
2.5002
2.5001
2.5000
2.4999
2.4998
2.4997
2.4996
2.4995
2.4994
2.4993
0.6
0.4
0.2
0
+125°C
UNIT 2
-40°C
UNIT 1
+25°C
-0.2
-0.4
-0.6
-0.8
-1.0
UNIT 3
80
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
-40
-20
0
20
40
60
100
120 140
SINKING OUTPUT CURRENT (mA)
SOURCING
TEMPERATURE (°C)
FIGURE 33. LOAD REGULATION OVER TEMPERATURE
FIGURE 34. VOUT vs TEMPERATURE (3 UNITS)
X: 200mV/DIV
Y: 10µs/DIV
10
NO LOAD
1nF
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
10nF
100nF
V = +0.3V
IN
1µF
V = -0.3V
IN
1.E+00
1.E+02
1.E+04
1.E+06
FREQUENCY (Hz)
FIGURE 35. PSRR vs CAPACITIVE LOADS
FIGURE 36. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
X: 200mV/DIV
Y: 10µs/DIV
X: 20µs/DIV
Y: 1V/DIV
V = +0.3V
IN
V
IN
V
= 2.5V
V = -0.3V
OUT
IN
FIGURE 37. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
FIGURE 38. TURN-ON TIME
FN6326 Rev.12.00
Jun 9, 2017
Page 12 of 20
ISL21007
Typical Performance Curves (ISL21007-25) (REXT = 100kΩ) (Continued)
GAIN IS x1000,
NOISE IS 4.5µV
P-P
140
1nF
10nF
NO LOAD
120
100
80
60
40
20
0
100nF
1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06
FREQUENCY (Hz)
FIGURE 39. Z
vs FREQUENCY
FIGURE 40. VOUT NOISE, 0.1Hz TO 10Hz
OUT
NO OUTPUT CAPACITANCE
X: 50µs/DIV
Y: 500mV/DIV
+5mA
-5mA
FIGURE 41. LOAD TRANSIENT RESPONSE
Typical Performance Curves (ISL21007-30) (REXT = 100kΩ)
120
120
100
80
60
40
20
0
UNIT 2
+125°C
100
80
60
40
20
0
UNIT 3
UNIT 1
+25°C
-40°C
3.2
3.7
4.2
V
4.7
5.2
3.2
3.7
4.2
4.7
5.2
(V)
V
(V)
IN
IN
FIGURE 42. IIN vs VIN (3 UNITS)
FIGURE 43. IIN vs VIN OVER TEMPERATURE
FN6326 Rev.12.00
Jun 9, 2017
Page 13 of 20
ISL21007
Typical Performance Curves (ISL21007-30) (REXT = 100kΩ) (Continued)
3.001
3.000
2.999
2.998
2.997
2.996
2.995
2.994
3.0005
2.9995
2.9985
2.9975
2.9965
2.9955
UNIT 1
UNIT 2
+125°C
+25°C
UNIT 3
-40°C
3.2
3.6
4.0
4.4
4.8
5.2
5.6
3.2
3.6
4.0
4.4
(V)
4.8
5.2
5.6
V
(V)
IN
V
IN
FIGURE 45. LINE REGULATION OVER TEMPERATURE
FIGURE 44. LINE REGULATION (3 UNITS)
0.10
3.0006
3.0004
0.05
0.00
-40°C
+25°C
3.0002
UNIT 3
3.0000
-0.05
-0.10
-0.15
-0.20
-0.25
UNIT 2
2.9998
+125°C
2.9996
UNIT 1
2.9994
2.9992
2.9990
-7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
SINKING
LOAD (mA)
SOURCING
FIGURE 46. LOAD REGULATION OVER TEMPERATURE
FIGURE 47. VOUT vs TEMPERATURE (3 UNITS)
X: 200mV/DIV
Y: 10µs/DIV
10
NO LOAD
V
V
(DC) = 5.0V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
IN
IN
V = +0.5V
IN
1nF
10nF
100nF
(AC) = 50mV
P-P
1µF
V = -0.5V
IN
1.E+00
1.E+02
1.E+04
1.E+06
FREQUENCY (Hz)
FIGURE 48. PSRR vs CAPACITIVE LOADS
FIGURE 49. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
FN6326 Rev.12.00
Jun 9, 2017
Page 14 of 20
ISL21007
Typical Performance Curves (ISL21007-30) (REXT = 100kΩ) (Continued)
X: 200mV/DIV
Y: 10µs/DIV
V
IN = 5.0V
V = +0.5V
IN
V
= 3.0V
OUT
V = -0.5V
IN
20µs/DIV
FIGURE 50. LINE TRANSIENT RESPONSE, 0.001µF LOAD
CAPACITANCE
FIGURE 51. TURN-ON TIME
GAIN IS x1000,
NOISE IS 4.5µV
P-P
140
120
100
80
1nF
10nF
NO LOAD
100nF
60
40
20
0
1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06
FREQUENCY (Hz)
FIGURE 52. Z
vs FREQUENCY
FIGURE 53. VOUT NOISE, 0.1Hz TO 10Hz
OUT
+7mA
-7mA
100µs/DIV
FIGURE 54. LOAD TRANSIENT RESPONSE
FN6326 Rev.12.00
Jun 9, 2017
Page 15 of 20
ISL21007
Board Assembly Considerations
Applications Information
FGA Technology
FGA references provide high accuracy and low temperature drift
but some PC board assembly precautions are necessary. Normal
Output voltage shifts of 100µV to 1mV can be expected with
Pb-free reflow profiles or wave solder on multi-layer FR4 PC
boards. Precautions should be taken to avoid excessive heat or
extended exposure to high reflow or wave solder temperatures,
this may reduce device initial accuracy.
The ISL21007 voltage reference uses floating gate technology to
create references with very low drift and supply current.
Essentially, the charge stored on a floating gate cell is set
precisely in manufacturing. The reference voltage output itself is
a buffered version of the floating gate voltage. The resulting
reference device has excellent characteristics that are unique in
the industry: very low temperature drift, high initial accuracy, and
almost zero supply current. Also, the reference voltage itself is
not limited by voltage bandgaps or zener settings, so a wide
range of reference voltages can be programmed (standard
voltage settings are provided, but customer-specific voltages are
available).
Post-assembly X-ray inspection may also lead to permanent
changes in device output voltage and should be minimized or
avoided. If X-ray inspection is required, it is advisable to monitor
the reference output voltage to verify excessive shift has not
occurred. If large amounts of shift are observed, it is best to add
an X-ray shield consisting of thin zinc (300µm) sheeting to allow
clear imaging, yet block X-ray energy that affects the FGA
reference.
The process used for these reference devices is a floating gate
CMOS process, and the amplifier circuitry uses CMOS transistors
for amplifier and output transistor circuitry. While providing
excellent accuracy, there are limitations in output noise level and
load regulation due to the MOS device characteristics. These
limitations are addressed with circuit techniques discussed in
other sections.
Special Applications Considerations
In addition to post-assembly examination, there are also other
X-ray sources that may affect the FGA reference long term
accuracy. Airport screening machines contain X-rays and will
have a cumulative effect on the voltage reference output
accuracy. Carry-on luggage screening uses low level X-rays and is
not a major source of output voltage shift, however, if a product is
expected to pass through that type of screening over 100 times,
it may need to consider shielding with copper or aluminum.
Checked luggage X-rays are higher intensity and can cause
output voltage shift in much fewer passes, thus devices expected
to go through those machines should definitely consider
shielding. Note that just two layers of 1/2 ounce copper planes
will reduce the received dose by over 90%. The leadframe for the
device which is on the bottom also provides similar shielding.
Micropower Operation
The ISL21007 consumes extremely low supply current due to the
proprietary FGA technology. Low noise performance is achieved
using optimized biasing techniques. Supply current is typically
75µA and noise is 4.5µVP-P benefitting precision, low noise
portable applications such as handheld meters and instruments.
Data Converters in particular can use the ISL21007 as an
external voltage reference. Low power DAC and ADC circuits will
realize maximum resolution with lowest noise.
If a device is expected to pass through luggage X-ray machines
numerous times, it is advised to mount a 2-layer (minimum) PC
board on the top, along with a ground plane underneath, which will
effectively shield it from 50 to 100 passes through the machine.
Because these machines vary in X-ray dose delivered, it is difficult to
produce an accurate maximum pass recommendation.
Handling and Board Mounting
FGA references provide excellent initial accuracy and low
temperature drift at the expense of very little power drain. There
are some precautions to take to ensure this accuracy is not
compromised. Excessive heat during solder reflow can cause
excessive initial accuracy drift, so the recommended +260°C
max temperature profile should not be exceeded. Expect up to
1mV drift from the solder reflow process.
FGA references are susceptible to excessive X-radiation like that
used in PC board manufacturing. Initial accuracy can change
10mV or more under extreme radiation. If an assembled board
needs to be X-rayed, care should be taken to shield the FGA
reference device.
Board Mounting Considerations
For applications requiring the highest accuracy, board mounting
location should be reviewed. Placing the device in areas subject
to slight twisting can cause degradation of the accuracy of the
reference voltage due to die stresses. It is normally best to place
the device near the edge of a board, or the shortest side, as the
axis of bending is most limited at that location. Obviously,
mounting the device on flexprint or extremely thin PC material
will likewise cause loss of reference accuracy.
FN6326 Rev.12.00
Jun 9, 2017
Page 16 of 20
ISL21007
Noise Performance and Reduction
Temperature Coefficient
The output noise voltage in a 0.1Hz to 10Hz bandwidth is typically
4.5µVP-P. The noise measurement is made with a bandpass filter
made of a 1-pole high-pass filter with a corner frequency at 0.1Hz
and a 2-pole low-pass filter with a corner frequency at 12.6Hz to
create a filter with a 9.9Hz bandwidth. Noise in the 10kHz to 1MHz
bandwidth is approximately 40µVP-P with no capacitance on the
output. This noise measurement is made with a 2 decade
bandpass filter made of a 1-pole high-pass filter with a corner
frequency at 1/10 of the center frequency and 1-pole low-pass
filter with a corner frequency at 10 times the center frequency.
Load capacitance up to 1000pF can be added but will result in
only marginal improvements in output noise and transient
response. The output stage of the ISL21007 is not designed to
drive heavily capacitive loads, so for load capacitances above
0.001µF, the noise reduction network shown in Figure 55 on
page 17 is recommended. This network reduces noise significantly
over the full bandwidth. Noise is reduced to less than 20µVP-P from
1Hz to 1MHz using this network with a 0.01µF capacitor and a 2kΩ
resistor in series with a 10µF capacitor. Also, transient response is
improved with higher value output capacitor. The 0.01µF value can
be increased for better load transient response with little sacrifice
in output stability.
The limits stated for temperature coefficient (tempco) are governed
by the method of measurement. The overwhelming standard for
specifying the temperature drift of a reference is to measure the
reference voltage at two temperatures, take the total variation,
(VHIGH – VLOW), and divide by the temperature extremes of
measurement (THIGH – TLOW). The result is divided by the nominal
reference voltage (at T = +25°C) and multiplied by 106 to yield
ppm/°C. This is the “Box” method for specifying temperature
coefficient.
Output Voltage Adjustment
The output voltage can be adjusted up or down by 2.5% by placing a
potentiometer from VOUT to ground, and connecting the wiper to the
TRIM pin. The TRIM input is high impedance, so no series resistance
is needed. The resistor in the potentiometer should be a low tempco
(<50ppm/°C) and the resulting voltage divider should have very low
tempco <5ppm/°C. A digital potentiometer such as the ISL95810
provides a low tempco resistance and excellent resistor and tempco
matching for trim applications. See Figure 59 and TB473 for further
information.
V
= 5.0V
IN
V
10µF
IN
V
O
Turn-On Time
0.1µF
ISL21007
GND
The ISL21007 devices have low supply current and thus the time
to bias up internal circuitry to final values will be longer than with
higher power references. Normal turn-on time is typically 120µs.
This is shown in Figure 10. Circuit design must take this into
account when looking at power-up delays or sequencing.
2kΩ
0.01µF
10µF
FIGURE 55. HANDLING HIGH LOAD CAPACITANCE
Typical Application Circuits
V
= +5.0V
IN
R = 200Ω
2N2905
V
IN
V
2.5V/50mA
OUT
ISL21007
V
= 2.500V
OUT
0.001µF
GND
FIGURE 56. PRECISION 2.500V 50mA REFERENCE
FN6326 Rev.12.00
Jun 9, 2017
Page 17 of 20
ISL21007
Typical Application Circuits(Continued)
+2.7 TO 5.5V
0.1µF
10µF
V
IN
V
OUT
ISL21007-25
V
= 2.500V
OUT
GND
0.001µF
V
R
CC
V
H
OUT
X9119
SDA
SCL
(UNBUFFERED)
+
–
2-WIRE BUS
EL8178
V
OUT
(BUFFERED)
V
R
L
SS
FIGURE 57. 2.500V FULL SCALE LOW-DRIFT, LOW NOISE, 10-BIT ADJUSTABLE VOLTAGE SOURCE
+2.7 TO 5.5V
0.1µF
10µF
V
IN
EL8178
+
–
V
SENSE
OUT
V
OUT
ISL21007-12
GND
LOAD
FIGURE 58. KELVIN SENSED LOAD
10µF
+2.7 TO 5.5V
0.1µF
V
2.5V ±2.5%
IN
V
OUT
ISL21007-12
TRIM
GND
R
V
H
CC
SDA
SCL
I2C BUS
ISL95810
R
L
V
SS
FIGURE 59. OUTPUT ADJUSTMENT USING THE TRIM PIN
FN6326 Rev.12.00
Jun 9, 2017
Page 18 of 20
ISL21007
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure that you have the latest revision.
DATE
REVISION
CHANGE
Jun 9, 2017
FN6326.12
Applied new header/footer.
Updated Table 1 on page 1.
Updated Related Literature section.
Updated Ordering information table.
Updated Note 2.
Updated About Intersil section.
Sept 2, 2015
FN6326.11
Added Rev History beginning with Revision 11.
Added About Intersil verbiage.
Removed Initial Accuracy from Features on page 1.
Updated Available Options Table on page 1.
Updated Ordering Information on page 2.
Moved Pin Configuration from page 1 to page 3.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary.
You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2007-2017. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6326 Rev.12.00
Jun 9, 2017
Page 19 of 20
ISL21007
For the most recent package outline drawing, see M8.15.
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
AREA
6.20 (0.244)
5.80 (0.228)
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
8°
0°
1
2
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
1
8
SEATING PLANE
0.60 (0.023)
1.27 (0.050)
1.75 (0.069)
5.00 (0.197)
4.80 (0.189)
2
3
7
6
1.35 (0.053)
-C-
4
5
0.25(0.010)
0.10(0.004)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
5.20(0.205)
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs. Mold
flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per
side.
3. Package width does not include interlead flash or protrusions. Interlead flash
and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
FN6326 Rev.12.00
Jun 9, 2017
Page 20 of 20
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