ISL21007CFB830Z [INTERSIL]
5-Channel Integrated LCD Supply; 5通道集成LCD供应
| 型号： | ISL21007CFB830Z |
| 厂家： | 
Intersil |
| 描述： | 5-Channel Integrated LCD Supply |
| 文件： | 总18页 (文件大小：529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL97653A
®
Data Sheet
December 6, 2007
FN6367.0
5-Channel Integrated LCD Supply
Features
The ISL97653A represents a fully integrated supply IC for
LCD-TV applications. With an input operating range of 4V to
14V, both commonly used LCD-TV input supplies, 5V and
• 5V to 14V Input Supply
• Integrated 4.4A Boost Converter
• Integrated V
• Integrated V
Charge Pump and V
Slice Circuit
12V, are supported. An A
supply up to 20V is generated
ON
ON
VDD
by a high-performance PWM BOOST converter with an
integrated 4.4A FET. V is generated using an integrated
Charge Pump Output
OFF
ON
charge pump with on-chip diodes and can be modulated using
an on-chip V slice control circuit. V is generated using
• Integrated 2.5A Buck Converter
• LDO Controller for an Additional Logic Supply
• High Voltage Stress (HVS) Test Mode
• Thermal Shutdown
ON OFF
an integrated charge pump controller. Additionally, the chip
allows for two logic supplies. A buck regulator with an
included 2.5A high side switch is used for the main logic
output and an internal LDO controller can be used to generate
a second logic LDO output.
• 40 Ld QFN (6mmx6mm) Package
• Pb-Free (RoHS Compliant)
To facilitate production test, an integrated HVS circuit is
included which can provide high voltage stress of the LCD
panel.
Applications
• LCD-TVs
An on-board temperature sensor is also provided for system
thermal management control.
• Industrial/Medical LCD Displays
Pinout
The ISL97653A is packaged in a 40 Ld 6mmx6mm QFN
package and is specified for operation over the -40°C to
+105°C temperature range.
ISL97653A
40 LD 6X6 QFN
TOP VIEW
Ordering Information
PART NUMBER
(Note)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
40 39 38 37 36 35 34 33 32 31
ISL97653AIRZ
ISL97653A
40 Ld 6X6 QFN
L40.6X6
L40.6X6
ISL97653AIRZ-T* ISL97653A
40 Ld 6X6 QFN
Tape and Reel
PVIN2
1
2
3
4
5
6
7
8
9
30 COMP
29 FBB
CB
LXL1
LXL2
PGND3
PGND4
CM2
ISL97653AIRZ-TK* ISL97653A
40 Ld 6X6 QFN
Tape and Reel
L40.6X6
28 RSET
*Please refer to TB347 for details on reel specifications.
27
26
25
24
23
22
HVS
EN
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
CDEL
CTL
DRN
COM
FBL
VL
VREF 10
21 POUT
11 12 13 14 15 16 17 18 19 20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL97653A
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Maximum Pin Voltages, all pins except below . . . . . . . . . . . . . . 6.5V
LX1, LX2, SUPP, SUPN, NOUT, PROT, C1N, C2N . . . . . . . . .24V
PVIN1, PVIN2, LXL1, LXL2 . . . . . . . . . . . . . . . . . . . . . . . . . 16.8V
EN, CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V
DRN, POUT, COM, C1P, C2P. . . . . . . . . . . . . . . . . . . . . . . . . .33V
CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21V
Operating Ambient Temperature Range . . . . . . . . -40°C to +105°C
Operating Junction Temperature . . . . . . . . . . . . . . -40°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Input Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . 4V to 14V
Input Capacitance, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2x10µF
IN
Boost Output Voltage Range, A
. . . . . . . . . . . . . . . . . . . . +20V
. . . . . . . . . . . . . . . . . . . . . . . . . .3x22µF
VDD
Output Capacitance, C
OUT
Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH-10µH
V
V
Output Range, V
. . . . . . . . . . . . . . . . . . . . . . +15V to +30V
ON
ON
Output Range, V
. . . . . . . . . . . . . . . . . . . . . . .-15V to -5V
OFF
OFF
Logic Output Voltage Range, V
. . . . . . . . . . . . +1.5V to +3.3V
LOGIC
Buck Inductor, L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH to 10µH
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications
V
= 12V, V
BOOST
= V
= V
= 15V, V
= 25V, V
= -8V, over temperature from -40°C to +105°C,
OFF
IN
SUPN
SUPP
ON
unless otherwise stated.
PARAMETER
SUPPLY PINS
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
V
Supply Voltage
4
14
5
V
mA
mA
kHz
V
IN
I
Quiescent Current
Enabled, no switching
Disabled
4
S
2.7
3.5
F
Switching Frequency
Reference Voltage
580
1.190
1.187
3.4
680
1.215
1.215
3.55
3.0
780
1.240
1.243
3.7
SW
V
T
= +25°C
REF
A
V
VLOR
VLOF
Undervoltage Lockout Threshold
Undervoltage Lockout Threshold
Thermal Shutdown
V
V
rising
falling
V
L
L
2.9
3.2
V
Temperature rising
150
20
°C
°C
Thermal Shutdown Hysteresis
LOGIC SIGNALS HVS, EN, CTL
Logic Input High
2.0
V
V
Logic Input Low
0.4
Pull-down Resistance
HVS, RSET
130
174
200
215
kΩ
RSET
RSET Pull-down Resistance
HVS = HIGH
HVS = LOW, V
Ω
I
RSET Leakage Current
= 1.2V
0.4
12
µA
RSET
RSET
A
BOOST
VDD
DLIM
Min Duty Cycle
8.5
90
%
%
V
Max Duty Cycle
V
Boost Output Range
Boost Efficiency
20
BOOST
EFF
VIN = 12V, V
= 15V
90+
1.215
1.215
%
V
BOOST
BOOST
V
Boost Feedback Voltage
T
= +25°C
1.203
1.198
1.227
1.232
FB
A
V
FN6367.0
December 6, 2007
2
ISL97653A
Electrical Specifications
V
= 12V, V
BOOST
= V
= V
= 15V, V
= 25V, V
= -8V, over temperature from -40°C to +105°C,
OFF
IN
SUPN
SUPP
ON
unless otherwise stated. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
4.4
MAX
4.95
200
0.15
1
UNIT
A
I
Boost FET Current Limit
Switch On Resistance
Line Regulation - Boost
Load Regulation - Boost
3.7
BOOST
R
93
mΩ
%
DSON-BOOST
ΔV
ΔV
/ΔV
BOOST IN
0.08
0.004
/ΔI
BOOST OUT
Load 100mA to 200mA
%
LOGIC BUCK
EFF
Buck Efficiency
VIN = 5V, V
LOGIC
= 3.3V
90+
%
A
BUCK
I
Buck FET Current Limit
Switch On Resistance
Load Regulation - Buck
Feedback Voltage
1.9
4.0
210
1
BUCK
R
150
0.5
mΩ
%
V
DSON-BUCK
ΔV
/ΔI
LDO OUT
Load 100mA to 500mA
= +25°C
V
T
1.195
1.189
1.215
1.215
1.235
1.241
FL
A
V
V
CHARGE PUMP
ON
ILoad_PCP_min
External Load Driving Capability
V
V
= 24V (2X Charge Pump)
= 28V (3X Charge Pump)
40
40
mA
mA
V
ON
ON
V
Feedback Voltage, I
= 1mA
T = +25°C
A
1.195
1.189
1.215
1.215
10
1.235
1.241
17
FBP
ON
V
R
R
(VSUP_SW)
(C1/2-)H
ON Resistance of V
Input Switch
I(switch) = +40mA
I(C1/2-) = +40mA
Ω
ON
SUP
High-Side Driver ON Resistance at
C1- and C2-
30
Ω
ON
R
(C1/2-)L
Low-Side Driver ON Resistance at
C1- and C2-
I(C1/2-) = -40mA
4
10
Ω
ON
V
Load Reg
V
Output Load Regulation
I
= 10mA to 40mA
ON
+1
%
ON
ON
V(diode)
Internal Schottky Diode Forward Voltage I(diode) = +40mA
Drop
700
800
mV
V
CHARGE PUMP
OFF
ILoad_NCP_min
External Load Driving Capability
Feedback Voltage, I = 10mA
SUPN>13.5V VOFF=-8V
= +25°C
100
120
mA
V
V
T
A
0.173
0.171
0.203
0.203
0.233
0.235
10
FBN
OFF
V
R
R
(NOUT)H
(NOUT)L
High-Side Driver ON Resistance at
NOUT
I(NOUT) = +60mA
I(NOUT) = -60mA
Ω
ON
Low-Side Driver ON Resistance at
NOUT
5
Ω
ON
V
Load Reg
V
Output Load Reg
I
= 10mA to 100mA, T = +25°C
2.4
%
OFF
OFF
OFF
A
LDO Controller
I
Sink Current
V
= 1.1V, V
= 10V
12
15
mA
V
DRVP
FBP
LDO_CTL
LDO-FB
Feedback Voltage w/transistor load 1mA T = +25°C
1.191
1.189
1.215
1.215
1.239
1.241
A
V
FAULT DETECTION THRESHOLDS
T_off
Thermal Shut-Down (latched and reset Temperature rising
by power cycle or EN cycle)
150
0.9
°C
V
Vth_A
(FBB)
A
Boost Short Detection
V(FBB) falling less than
VDD
VDD
FN6367.0
December 6, 2007
3
ISL97653A
Electrical Specifications
V
= 12V, V
BOOST
= V
= V
= 15V, V
= 25V, V
= -8V, over temperature from -40°C to +105°C,
OFF
IN
SUPN
SUPP
ON
unless otherwise stated. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
0.9
MAX
UNIT
V
Vth_POUT (FBP)
Vth_NOUT (FBN)
P
Charge Pump Short Detection
Charge Pump Short Detection
V(FBP) falling less than
V(FBN) rising more than
OUT
N
0.4
V
OUT
V
Slice POSITIVE SUPPLY = V(POUT)
ON
I(POUT)_slice
V
Slice Current from POUT Supply CTL = VDD, sequence complete
CTL = AGND, sequence complete
400
150
5
500
200
10
µA
µA
Ω
ON
R
R
(POUT-COM)
(DRN-COM)
ON Resistance between POUT-COM
ON Resistance between DRN-COM
CTL = VDD, sequence complete
CTL = AGND, sequence complete
ON
30
60
Ω
ON
RON_COM
ON Resistance between DRN-COM and
PGND
200
260
400
Ω
PROT
I
PROT Pull-Down Current or Resistance V
> 0.9V
< 0.9V
< 20V
38
500
2
50
760
3
60
1000
4
µA
Ω
PROT_ON
PROT
PROT
PROT
when Enabled by the Start-U
V
I
PROT Pull-Up Current when Disabled
V
mA
PROT_OFF
FN6367.0
December 6, 2007
4
ISL97653A
Typical Application Diagrams
D1
L
L1
VIN
AVDD
M0
6.8µH
C3
22µF
x3
C1
2.2µF
R22 75k
R3
55k
LX1
LX2
FBB
34
C30
Optional
30
32
33
COMP
PGND1
PGND2
35
29
BOOST
R2
0
C2
4.7nF
R21 75k
R4
5k
HVS
27
RSET
28
HVS
EN
26
36
R5 20k
SEQUENCING/FAULT CONTROL
PROT
19
21
SUPP
POUT
C1P
15
C4
VON
220nF
R6
983k
C1N
C2P
16
17
C9
470nF
VON CP
20
FBP
C5
220nF
R8
1k
R7, 50k
C2N
18
CTL
24
25
R10
15
R9
1k
DRN
COM
23
22
C6
0.22µF
CDEL
C22 0.1µF
VON SLICE
PGND5
VL
14
9
R17
100k
12
SUPN
C19
220nF
10
11
VREF
FBN
INTERNAL
REGULATOR
R11 40k
R12
328k
VOFF CP
C7
4.7µF
NOUT
VOFF
13
2
C11
220nF
D2
C12
470nF
PVIN1
PVIN2
38
1
D3
CB
C13
L
1µF
L2
VLOGIC
C0
10µF
CM2
LXL1
LXL2
7
3
4
C8
4.7nF
6.8µH
C14
20µF
R20 10k
D4
BUCK
R13
2k
FBL
8
PGND3
PGND4
5
6
VLOGIC
R14
1.2k VLOGIC2
R17
R15
5.4k
C15
4.7µF
Q1
LDO-CTL
LDO-FB
40
39
LDO CONTROLLER
TEMP SENSOR
R16
5k
AGND
TEMP
31
37
C16
10nF
FN6367.0
December 6, 2007
5
ISL97653A
Typical Application Diagrams (Continued)
RSET HVS
V
PROT
REF
HVS
LOGIC
SAWTOOTH
GENERATOR
CM1
FBB
GM AMPLIFIER
LX1
LX2
SLOPE
COMPENSATION
-
+
BUFFER
V
REF
CONTROL
LOGIC
Ε
UVLO COMPARATOR
-
+
R
SENSE
PGND1
PGND2
CURRENT
AMPLIFIER
0.75 V
REF
680kHz
OSCILLATOR
FREQ
VL
CURRENT LIMIT
COMPARATOR
P
VIN1,2
REGULATOR
REFERENCE BIAS
AND
CDEL
EN
CURRENT LIMIT
THRESHOLD
SEQUENCE CONTROLLER
VL
P
VIN1,2
CB
SUPN
LXL1
LXL2
N
OUT
CONTROL
LOGIC
CURRENT
LIMIT
COMPARATOR
BUFFER
CURRENT AMPLIFIER
CM2
FBL
GM AMPLIFIER
FBN
-
-
+
-
Ε
+
+
V
0.2V
REF
SLOPE
CURRENT LIMIT
THRESHOLD
COMPENSATION
UVLO COMPARATOR
SAWTOOTH
GENERATOR
-
+
0.4V
LDO-CTL
LDO-FB
0.75 V
LDO
CONTROL
LOGIC2
REF
-
+
TEMP
SENSOR
SUPP
TEMP
FBP
-
+
V
REF
P
OUT
SUPP
C1-
C1+
P
C2+ C2-
DRN
CTL
COM
OUT
FN6367.0
December 6, 2007
6
ISL97653A
Typical Performance Curves
0.5
0.4
0.3
100
V
= 8V
IN
90
V
= 12V
IN
V
= 8V
IN
V
= 5V
IN
V
= 5V
IN
0.2
0.1
0.0
80
70
V
= 12V
IN
0
500
1000
1500
0
500
1000
1500
I
(mA)
I
(mA)
O
O
FIGURE 1. BOOST EFFICIENCY
FIGURE 2. BOOST LOAD REGULATION
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
100
90
80
70
60
50
V
= 5V
IN
I
= 100mA
O
V
= 8V
IN
V
= 12V
IN
I
= 400mA
O
0
500
1000
(mA)
1500
2000
5
6
7
8
9
10
11
12
13
14
I
V
(V)
O
IN
FIGURE 3. BOOST LINE REGULATION
FIGURE 4. BUCK EFFICIENCY
0.10
0.08
0.06
0.3
0.2
I
= 400mA
O
0.1
0.0
V
= 5V
IN
0.04
0.02
V
= 12V
IN
I
= 100mA
O
-0.1
-0.2
-0.3
V
= 8V
IN
0.00
5
6
7
8
9
10
(V)
11
12
13
14
0
500
1000
(mA)
1500
2000
V
I
IN
O
FIGURE 5. BUCK LOAD REGULATION
FIGURE 6. BUCK LINE REGULATION
FN6367.0
December 6, 2007
7
ISL97653A
Typical Performance Curves (Continued)
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
0
V
= 25V
-1
-2
-3
-4
-5
ON
V
= 25V
20
ON
0
10
20
30
40
50
60
0
10
30
(mA)
40
50
60
I
I
(mA)
ON
ON
FIGURE 7. VON LOAD REGULATION
FIGURE 8. VOFF LOAD REGULATION
CH1 = A )(500mV/DIV)
(V
VDD BOOST
CH2 = I (BOOST)(200mA/DIV)
O
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
V
= 2.3V
LOGIC
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
(mA)
I
LDO
1ms/DIV
FIGURE 9. LOGIC LDO LOAD REGULATION
FIGURE 10. BOOST TRANSIENT RESPONSE
CH1 = A
CH2 = I (BOOST) (100mA/DIV)
O
(V
) (100mV/DIV)
CH1 = VCTL (5V/DIV)
CH2 = COM (10V/DIV)
VDD BOOST
40µs/DIV
1ms/DIV
FIGURE 11. BUCK TRANSIENT RESPONSE
FIGURE 12. VON SLICE OPERATION
FN6367.0
December 6, 2007
8
ISL97653A
Typical Performance Curves (Continued)
Ch1 = LXL (400ns/DIV)
Ch2 = ILXL (400ns/DIV)
Ch1 = LXL (400ns/DIV)
Ch2 = ILXL (400ns/DIV)
FIGURE 13. BOOST CURRENT LIMIT
FIGURE 14. BUCK CURRENT LIMIT
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
PVIN2
Logic buck supply voltage. This is also the analog supply from which the VL is generated. Needs at
least 1µF bypassing.
2
CB
Logic buck boot strap pin. Generate the gate drive voltage for the N-Channel MOSFET by connecting
a 1µF cap to the switching node LXL1,2.
3, 4
5, 6
7
LXL1, 2
PGND3,4
CM2
Logic buck switching node. Source of the high side internal power N-Channel MOSFET for the Buck.
Logic buck ground pin.
Buck compensation pin. An RC network is recommended. Increase R for better transient response at
the expense of stability.
8
9
FBL
VL
Logic buck feedback pin. High impedance input to regulate at 1.215V.
5.25V internal regulator output. Bypass with a 4.7µF cap. Ref voltage is generated from VL.
10
VREF
Reference voltage output. Bypass with a low valued cap for transients - recommend 220nF. Should not
be greater than 5 times CDEL cap to ensure correct start-up sequence.
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FBN
SUPN
NOUT
PGND5
C1P
Negative charge pump feedback pin. High impedance input to regulate to 0.203V.
Negative charge pump supply voltage. Can be the same as or different from A
Negative charge pump driver output.
VDD.
Charge pump ground pin.
Charge pump capacitor 1, positive connection.
Charge pump capacitor 1, negative connection.
Charge pump capacitor 2, positive connection.
Charge pump capacitor 2, negative connection.
C1N
C2P
C2N
SUPP
FBP
Positive charge pump supply. Can be the same as or different from A
VDD.
Positive charge pump feedback pin. High impedance input to regulate at 1.215V
V charge pump output.
POUT
COM
DRN
ON
High voltage switch control output. V
slice output.
ON
Lower reference voltage for V
slice output. Usually connected to A
.
VDD
ON
CTL
Input control pin for V
ON
slice output.
FN6367.0
December 6, 2007
9
ISL97653A
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
slice control delay input. Minimum 47nF. Recommend 220nF but is only limited by leakage in the
25
CDEL
V
ON
cap reaching µA levels.
26
27
28
29
30
EN
HVS
Chip enable (active high). Can be driven to VIN levels.
High-voltage stress input select pin. High selects high voltage mode.
Voltage set pin for HVS test. RSET connects to ground in the high voltage mode - RSET high.
RSET
FBB
A
boost feedback pin. High impedance input to regulate at 1.215V.
VDD
COMP
Boost compensation network pin. An RC network is recommended. Increase R for better transient
response at the expense of stability. An R = 0Ω is recommended for 4.4A Boost requirements.
31
TEMP
Temperature sensor output voltage. An analog voltage from 0V to 3V for temperatures of -40°C to
+150°C.
32, 33
34, 35
36
PGND1, 2
LX1, 2
Boost ground pins.
Boost switch output. Drain of the internal power NMOS for the Boost.
Gate driver of the Input protection switch. Goes low when EN is high. Can be used to modulate the
PROT
passive input inrush current as shown by R ,R , and C in the typical application diagram.
21 22 30
37
38
AGND
PVIN1
Analog ground. Separate from PGND’s and star under the chip.
Logic buck supply voltage.This is also the analog supply from which the VL is generated. Needs at least
1µF bypassing.
39
40
LDO-FB
LDO controller feedback. High impedance input to regulate at 1.215V.
LDO control pin. Gate drive for the external PNP BJT.
LDO-CTL
FN6367.0
December 6, 2007
10
ISL97653A
Table 1 gives typical values (worst case margins are
considered 10%, 3%, 20%, 10% and 15% on V , V , L,
Application Information
IN
O
A
Boost Converter
VDD
F
and I ):
SW OMAX
The AVDD boost converter features a fully integrated 4.4A
boost FET. The regulator uses a current mode PI control
scheme which provides good line regulation and good
transient response. It can operate in both discontinuous
conduction mode (DCM) at light loads and continuous mode
(CCM). In continuous current mode, current flows
continuously in the inductor during the entire switching cycle
in steady state operation. The voltage conversion ratio in
continuous current mode is given by Equation 1:
TABLE 1. MAXIMUM OUTPUT CURRENT CALCULATION
V
(V)
V
(V)
L
(µH)
I
IN
O
OMAX
(mA)
5
9
6.8
6.8
6.8
6.8
6.8
2215
1673
1344
3254
2670
5
12
15
15
18
5
12
12
V
1
boost
------------------
-------------
=
(EQ. 1)
V
1 – D
IN
Boost Converter Input Capacitor
where D is the duty cycle of the switching MOSFET.
An input capacitor is used to suppress the voltage ripple
injected into the boost converter. A ceramic capacitor with
capacitance larger than 10µF is recommended. The voltage
rating of input capacitor should be larger than the maximum
input voltage. Some capacitors are recommended in Table 2
for input capacitor.
The boost soft-start function is digitally controlled within a
fixed 10ms time frame during which the current limit is
increased in eight linear steps.
The boost converter uses a summing amplifier architecture
for voltage feedback, current feedback, and slope
compensation. A comparator looks at the peak inductor
current cycle by cycle and terminates the PWM cycle if the
current limit is triggered. Since this comparison is cycle
based, the PWM output will be released after the peak
current goes below the current limit threshold.
TABLE 2. BOOST CONVERTER INPUT CAPACITOR
RECOMMENDATION
CAPACITOR
10µF/25V
SIZE
VENDOR
PART NUMBER
C3225X7R1E106M
GRM32DR61E106K
1210 TDK
10µF/25V
1210 Murata
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 60kΩ is recommended.
The boost converter output voltage is determined by
Equation 2:
Boost Inductor
The boost inductor is a critical part which influences the
output voltage ripple, transient response, and efficiency.
Values of 3.3µH to 10µH are recommended to match the
internal slope compensation as well as to maintain a good
transient response performance. The inductor must be able
to handle the average and peak currents expressed in
Equations 5 and 6:
R
+ R
4
R
4
3
--------------------
A
=
× V
VDD
FBB
I
(EQ. 2)
O
-------------
I
I
=
LAVG
(EQ. 5)
(EQ. 6)
1 – D
where R and R are in the “” on page 5. Unless otherwise
3
4
ΔI
L
--------
+
= I
stated, component variables referred to in equations refer to
the Typical Application Diagram.
LPK
LAVG
2
Some inductors are recommended in Table 3.
The current through the MOSFET is limited to 4.4A peak.
This restricts the maximum output current (average) based
on Equation 3:
TABLE 3. BOOST INDUCTOR RECOMMENDATION
DIMENSIONS
ΔI
V
IN
V
O
INDUCTOR
(mm)
VENDOR
PART NUMBER
L
⎛
⎝
⎞
⎠
--------
---------
I
=
I
–
LMT
×
(EQ. 3)
OMAX
2
10µH/
13x13x4.5 TDK
RLF12545T-100M5R1
5.1A
PEAK
Where ΔIL is peak to peak inductor ripple current, and is set
5.9µH/
12.9X12.9X4 Sumida CDEP12D38NP-5R9MB-120
by Equation 4. f is the switching frequency (680kHz).
s
6A
PEAK
V
D
f
S
IN
--------- ----
ΔI
=
×
(EQ. 4)
L
L
FN6367.0
December 6, 2007
11
ISL97653A
Stability can be examined by repeatedly changing the load
between 100mA and a max level that is likely to be used in
the system being used. The A voltage should be
examined with an oscilloscope set to AC 100mV/DIV and the
amount of ringing observed when the load current changes.
Reduce excessive ringing by reducing the value of the
resistor in series with the CM1 pin capacitor.
Rectifier Diode (Boost Converter)
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of
their fast recovery time and low forward voltage. The reverse
voltage rating of this diode should be higher than the
maximum output voltage. The rectifier diode must meet the
output current and peak inductor current requirements. The
following table lists two recommendations for boost
converter diode.
VDD
Cascaded MOSFET Application
A 20V N-Channel MOSFET is integrated in the boost
regulator. For applications requiring output voltages greater
than 20V, an external cascaded MOSFET is needed as
shown in Figure 15. The voltage rating of the external
TABLE 4. BOOST CONVERTER RECTIFIER DIODE
RECOMMENDATION
V /I
R AVG
DIODE
RATING
PACKAGE
VENDOR
Fairchild
MOSFET should be greater than A
.
VDD
FYD0504SA
50V/2A
DPAK
V
Semiconductor
A
IN
VDD
30WQ04FN
40V/3.5A
DPAK
International
Rectifier
LX1, LX2
FBB
Output Capacitor
Integrating output capacitors supply the load directly and
reduce the ripple voltage at the output. Output ripple voltage
consists of two components: the voltage drop due to the
inductor ripple current flowing through the ESR of output
capacitor, and the charging and discharging of the output
capacitor.
INTERSIL
ISL97653A
V
– V
I
O
1
f
s
O
IN
----------------------- --------------- ---
V
= I
× ESR +
LPK
×
×
FIGURE 15. CASCADED MOSFET TOPOLOGY FOR HIGH
OUTPUT VOLTAGE APPLICATIONS
RIPPLE
V
C
(EQ. 7)
O
OUT
For low ESR ceramic capacitors, the output ripple is
V
Protection
IN
dominated by the charging and discharging of the output
capacitor. The voltage rating of the output capacitor should
be greater than the maximum output voltage.
A series external P-FET can be used to prevent passive
power-up inrush current from the Boost output caps charging
to V - V
via the boost inductor and Schottky
IN SCHOTTKY
Note: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across them
diode. This FET also adds protection in the event of a short
circuit on A The gate of the PFET (shown as M0 in the “”
VDD.
increases. C
in Equation 7 assumes the effective value
on page 5) is controlled by PROT. When EN is low, PROT is
pulled internally to PVIN1, thus M0 is switched off. When EN
goes high, PROT is pulled down slowly via a 50µA current
source, switching M0 on.
OUT
of the capacitor at a particular voltage and not the
manufacturer's stated value, measured at zero volts.
Table 5 shows some selections of output capacitors.
If the device is powered up with EN tied to high, M0 will
remain switched off until the voltage on VL exceeds the
VLOR threshold. Once the voltage on PROT falls below 0.6V
and the step-up regulator is within 90% of its target voltage,
PROT is pulled down to ground via a 1.3kΩ impedance. If
TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR
10µF/25V
SIZE
VENDOR
PART NUMBER
C3225X7R1E106M
GRM32DR61E106K
1210 TDK
10µF/25V
1210 Murata
A
falls 10% below regulation, the drive to PROT reverts
VDD
to a 50µA current source. If a timed fault is detected, M0 is
actively switched off.
PI Loop Compensation (Boost Converter)
The boost converter of ISL97653A can be compensated by
a RC network connected from COMP pin to ground.
Several additional external components can optionally be
used to fine-tune the function of pin PROT (shown in the
dashed box near M0 in application diagram). PROT ramp
rate can be controlled by adding a capacitor C30 between
gate and source of M0. M0 gate voltage can be limited
during soft-start by adding a resistor (~75kΩ) between gate
C = 4.7nF and R = 0Ω to 10Ω. A RC network is used in the
2
2
demo board. A higher capacitor value can be used to
increase system stability.
FN6367.0
December 6, 2007
12
ISL97653A
and source of M0. In addition, a resistor can be connected
between PROT and the gate of M0, in order to limit the
Where I is the output current of the buck converter. Table 6
shows some recommendations for input capacitor.
o
maximum V
GS
of M0 at all times.
TABLE 6. INPUT CAPACITOR (BUCK) RECOMMENDATION
Buck Converter
CAPACITOR SIZE
VENDOR
PART NUMBER
C3216X7R1C106M
GRM21BR61A106K
C3225X7R1C226M
The buck converter is a step down converter supplying
power to the logic circuit of the LCD system. The ISL97653A
integrates a high voltage N-channel MOSFET to save cost
and reduce external component count. In the continuous
current mode, the relationship between input voltage and
output voltage as expressed in Equation 8:
10µF/16V
10µF/10V
22µF/16V
1206 TDK
0805 Murata
1210 Murata
Buck Inductor
V
A 3.3µH to 10µH inductor range is recommended for the
buck converter. Besides the inductance, the DC resistance
and the saturation current are also factors that need to be
considered when choosing a buck inductor. Low DC
resistance can help maintain high efficiency. Saturation
current rating should be higher than 2A. Here are some
recommendations for buck inductor.
LOGIC
---------------------
= D
V
(EQ. 8)
IN
Where D is the duty cycle of the switching MOSFET.
Because D is always less than 1, the output voltage of a
buck converter is lower than input voltage.
The peak current limit of buck converter is set to 2.5A, which
restricts the maximum output current (average) based on
Equation 9:
TABLE 7. BUCK INDUCTOR RECOMMENDATION
DIMENSIONS
INDUCTOR
(mm)
VENDOR
PART NUMBER
I
= 2.5A – ΔI
P-P
(EQ. 9)
OMAX
4.7µH/
5.7x5.0x4.7 Murata
LQH55DN4R7M01K
2.7A
PEAK
Where ΔI
is the ripple current in the buck inductor as
P-P
shown in Equation 10:
6.8µH/
7.3x6.8x3.2 TDK
RLF7030T-6R8M2R8
3A
PEAK
V
LOGIC
---------------------
ΔI
=
⋅ (1 – D)
(EQ. 10)
pp
L ⋅ f
s
Rectifier Diode (Buck Converter)
Where L is the buck inductor, f is the switching frequency
s
(680kHz).
A Schottky diode is recommended for fast recovery and low
forward voltage. The reverse voltage rating should be higher
than the maximum input voltage. The peak current rating is
2.5A, and the average current is given by Equation 13:
Feedback Resistors
The buck converter output voltage is determined by
Equation 11:
I
= (1 – D)*I
o
avg
(EQ. 13)
R
+ R
13
14
--------------------------
V
=
× V
Where I is the output current of buck converter. The
o
following table shows some diode recommended.
LOGIC
FBL
R
(EQ. 11)
14
TABLE 8. BUCK RECTIFIER DIODE RECOMMENDATION
Where R and R are the feedback resistors in the buck
13 14
converter loop to set the output voltage Current drawn by
the resistor network should be limited to maintain the overall
converter efficiency. The maximum value of the resistor
network is limited by the feedback input bias current and the
potential for noise being coupled into the feedback pin. A
resistor network in the order of 1kΩ is recommended.
V /I
RATING
R AVG
DIODE
PACKAGE
VENDOR
PMEG2020EJ
20V/2A
SOD323F Philips
Semiconductors
Fairchild
SS22
20V/2A
SMB
Semiconductor
Buck Converter Input Capacitor
Input capacitance should support the maximum AC RMS
current which occurs at D = 0.5 and maximum output
current.
I
(C ) = D ⋅ (1 – D) ⋅ I
O
(EQ. 12)
acrms IN
FN6367.0
December 6, 2007
13
ISL97653A
Output Capacitor (Buck Converter)
Positive Charge Pump Design Consideration
Four 10µF or two 22µF ceramic capacitors are recommended
for this part. The overshoot and undershoot will be reduced
with more capacitance, but the recovery time will be longer.
All positive charge pump diodes (D1, D2 and D3 shown in
the “NEGATIVE CHARGE PUMP BLOCK DIAGRAM” on
page 16) for x2 (doubler) and x3 (Tripler) modes of operation
are included in the ISL97653A. During the chip start-up
sequence the mode of operation is automatically detected
TABLE 9. BUCK OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR
10µF/6.3V
10µF/6.3V
22µF/6.3V
100µF/6.3V
SIZE
0805
0805
1210
1206
VENDOR
TDK
PART NUMBER
C2012X5R0J106M
GRM21BR60J106K
C3216X5R0J226M
GRM31CR60J107M
when the charge pump is enabled. With both C and C
present, the x3 mode of operation is detected. With C
7
7
8
present, C open and with C + shorted to C +, the x2 mode
8
1
2
Murata
TDK
of operation will be detected.
Internal switches M1, M2 and M3 isolate P
from SUPP
OUT
Murata
until the charge pump is enabled. This is important for TFT
applications that require the negative charge pump output
PI Loop Compensation (Buck Converter)
(V
) and A
VDD
supplies to be established prior to P
.
OFF
OUT
The buck converter of ISL97653A can be compensated by a
The maximum P
from the following equations assuming a 50% switching
duty:
charge pump current can be estimated
OUT
RC network connected from CM2 pin to ground. C = 4.7nF
8
and R = 10k RC network is used in the demo board. A
20
larger value resistor can lower the transient overshoot,
however, at the expense of stability of the loop.
I
(2x) ∼ min of 40mA or
MAX
2 • V
– 2 • V
(2 • I
) – V(V
)
ON
The stability can be optimized in a similar manner to that
described in “PI Loop Compensation (Boost Converter)” on
page 12.
SUPP
DIODE
MAX
--------------------------------------------------------------------------------------------------------------------------
• 0.95A
(2 • (2 • R
+ R
))
ONL
ONH
I
(3x) ∼ min of 40mA or
Bootstrap Capacitor (C
13
)
MAX
This capacitor provides the supply to the high driver circuitry
for the buck MOSFET. The bootstrap supply is formed by an
internal diode and capacitor combination. A 1µF is
recommended for ISL97653A. A low value capacitor can
lead to overcharging and in turn damage the part.
3 • V
– 3 • V
(2 • I
) – V(V
)
ON
·
DIODE
MAX
SUPP
--------------------------------------------------------------------------------------------------------------------------
• 0.95V
(EQ. 14)
(2 • (3 • R + 2 • R ))
ONH
ONL
Note: V
DIODE
function of I
(2 • I
) is the on-chip diode voltage as a
and V (40mA) < 0.7V.
DIODE
MAX
MAX
During very light loads, the on-time of the low side diode
may be insufficient to replenish the bootstrap capacitor
voltage. Additionally, if V - V
< 1.5V, the internal
IN BUCK
MOSFET pull-up device may be unable to turn-on until
falls. Hence, there is a minimum load requirement in
V
LOGIC
this case. The minimum load can be adjusted by the
feedback resistors to FBL.
Charge Pump Controllers (V
and V
)
OFF
ON
The ISL97653A includes 2 independent charge pumps (see
charge pump block and connection diagram). The negative
charge pump inverts the SUPN voltage and provides a
regulated negative output voltage. The positive charge pump
doubles or triples the SUPP voltage and provides a
regulated positive output voltage. The regulation of both the
negative and positive charge pumps is controlled by internal
comparators that sense the output voltage. These sensed
voltages are then compared to scaled internal reference
voltages.
Charge pumps use pulse width modulation to adjust the
pump period, depending on the load present. The pumps
can provide 100mA for V
OFF
and 40mA for V .
ON
FN6367.0
December 6, 2007
14
ISL97653A
External Connections
and Components
SUPP
M2
x2 Mode
x3 Mode
Both
C1-
C7
M4
C1+
SUPP
M1
Control
D3
D2
D1
POUT
680KHz
0.9V
C14
SUPP
C2+
C2-
Error
FB
M3
C8
V
REF
R8
C21
M5
FBP
C22
R9
FIGURE 16. V
FUNCTION DIAGRAM
ON
In voltage doubler configuration, the maximum V
given by the following equation:
is as
The maximum V
pump is:
output voltage of a single stage charge
OFF
ON
V
= 2 • (V
– V
) – 2 • I
• (2 • R
+ R
)
ONL
V
(2x) = – V
+ V
+ 2 • I
DIODE OUT
ON_MAX(2x)
SUPP
DIODE
OUT
ONH
OFF_MAX
SUPP
(EQ. 15)
• (R (NOUT)H + R
(NOUT)L)
ON
ON
(EQ. 18)
For Voltage Tripler:
R and R in the Typical Application Diagram determine
6
7
V
= 3 • (V
– V
)– 2 • I
• (3 • R
+ 2 • R
ONH ONL
ON_MAX(3x)
SUPP
DIODE
OUT
V
output voltage.
OFF
(EQ. 16)
R7
R6
R7
R6
⎛
⎞
⎠
⎛
⎝
⎞
⎠
-------
-------
V
= V
• 1 +
– V •
REF
OFF
FBN
⎝
(EQ. 19)
V
output voltage is determined by the following equation:
ON
R
⎛
⎞
⎟
⎠
8
*Although in the given typical application diagram, SUPP and SUPN are
connected to A , depending on a specific application, SUPN and/or SUPP
------
V
= V
• 1 +
⎜
ON
FBP
R
9
(EQ. 17)
VDD
could be connected to either A
⎝
or V
VDD
IN.
Negative Charge Pump Design Consideration
The negative charge pump consists of an internal switcher
M1, M2 which drives external steering diodes D2 and D3 via
a pump capacitor (C ) to generate the negative V
12
OFF
supply. An internal comparator (A1) senses the feedback
voltage on FBN and turns on M1 for a period up to half a
CLK period to maintain V
in regulated operation at
(FBN)
0.2V. External feedback resistor R is referenced to V
.
6
REF
Faults on V
which cause V
FBN
to rise to more than 0.4V,
OFF
are detected by comparator (A2) and cause the fault
detection system to start the internal fault timer which will
cause the chip to power down if the fault persists.
FN6367.0
December 6, 2007
15
ISL97653A
V
C19
REF
100pF
SUPN
VDD
A2
FAULT
C20
820pF
R6
40k
0.4V
FBN
A1
R7
328k
0.2V
1.2MHz
STOP
M2
M1
CLK
C12
220nF
D2
NOUT
PGND
V
(-8V)
OFF
C13
470nF
D3
PWM
CONTROL
EN
FIGURE 17. NEGATIVE CHARGE PUMP BLOCK DIAGRAM
V
Slice Circuit
V
LDO
LOGIC2
ON
The V
slice circuit functions as a three way multiplexer,
An LDO controller is also integrated to provide a second
logic supply. The LDO-CTL pin drives the base of an
external transistor which should be sized for the current
required. A resistor divider is used to set the output voltage
by feeding back a reference voltage to LDO-FB. The internal
feedback reference is 1.215V.
ON
switching the voltage on COM between ground, DRN and
POUT, under control of the start-up sequence and the CTL pin.
During the start-up sequence, COM is pulled to ground via
an NDMOS FET with R
of 260 ohms. After the start-up
DS(on)
sequence has completed, CTL is enabled and acts as a
multiplexer control such that if CTL is low, COM connects to
DRN through a 30Ω internal MOSFET, and if CTL is high,
HVS Operation
When the HVS input is taken high, the ISL97653A enters
COM connects to P
internally via a 5Ω MOSFET.
OUT
HVS test mode. In this mode, the output of A
is
VDD
increased by switching RSET to ground, and the AVDD is
set to:
The slew rate of the switch control circuit is mainly restricted
by the load capacitance at COM pin and is given by
Equation 20:
V
R
+ R
x
R
x
3
--------------------
A
=
× V
VDD
FBB
(EQ. 22)
ΔV
g
-------
------------------------------------
=
(EQ. 20)
||
(R R ) × C
L
Δt
i
L
Where R is the value of R in parallel with R . AVDD
x
4
5
Where V is the supply voltage applied to DRN or voltage at
voltage higher than the maximum rating of the boost
MOSFET may damage the part.
g
P
, which range is from 0V to 30V. Ri is the resistance
OUT
between COM and DRN or P
including the internal
OUT
Fault Protection
MOSFET r
, the trace resistance and the resistor
DS(on)
inserted, R is the load resistance of VON slice circuit, and
The ISL97653A incorporates a number of fault protection
schemes. AVDD, VON, and VOFF are constantly monitored.
If fault conditions are detected for longer than 1ms on these
FB inputs, the device stops switching and the outputs are
disconnected. The ISL97653A also integrates over temp and
over current protection.
L
C is the load capacitance of switch control circuit.
L
In the Typical Application Circuit, R , R and C give the
22
bias to DRN based on Equation 21:
8
9
V
⋅ R +AVDD ⋅ R
9 8
ON
---------------------------------------------------------
=
V
(EQ. 21)
DRN
R
+ R
9
8
Supply Sequencing
When the input voltage V is higher than 4V(UVLO), V
IN
,
REF
And R can be adjusted to adjust the slew rate.
10
V
and V
are turned on. V
has a 9ms
LOGIC,
LOGIC2
LOGIC
fixed soft-start at start-up. A , V , and V
VDD ON
are
OFF
dependant on the EN pin.
FN6367.0
December 6, 2007
16
ISL97653A
When EN is taken high, voltage of pin PROT and V
start
Fault Sequencing
OFF
ramping down. Once the PROT voltage falls below 0.9V,
VDD starts up with a 9ms fixed soft-start time. Please note if
is to start earlier than AVDD, then the SUPN needs to
The ISL97653A has advanced overall fault detection
systems including Over Current Protection (OCP) for both
boost and buck converters, Under Voltage Lockout
Protection (UVLP) and Over-Temperature Protection.
A
V
OFF
connect to Vin, and Vin voltage should be larger than V
OFF
and AVDD can be
absolute value. The delay between V
OFF
Once the peak current flowing through the switching
MOSFET of the boost and buck converters triggers the
current limit threshold, the PWM comparator will disable the
output, cycle by cycle, until the current is back to normal.
controlled by C30 in the typical application diagram and is
given by Equation 23:
T
= (V – 0.9V) × C ⁄ (50μA)
IN 30
DELAY
(EQ. 23)
The successful completion of the A
VDD
soft-start cycle
begins to ramp up
Layout Recommendation
triggers two simultaneous events. V
ON
and the voltage on CDEL starts ramping up. When the
The device's performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
voltage reaches 1.215V, V
slice starts.
ON
There are some general guidelines for layout:
VIN
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
VREF
VLOGIC
EN
PROT
AVDD
0.9V
2. Place V
and V bypass capacitors close to the pins.
L
REF
3. Reduce the loop with large AC amplitudes and fast slew
rate.
VON
VOFF
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
2.8V
1.215V
CDEL
VON Slice
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point.
* For demonstration only, not to scale
FIGURE 18.
6. The exposed die plate, on the underneath of the
package, should be soldered to an equivalent area of
metal on the PCB. This contact area should have multiple
via connections to the back of the PCB as well as
connections to intermediate PCB layers, if available, to
maximize thermal dissipation away from the IC.
Temperature Sensor
The ISL97653A also includes a temperature output for use
in system thermal management control. The integrated
sensor measures the die temperature over the -40°C to
+150°C range. Output is in the form of an analog voltage on
the TEMP pin in the range of 0V to 3V, which is proportional
to the sensed die temperature. Temperature accuracy is
±8.5°C over the -40°C to +150°C temperature range.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track
and ground plane area connected to the exposed die
plate should be maximized and spread out as far as
possible from the IC. The bottom and top PCB areas
especially should be maximized to allow thermal
dissipation to the surrounding air.
The device should be disabled by the user when the TEMP
pin output reaches 3V ( = +150°C die junction). Operation of
the device between +125°C and +150°C can be tolerated for
short periods, however in order to maximize the life of the IC,
it is recommended that the effective continuous operating
junction temperature of the die should not exceed +125°C.
8. Minimize feedback input track lengths to avoid switching
noise pick-up.
A demo board is available to illustrate the proper layout
implementation.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6367.0
December 6, 2007
17
ISL97653A
Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 10/06
4X
4.5
6.00
0.50
36X
A
6
B
31
40
PIN #1 INDEX AREA
6
30
1
PIN 1
INDEX AREA
4 . 10 ± 0 . 15
21
10
(4X)
0.15
11
20
0.10 M C A B
TOP VIEW
40X 0 . 4 ± 0 . 1
4
0 . 23 +0 . 07 / -0 . 05
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
0 . 90 ± 0 . 1
BASE PLANE
( 5 . 8 TYP )
(
SEATING PLANE
0.08 C
SIDE VIEW
4 . 10 )
( 36X 0 . 5 )
5
C
0 . 2 REF
( 40X 0 . 23 )
( 40X 0 . 6 )
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6367.0
December 6, 2007
18
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