ISL14011 [INTERSIL]
Low Jitter Clock Generators for Set-Top Box; 低抖动时钟发生器用于机顶盒
| 型号： | ISL14011 |
| 厂家： | 
Intersil |
| 描述： | Low Jitter Clock Generators for Set-Top Box |
| 文件： | 总5页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL14011
®
Data Sheet
January 30, 2007
FN6427.0
Low Jitter Clock Generators for Set-Top
Box
Features
• LVTTL Outputs
The ISL14011 series of devices are general purpose
integrated Clock Synthesizers and Generators suited for
consumer applications such as Set-top Box, and various
other consumer applications.
• Selectable Crystal or Ref. Clock for Inputs
• Period Jitter ~50ps RMS
• Single Supply; 3.3V nominal
The selectable reference input accepts 30MHz signal either
from crystal or an external source. It is specified to operate
with a nominal 3.3V supply and is offered in 16 Ld QFN
package.
• Extended Temperature Range: -40°C to +85°C
• Available in small foot print package
- 16 Ld QFN 3mmx3mm
• Pb-Free plus anneal available (RoHS Compliant)
Contact Factory for other output frequency options.
Applications
Ordering Information
• Set-Top Boxes
PART
PART
TEMP.
PKG.
NUMBER
MARKING RANGE (°C) PACKAGE DWG. #
Pinout
ISL14011IRZ* 11IZ
-40 to +85 16 Ld QFN L16.3x3
ISL14011
(16 LD QFN)
TOP VIEW
*Add "-T" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
16 15 14 13
VCC
X1
1
2
3
4
12 NC
11 CLK3
Selection Table
10
9
X2
CLK2
NC
NUMBER
PART
INPUT
OF
OUTPUT
GND
OPTIONS FREQUENCY OUTPUTS FREQUENCY PACKAGE
5
6
7
8
ISL14011 30MHz 4 LVTTL 25, 30, 24, 27 16 Ld QFN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL14011
Functional Block Diagram
CLK1
CLK2
M1
PHASE FREQ DET.
VCO1
OSC.
30MHz
CRYSTAL
N1
CLK3
CLK4
M2
PHASE FREQ DET.
VCO2
N2
Pin Description
16 LD QFN
SYMBOLS
VCC
X1
PIN DESCRIPTION
1,14,16
Supply Voltage
2
The X1 pin is the terminal 1 of an external 30MHz crystal. This pin is grounded for external CK input.
3
X2
The X2 pin is the terminal 2 of external 30MHz crystal, or external clock input.
4, 5, 7
GND
CLK1
CLK2
CLK3
CLK4
NC
Ground
8
10
CLK1 Output: 25MHz
CLK2 Output: 30MHz
CLK3 Output: 24MHz
CLK4 Output: 27MHz
No Connect
11
13
6, 9,12,15
FN6427.0
January 30, 2007
2
ISL14011
Absolute Maximum Ratings
Thermal Information
Voltage on VCC, CLK pins (respect to Gnd) . . . . . . . . -0.3V to 4.0V
Voltage on X1, X2 pins (respect to Gnd) . . . . . . . . . . . -0.3V to 2.5V
ESD Rating
MIL STD-883, Method 3014. . . . . . . . . . . . . . . . . . . . . . . . .>±5kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
Thermal Resistance (Typical, Note 1)
16 Ld QFN Package. . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65ºC to +150ºC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300ºC
θ
(°C/W)
59
θ
(°C/W)
JA
JC
11.5
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
DC Electrical Specifications
V
= 3.3V ±10%, T = -40ºC to +85ºC, Typical values are at T = +25ºC and V
= 3.3V,
CC
A
A
CC
Unless otherwise noted
SYMBOL
Supply Voltage
SYMBOL
CONDITIONS
Supply Voltage
Supply Current CL = 5pF on all outputs
MIN
TYP
3.3
11
MAX
3.6
UNIT
V
V
3.0
CC
Supply Current
I
15
mA
CC
CLOCK INPUT X (X GROUNDED) FOR EXTERNAL CLOCK MODE
2
1
Input High Level
Input Level Low
Input Current
V
1.5
2.4
0.5
V
V
IH
V
IL
IIL, IIH
V
to Ground
0.5
mA
X2
CLOCK OUTPUTS (CLK)
Output High Level
V
I
I
I
I
I
I
= -100µA
= -4mA
= -6mA
= 100µA
= 4mA
V
-0.2
V
V
OH
OH
OH
OH
OL
OL
OL
CC
2.4
2.1
V
Output Low Level
V
0.2
0.4
0.75
30
V
OL
V
= 6mA
V
Output Short Circuit Current
IOSC
CLK = V
or Gnd
6
13
mA
CC
AC Electrical Specifications CL= 5pF on all outputs
SYMBOL
Crystal Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
fin
30
MHz
CLOCK OUTPUTS
Rise Time
t
20% to 80% V
1.8
1.8
ns
ns
%
R
CC
CC
Fall Time
t
80% to 20% V
F
Duty Cycle
40
60
Period Jitter
Power Up Time
J
RMS
50
2
ps
ms
P
t
V
>2.7V
CC
PO
FN6427.0
January 30, 2007
3
ISL14011
Typical Performance Curves (Period Jitter)
70
65
60
55
50
45
40
35
30
25
20
V
= 3.3V
SUPPLY
TEMPERATURE +23ºC
CK1
CK2
CK4
CK3
0
2
4
6
8
10
12
14
LOAD CAPACITANCE (pF)
FIGURE 1. STANDARD DEVIATION vs LOAD CAPACITANCE
FN6427.0
January 30, 2007
4
ISL14011
Quad Flat No-Lead Plastic Package (QFN)
L16.3x3
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Micro Lead Frame Plastic Package (MLFP)
2X
MILLIMETERS
0.15
C A
D
A
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
9
D/2
A
A1
A2
A3
b
0.80
0.90
-
D1
-
-
-
-
-
9
D1/2
2X
N
0.15
C B
0.20 REF
9
6
INDEX
AREA
0.18
1.35
1.35
0.23
0.30
1.65
1.65
5, 8
1
2
3
E1/2
E/2
9
D
3.00 BSC
-
E1
E
D1
D2
E
2.75 BSC
9
1.50
7, 8, 10
2X
3.00 BSC
-
0.15
C
B
B
2X
E1
E2
e
2.75 BSC
9
TOP VIEW
0.15
4X
C
0
A
1.50
7, 8, 10
A2
0.50 BSC
-
A
/ /
0.10
C
C
C
k
0.20
0.30
-
0.40
16
4
-
-
0.08
L
0.50
8
SEATING PLANE
A3 A1
SIDE VIEW
N
2
9
Nd
Ne
P
3
5
NX b
4
3
0.10 M C A B
4X P
-
-
-
0.60
12
9
D2
D2
8
7
NX k
θ
-
9
(DATUM B)
2
N
Rev. 1 6/04
4X P
NOTES:
1
(DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
2
3
(Ne-1)Xe
REF.
E2
6
INDEX
AREA
7
8
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
NX L
8
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
N
e
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
BOTTOM VIEW
A1
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
NX b
5
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
SECTION "C-C"
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
C
L
C
L
10. Compliant to JEDEC MO-220VEED-2 Issue C, except for the E2
and D2 MAX dimension.
L
L
10
10
L1
L1
e
e
C
C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6427.0
January 30, 2007
5
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