ISL15102 [RENESAS]
Line Driver;
| 型号： | ISL15102 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Line Driver 驱动 接口集成电路 |
| 文件： | 总16页 (文件大小：898K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL15102
Single Port, PLC Differential Line Driver
FN8823
Rev.1.00
May 3, 2018
The ISL15102 is a single port differential line driver
developed for Power Line Communication (PLC)
applications. The device is designed to drive heavy line
loads while maintaining a high level of linearity required
in Orthogonal Frequency Division Multiplexing (OFDM)
PLC modem links.
Features
• Single differential driver
• Internal V
CM
• 90MHz signal bandwidth
• 900V/µs slew rate
The ISL15102 has a disable control pin (DIS). In Disable
mode, the line driver goes into Low Power mode and the
outputs maintain a high impedance in the presence of
high receive signal amplitude, improving TDM receive
signal integrity.
• Single +8V to +28V supply, absolute maximum 30V
• Supports narrowband and broadband DMT PLC
• -86dB THD at 200kHz in to 50Ω line load
• -70dB THD at 3MHz in to 50Ω line load
• Control pin for enable/disable for TDM operation
• Thermal shutdown
The ISL15102 has built-in thermal protection. When the
internal temperature reaches +150°C (typical) the driver
shuts down to prevent damage to the device.
An internal input CM buffer maximizes the dynamic
range and reduces the number of external components in
the application circuit.
Applications
• Power line communication differential driver
The ISL15102 is supplied in a thermally-enhanced small
footprint (4mmx5mm) 24 Ld QFN package. The
ISL15102 is specified for operation across the -40°C to
+85°C operating ambient temperature range.
Table 1. Alternate Solutions
Nominal ±V
(V)
Bandwidth
(MHz)
S
Part #
ISL15100
ISL1571
ISL15110
Applications
Broadband PLC
Broadband PLC
MIMO PLC
±6, +12
±6, +12
±6, +12
180
250
120
Related Literature
For a full list of related documents, visit our website
• ISL15102 product page
+12V
ISL15102
VS+
+12V
A = 10
100nF
VINA+
R
S
+
-
100nF
2.49
INA
VOUTA
CM Buffer
50
Vs
R
F
4.22k
VINA-
3k
3k
100k
100k
1:1
100
VCM
50
R
G
R
L
AFE
Line
931
100nF
VINB-
+12V
R
F
100nF
4.22k
-
VOUTB
100nF
VINB+
INB
+
R
S
2.49
50
Bias Current
Control
Thermal
Shutdown
GND
DIS
Figure 1. Typical Application Circuit
FN8823 Rev.1.00
May 3, 2018
Page 1 of 16
ISL15102
1. Overview
1. Overview
1.1
Ordering Information
Part Number
(Notes 2, 3)
Part
Marking
Operating Ambient
Temp Range (°C)
Tape and Reel
(Units) (Note 1)
Package
(RoHS Compliant)
Pkg.
Dwg. #
ISL15102IRZ
15102IRZ
15102IRZ
-40 to +85
-40 to +85
-
24 Ld QFN
24 Ld QFN
L24.4x5F
L24.4x5F
ISL15102IRZ-T13
ISL15102IRZ-EVALZ
Notes:
2.5k
1. Refer to TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL15102 product information page. For more information about MSL, refer to
TB363.
1.2
Pin Configuration
ISL15102
(24 Ld QFN)
Internal View
Top View
VINA+
VINB+
NC
1
2
3
4
5
6
7
19 VINA-
18 VINB-
17 VOUTB
16 NC
VINA+
VINB+
NC
1
2
3
4
5
6
7
19 VINA-
18 VINB-
17 VOUTB
+
-
-
+
THERMAL
PAD
NC
NC
16
NC
VCM
NC
15 NC
VCM
NC
15 NC
14 NC
13 NC
14 NC
NC
13 NC
NC
FN8823 Rev.1.00
May 3, 2018
Page 2 of 16
ISL15102
1. Overview
1.3
Pin Descriptions
Pin Number
Pin Name
VINA+
VINB+
NC
Function
Amplifier A non-inverting input
Amplifier B non-inverting input
No internal connection
Circuit
Refer to Circuit 1
Refer to Circuit 1
1
2
3, 4, 6, 7, 8, 9, 12, 13,
14, 15, 16, 24
10, 22
5
GND
VCM
Ground connection
Output common-mode bias
Positive supply voltage
Amplifier B output
11, 21
17
VS+
VOUTB
VINB-
Refer to Circuit 2
Refer to Circuit 3
Refer to Circuit 3
Refer to Circuit 2
18
Amplifier B inverting input
Amplifier A inverting input
Amplifier A output
19
VINA-
20
VOUTA
DIS
23
Disable control pin
-
Thermal Pad
Connects to GND
V +
S
V +
S
V +
S
V +
S
GND
GND
GND
GND
Circuit 1
Circuit 2
Circuit 3
FN8823 Rev.1.00
May 3, 2018
Page 3 of 16
ISL15102
2. Specifications
2. Specifications
2.1
Absolute Maximum Ratings
T
= +25°C
A
Parameter
Minimum
-0.3
Maximum
30
Unit
V
V + Voltage to GND
S
Driver V + Voltage
IN
GND
V +
S
V
DIS Voltage to GND
-0.3
6
V
V
Voltage to GND
GND
V +
S
CM
ESD Rating
Value
2
Unit
kV
V
Human Body Model (Tested per JS-001-2014)
Charged Device Model (Tested per JS-002-2014)
750
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may
adversely impact product reliability and result in failures not covered by warranty.
2.2
Thermal Information
Thermal Resistance (Typical)
(°C/W)
(°C/W)
JC
JA
24 Ld QFN Package (Notes 4, 5)
Notes:
38
4
4. is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach”
JA
features. See TB379.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Parameter
Storage Temperature Range
Minimum
Maximum
+150
Unit
-65
°C
Power Dissipation
See Figure 14 on page 9
Refer to TB493
Pb-Free Reflow Profile
2.3
Recommended Operation Conditions
Parameter
Minimum
-40
Maximum
+85
Unit
°C
Temperature Range
Junction Temperature
-40
+150
°C
FN8823 Rev.1.00
May 3, 2018
Page 4 of 16
ISL15102
2. Specifications
2.4
Electrical Specifications
Unless otherwise noted, all tests are at the specified temperature T = +25°C, V + = +12V, A = 10V/V, R = 4.22kΩ, R = 50Ω
A
S
V
F
L
differential, DIS = 0V.
Min
Typ
Max
Parameter
Symbol
BW
Test Conditions
(Note 6) (Note 7) (Note 6) Unit
AC Performance
-3dB Small Signal Bandwidth
-3dB Large Signal Bandwidth
20% to 80%
V
V
V
V
< 2V
90
60
MHz
MHz
V/µs
dBc
O
O
O
P-P-DIFF
= 10V
P-P-DIFF
P-P-DIFF
SR
= 10V
900
-88
200kHz Harmonic Distortion
2nd
= 2V
OUT P-P-DIFF
Harmonic
3rd Harmonic
THD
V
V
V
= 2V
= 2V
= 2V
-92
-86
-83
dBc
dBc
dBc
OUT
OUT
OUT
P-P-DIFF
P-P-DIFF
P-P-DIFF
3MHz Harmonic Distortion
6MHz Harmonic Distortion
2nd
Harmonic
3rd Harmonic
THD
V
V
V
= 2V
= 2V
= 2V
-70
-70
-76
dBc
dBc
dBc
OUT
OUT
OUT
P-P-DIFF
P-P-DIFF
P-P-DIFF
2nd
Harmonic
3rd Harmonic
THD
V
V
= 2V
= 2V
-66
-65
8.5
dBc
dBc
OUT
OUT
P-P-DIFF
P-P-DIFF
Non-Inverting Input Voltage Noise at each of
the Two Inputs
e
f = 1MHz
f = 1MHz
f = 1MHz
f = 1MHz
nV/Hz
N
Non-Inverting Input Current Noise at each of
the Two Inputs
+i
1.5
38
pA/Hz
pA/Hz
nV/Hz
N
N
Inverting Input Current Noise at each of the
Two Inputs
-i
Common-Mode Output Noise
Power Control Features
Logic High Voltage
e
128
N-CM
V
DIS input
DIS input
DIS = 3.3V
DIS = 0V
2.0
V
V
IH
Logic Low Voltage
V
0.8
IL
Logic High Current for DIS
Logic Low Current for DIS
Supply Characteristics
Maximum Operating Supply Voltage
Minimum Operating Supply Voltage
GND Pin Current
I
0.3
µA
µA
IH
I
-0.4
IL
28
8
V
V
I
All outputs at 0V, DIS = 3.3V
All outputs at V +/2, DIS = 0V
0.4
21
mA
mA
GND
I +
Positive Supply Current
S
S
(full power)
V
= 0V
O-Diff
Positive Supply Current
I +
All outputs at V +/2,
0.4
20
mA
S
S
(power-down) DIS = 3.3V, V
= 0V
O-Diff
Output Characteristics
Unloaded Output Differential Swing
Input Characteristics
V
R
= no load
V
P-P
OUT
L-DIFF
Input Offset Voltage - Differential Mode
Input Offset Voltage - Common-Mode
V
V
(VINA+ - VINB+)
Delta to V +/2
-17
-17
-0.3
4
17
17
mV
mV
IOS-DM
IOS-CM
S
FN8823 Rev.1.00
May 3, 2018
Page 5 of 16
ISL15102
2. Specifications
Unless otherwise noted, all tests are at the specified temperature T = +25°C, V + = +12V, A = 10V/V, R = 4.22kΩ, R = 50Ω
A
S
V
F
L
differential, DIS = 0V. (Continued)
Min
Typ
Max
Parameter
Symbol
Test Conditions
(Note 6) (Note 7) (Note 6) Unit
Input V
Drift
V
-25°C to +125°C T
J
±2
µV/°C
µA
OS
OS, DRIFT
Non-Inverting Input Bias Current - Differential
Mode
+I
(+I - +I
BA BB)
-3
0.2
3
BDM
Inverting Input Bias Current - Differential Mode
-I
(-I - -I
BA
-20
-0.6
±6
20
µA
nA/°C
nA/°C
dB
BDM
BB)
Non-Inverting I + Drift
I
-25°C to +85°C T
-25°C to +85°C T
B
B+, DRIFT
J
J
Inverting I - Drift
B
I
±6
B-, DRIFT
Power Supply Rejections to Differential Output
(Input Referred)
PSRR
V + = +8V to +28V
68
S
Power Supply Rejections to Common-Mode
Output (Output Referred)
V + = +8V to +28V
22
6
dB
kΩ
S
Differential Input Resistance
Thermal Protection
Thermal Shutdown
Notes:
Z
IN
+125
+160
°C
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
7. Typical values are for information purposes only.
FN8823 Rev.1.00
May 3, 2018
Page 6 of 16
ISL15102
3. Typical Performance Curves
3. Typical Performance Curves
V + = +12V, R = 4.22kΩ, A = 10V/V differential, R = 50Ω differential, T = +25°C, DIS = 0V, unless otherwise noted.
S
F
V
L
A
5
0
20
10
RF = 4.22kꢀ
VL = 2VP-P
RF = 4.22kꢀ
-5
A = 10
-10
-15
-20
-25
-30
-35
-40
0
-10
-20
-30
VOUT = 0.5VP-P
VOUT = 10VP-P
VOUT = 5VP-P
A = 10
A = 40
A = 20
100M
300M
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
300M
Figure 2. Small Signal Frequency Response vs Gain
Figure 3. Large Signal Frequency Response
-55
-70
RL = 50kꢀ
RL = 50kꢀ
-60
-75
-65
-70
-75
-80
-80
-85
-90
-95
-85
HD2
HD2
-100
-90
HD3
HD3
-105
-95
0.1
1.0
10.0
0.1
1.0
10.0 20.0
20.0
Differential Output Voltage (VP-P
)
Differential Output Voltage (VP-P
)
Figure 4. 1MHz Harmonic Distortion vs Output Swing
Figure 5. 4MHz Harmonic Distortion vs Output Swing
-30
-30
VL = 1VP-P
-40
VL = 1VP-P
-40
-50
-60
-70
-80
-90
-50
-60
-70
-80
-90
-100
-110
HD2
HD3
-100
-110
HD2
HD3
1
10
100
200
1
10
Differential Load (Ω)
100
200
Differential Load (Ω)
Figure 7. 4MHz Harmonic Distortion vs Load
Figure 6. 1MHz Harmonic Distortion vs Load
FN8823 Rev.1.00
May 3, 2018
Page 7 of 16
ISL15102
3. Typical Performance Curves
V + = +12V, R = 4.22kΩ, A = 10V/V differential, R = 50Ω differential, T = +25°C, DIS = 0V, unless otherwise noted. (Continued)
S
F
V
L
A
30
25
20
15
10
5
30
25
20
15
10
5
A = 10
A = 10
VL = 2VP-P
VL = 2VP-P
CL = 0pF
CL = 10pF
CL = 33pF
CL = 22pF
CL = 47pF
ꢀ
RF = 2800
RF = 4220
RF = 3480
RF = 6340
ꢀ
ꢀ
0
0
ꢀ
-5
-5
300M
1M
10M
Frequency (Hz)
100M
300M
1M
10M
100M
Frequency (Hz)
Figure 8. Small Signal Frequency Response vs R
Figure 9. Small Signal Frequency Response vs C
F
LOAD
30
0
A = 10
A = 10
L = 0.75VP-P
HD2
HD3
-10
-20
-30
-40
-50
-60
-70
-80
-90
VL = 2VP-P
25
20
15
10
5
V
RS = 1 , CL = 47pF
RS = 2.5 , CL = 47pF
RS = 10ꢀ , CL = 47pF
RS = 25 , CL = 47pF
ꢀ
ꢀ
0
ꢀ
-5
100k
1M
Frequency (Hz)
10M
50M
1M
10M
100M
300M
Frequency (Hz)
Figure 10. Small Signal Frequency Response vs R
Figure 11. Harmonic Distortion vs Frequency
S
and C
LOAD
5
0
25
20
15
10
5
A = 10
VL = 2VP-P
-5
-10
-15
-20
0
-5
CL = 0pF
CL = 22pF
CL = 47pF
CL = 10pF
CL = 33pF
VS = 8V
VS = 18V
-10
-15
VS = 28V
1M
10M
100M
300M
300M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 12. Common-Mode Small Signal Frequency
Response vs C
Figure 13. Small Signal Frequency Response vs Supply
Voltage
LOAD
FN8823 Rev.1.00
May 3, 2018
Page 8 of 16
ISL15102
3. Typical Performance Curves
V + = +12V, R = 4.22kΩ, A = 10V/V differential, R = 50Ω differential, T = +25°C, DIS = 0V, unless otherwise noted. (Continued)
S
F
V
L
A
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.38W
ꢁJA = +39°C/W
0
25
50
75
100
125
150
Ambient Temperature (°C)
Figure 14. Package Power Dissipation vs Ambient Temperature
FN8823 Rev.1.00
May 3, 2018
Page 9 of 16
ISL15102
4. Test Circuit
4. Test Circuit
A
R
Network
Analyzer
+12
DC
Splitter
S
50Ω
50Ω
487Ω
53Ω
Load
1:1
DUT
180°
Splitter
R
L
487Ω
50Ω
Figure 15. Frequency Response Characterization Circuit
FN8823 Rev.1.00
May 3, 2018
Page 10 of 16
ISL15102
5. Applications Information
5. Applications Information
5.1
Applying Wideband Current Feedback Op Amps as Differential Drivers
A Current Feedback Amplifier (CFA) such as the ISL15102 is particularly suited to the requirements of high output
power, high bandwidth, and differential drivers. This topology offers a high slew rate on low quiescent power and
the ability to hold AC characteristics relatively constant over a wide range of gains. The AC characteristics are
principally set by the feedback resistor (R ) value in simple differential gain circuits as shown in Figure 16.
F
+12V
+
R , 2.49
S
ISL15102
50
-
R , 4.22k
F
R
, 931
V
G
I
Load
V
O
R , 4.22k
F
R , 2.49
S
-
ISL15102
+
V
/V = 10V/V
I
O
50
Figure 16. Passive Termination Circuit
In this differential gain of 10V/V circuit, the 4.22k feedback resistors (R ) set the bandwidth, and the 931 gain
F
resistor (R ) controls the gain. The V /V gain for this circuit is set by Equation 1:
G
O
I
V
R
F
R
G
4.22kΩ
931Ω
O
(EQ. 1)
-------
--------
-------------------
= 1 + 2
= 1 + 2
= 10.06
V
I
The effect of increasing or decreasing the feedback resistor value is shown in Figure 8 on page 8. Increasing R
F
will tend to roll off the response, while decreasing it will peak the frequency response up, extending the bandwidth.
was adjusted in each of these plots to hold a constant gain of 10 (or 20dB). This shows the flexibility offered by
R
G
the CFA topology; the frequency response can be controlled with the value of the feedback resistor, R , with
F
resistor R setting the desired gain.
G
The ISL15102 provides two very power efficient, high output current CFAs. These are intended to be connected as
one differential driver. The “Pin Configuration” on page 2 show that Channels A and B are intended to operate as a
pair. Power-down control is provided through control pin DIS, which sets the power for Channels A and B together.
Very low output distortion at low power can be provided by the differential configuration. The high slew rate
intrinsic to the CFA topology also contributes to the exceptional performance shown in Figure 11 on page 8. This
swept frequency distortion plot shows low distortion at 200kHz holding to very low levels up through 10MHz.
5.2
Input Biasing and Input Impedance
The ISL15102 has internal resistors at the non-inverting inputs for mid-rail biasing, so only external AC coupling
capacitors are required for input biasing, shown in Figure 1 on page 1. With a 100nF coupling capacitor and an
input differential impedance of 6kΩ typical, the first order high-pass cut-off frequency is 530Hz.
FN8823 Rev.1.00
May 3, 2018
Page 11 of 16
ISL15102
5. Applications Information
5.3
Power Control Function
DIS controls the quiescent current for the port constructed from Amplifiers A and B. Taking DIS high (>2V), will
put the device in Power-Down mode, reducing the supply current to typical 0.4mA. Taking DIS low (<0.8V), will
place the drive in Full Power mode, consuming typically 22mA supply current. Table 2 summarizes the operation
modes for the ISL15102.
Table 2. Power Modes of the ISL15102
DIS
0
Operation
I
Full Power
S
1
Power-Down
FN8823 Rev.1.00
May 3, 2018
Page 12 of 16
ISL15102
6. Performance Considerations
6. Performance Considerations
6.1
Driving Capacitive Loads
All closed-loop op amps are susceptible to reduced phase margin when driving capacitive loads. This shows up as
peaking in the frequency response that can, in extreme situations, lead to oscillations. The ISL15102 is designed to
operate successfully with small capacitive loads such as layout parasitics. As the parasitic capacitance increases, it
is best to consider a small resistor in series with each output to isolate the phase margin effects of the capacitor.
Figure 9 on page 8 shows the effect of capacitive load on the differential gain-of-10 circuit. With 22pF on each
output, we see about 3dB peaking. This will increase quickly at higher C
. If this degree of peaking is
LOADS
unacceptable, a small series resistor can be used to improve the flatness as shown in Figure 10 on page 8.
6.2
Board Design Recommendations
The feedback resistors need to be placed as close as possible to the output and inverting input pins to minimize
parasitic capacitance in the feedback loop. Keep the gain resistor also very close to the inverting inputs for its port
and minimize parasitic capacitances to ground or power planes as well.
Close placement of the supply decoupling capacitors will minimize parasitic inductance in the supply path. High
frequency load currents are typically pulled through these capacitors, so close placement of 0.01µF capacitors on
each of the supply pins will improve dynamic performance. Higher valued capacitors, 6.8µF typically, can be
placed further from the package as they are providing more of the low frequency decoupling.
Connect the thermal pad for the ISL15102 to ground. It is recommended to fill the PCB metal beneath the thermal
pad with a 3x3 array of vias to spread heat away from the package. The larger the PCB metal area, the lower the
junction temperature of the device will be.
Although the ISL15102 is relatively robust in driving parasitic capacitive loads, it is always preferred to place any
series output resistors as close as possible to the output pins. Then trace capacitance on the other side of that
resistor will have a much smaller effect on loop phase margin.
Protection devices that are intended to steer large load transients away from the ISL15102 output stage and into the
power supplies or ground should have a short trace from their supply connections into the nearest supply capacitor,
or they should include their own supply capacitors to provide a low impedance path under fast transient conditions.
FN8823 Rev.1.00
May 3, 2018
Page 13 of 16
ISL15102
7. Revision History
7. Revision History
Rev.
Date
Description
1.00
May 3, 2018
Added ISL15102IRZ-EVALZ to the Ordering Information table.
Updated Figures 2-13 to correct formatting issues.
Figure 14, changed Y-axis unit of measurement from dB to W.
Removed About Intersil section
Updated the disclaimer.
0.00
Dec 1, 2017
Initial release
FN8823 Rev.1.00
May 3, 2018
Page 14 of 16
ISL15102
8. Package Outline Drawing
For the most recent package outline drawing, see L24.4x5F.
8. Package Outline Drawing
L24.4x5F
24 Lead Quad Flat No-Lead Plastic Package
Rev 0, 5/14
PIN 1
INDEX AREA
A
4.00
24x0.40
2.60
6
B
24
20
PIN #1 INDEX AREA
R0.20
6
1
19
13
7
0.10
4x
12
8
0.25 ±0.05
0.50
TOP VIEW
0.5x4 = 2.00 REF
BOTTOM VIEW
SEATING PLANE
0.08
C
C
(24x0.25)
0.10 C
0.203 REF
SEE DETAIL “X”
5
C
(20x0.50)
(24x0.60)
DETAIL "X"
2.60
0.00-0.05
3.80 TYP
TYPICAL RECOMMENDED LAND PATTERN
0.90 ±0.10
SIDE VIEW
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) are for Reference Only.
2. Dimensioning and tolerancing conform to ASMEY14.5m-1994.
3.
4.
Unless otherwise specified, tolerance: Decimal ± 0.05
Dimension applies to the metallized terminal and is measured
between 0.20mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN8823 Rev.1.00
May 3, 2018
Page 15 of 16
Notice
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Colophon 7.0
相关型号：
ISL1532AIRZ
Dual Channel Fixed Gain Differential DSL Line Driver; QFN24, TSSOP20; Temp Range: -40° to 85°C
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