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HSP50110_01 [INTERSIL]

Digital Quadrature Tuner; 数字正交调谐器
HSP50110_01
型号： HSP50110_01
厂家： Intersil    Intersil
描述：

Digital Quadrature Tuner
数字正交调谐器
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HSP50110  
TM  
Data Sheet  
March 2001  
File Number 3651.6  
Digital Quadrature Tuner  
Features  
The Digital Quadrature Tuner (DQT) provides many of the  
functions required for digital demodulation. These functions  
include carrier LO generation and mixing, baseband  
sampling, programmable bandwidth filtering, baseband AGC,  
and IF AGC error detection. Serial control inputs are provided  
which can be used to interface with external symbol and  
carrier tracking loops. These elements make the DQT ideal  
for demodulator applications with multiple operational modes  
or data rates. The DQT may be used with HSP50210 Digital  
Costas Loop to function as a demodulator for BPSK, QPSK,  
8-PSK OQPSK, FSK, FM, and AM signals.  
• Input Sample Rates to 52MSPS  
• Internal AGC Loop for Output Level Stability  
• Parallel or Serial Output Data Formats  
• 10-Bit Real or Complex Inputs  
• Bidirectional 8-Bit Microprocessor Interface  
• Frequency Selectivity <0.013Hz  
• Low Pass Filter Configurable as Three Stage Cascaded-  
Integrator-Comb (CIC), Integrate and Dump, or Bypass  
• Fixed Decimation from 1-4096, or Adjusted by NCO  
Synchronization with Baseband Waveforms  
The DQT processes a real or complex input digitized at rates  
up to 52 MSPS. The channel of interest is shifted to DC by a  
complex multiplication with the internal LO. The quadrature  
LO is generated by a numerically controlled oscillator (NCO)  
with a tuning resolution of 0.012Hz at a 52MHz sample rate.  
The output of the complex multiplier is gain corrected and fed  
into identical low pass FIR filters. Each filter is comprised of a  
decimating low pass filter followed by an optional  
• Input Level Detection for External IF AGC Loop  
• Designed to Operate with HSP50210 Digital Costas Loop  
• 84 Lead PLCC  
Applications  
compensation filter. The decimating low pass filter is a 3  
stage Cascaded-Integrator-Comb (CIC) filter. The CIC filter  
can be configured as an integrate and dump filter or a third  
order CIC filter with a (sin(X)/X)3 response. Compensation  
filters are provided to flatten the (sin(X)/X)N response of the  
CIC. If none of the filtering options are desired, they may be  
bypassed. The filter bandwidth is set by the decimation rate of  
the CIC filter. The decimation rate may be fixed or adjusted  
dynamically by a symbol tracking loop to synchronize the  
output samples to symbol boundaries. The decimation rate  
may range from 1-4096. An internal AGC loop is provided to  
maintain the output magnitude at a desired level. Also, an  
input level detector can be used to supply error signal for an  
external IF AGC loop closed around the A/D.  
• Satellite Receivers and Modems  
• Complex Upconversion/Modulation  
• Tuner for Digital Demodulators  
• Digital PLLs  
• Related Products: HSP50210 Digital Costas Loop;  
A/D Products HI5703, HI5746, HI5766  
• HSP50110/210EVAL Digital Demod Evaluation Board  
Ordering Information  
TEMP.  
o
PART NUMBER  
HSP50110JC-52  
HSP50110JI-52  
RANGE ( C)  
0 to 70  
PACKAGE  
84 Ld PLCC  
84 Ld PLCC  
PKG. NO.  
N84.1.15  
N84.1.15  
The DQT output is provided in either serial or parallel formats  
to support interfacing with a variety DSP processors or digital  
filter components. This device is configurable over a general  
purpose 8-bit parallel bidirectional microprocessor control bus.  
-40 to 85  
Block Diagram  
LOOP  
FILTER  
LEVEL  
DETECT  
COMPLEX  
MULTIPLIER  
GCA  
10  
10  
LOW PASS FIR  
FILTER  
I DATA  
o
90  
REAL OR COMPLEX  
o
CARRIER  
TRACKING CONTROL  
0
NCO  
INPUT DATA  
10  
LOW PASS FIR  
FILTER  
10  
Q DATA  
GCA  
DUMP  
IF AGC  
LEVEL  
SAMPLE STROBE  
CONTROL  
DETECT  
PROGRAMMABLE  
RE-SAMPLING  
NCO  
CONTROL  
SAMPLE RATE  
CONTROL  
CONTROL/STATUS  
BUS  
8
INTERFACE  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2001, All Rights Reserved  
1
HSP50110  
Pinout  
HSP50110 (PLCC)  
TOP VIEW  
11 10 9  
8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
IIN5  
IIN4  
IIN3  
IIN2  
GND  
IIN1  
IOUT3  
IOUT2  
IOUT1  
IOUT0  
DATARDY  
V
CC  
IIN0  
ENI  
CLK  
GND  
QIN9  
QIN8  
QIN7  
QIN6  
QIN5  
QIN4  
QOUT9  
QOUT8  
QOUT7  
QOUT6  
QOUT5  
GND  
QOUT4  
QOUT3  
QOUT2  
QOUT1  
QOUT0  
OEQ  
V
CC  
QIN3  
QIN2  
QIN1  
QIN0  
PH1  
PH0  
V
CC  
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  
Pin Descriptions  
NAME  
TYPE  
DESCRIPTION  
V
-
-
I
+5V Power Supply.  
Ground.  
CC  
GND  
IIN9-0  
In-Phase Input. Data input for in-phase (real) samples. Format may be either two’s complement or offset binary format  
(see I/O Formatting/Control Register in Table 9). IIN9 is the MSB.  
QIN9-0  
ENI  
I
I
Quadrature Input. Data input for quadrature (imaginary) samples. Format may be either two’s complement or offset bi-  
nary format (see I/O Formatting/Control Register in Table 9). QIN9 is the MSB.  
Input Enable. When ENI is active ‘low’, data on IIN9-0 and QIN9-0 is clocked into the processing pipeline by the rising  
edge of CLK. This input also controls the internal data processing as described in the Input Controller Section of the  
data sheet. ENI is active ‘low’.  
PH1-0  
CFLD  
I
I
Carrier Phase Offset. The phase of the internally generated carrier frequency may be shifted by 0, 90, 180, or 270 de-  
grees by controlling these pins (see Synthesizer/Mixer Section). The phase mapping for these inputs is given in Table 1.  
Carrier Frequency Load. This input loads the Carrier Frequency Register in the Synthesizer NCO (see  
Synthesizer/Mixer Section). When this input is sampled ‘high’ by clock, the contents of the Microprocessor Interface  
Holding Registers are transferred to the carrier frequency register in the Synthesizer NCO (see Microprocessor Inter-  
face Section). NOTE: This pin must be ‘low’ when loading other configuration data via the Microprocessor In-  
terface. Active high Input.  
COF  
I
I
Carrier Offset Frequency Input. This serial input is used to load the Carrier Offset Frequency into the Synthesizer NCO  
(see Serial Interface Section). The new offset frequency is shifted in MSB first by CLK starting with the clock cycle after  
the assertion of COFSYNC.  
COFSYNC  
Carrier Offset Frequency Sync. This signal is asserted one CLK cycle before the MSB of the offset frequency data word  
(see Serial Interface Section).  
2
HSP50110  
Pin Descriptions (Continued)  
NAME  
TYPE  
DESCRIPTION  
SOF  
I
Sampler Offset Frequency. This serial input is used to load the Sampler Offset Frequency into the Re-Sampler NCO  
(see Serial Interface Section). The new offset frequency is shifted in MSB first by CLK starting with the clock cycle after  
assertion of SOFSYNC.  
SOFSYNC  
A2-0  
I
I
Sampler Offset Frequency Sync. This signal is asserted one CLK cycle before the MSB of Sampler Offset Frequency  
data word (see Serial Interface Section).  
Address Bus. These inputs specify a target register within the Microprocessor Interface (see Table 5). A2 is the MSB.  
This input is setup and held to the rising edge of WR.  
C7-0  
I/0  
Control Bus. This is the bidirectional data bus for reads and writes to the Microprocessor Interface (see Microprocessor  
Interface Section). C7 is the MSB.  
WR  
RD  
I
I
Write. This is the write strobe for the Microprocessor Interface (see Microprocessor Interface Section).  
Read. This is the read enable for the Microprocessor Interface (see Microprocessor Interface Section).  
IOUT9-0  
O
In-Phase Output. The data on these pins is output synchronous to CLK. New data on IOUT9-0 is indicated by the as-  
sertion of the DATARDY pin. Data may be output parallel or serial mode (see Output Formatter Section). In the parallel  
mode, IOUT9 is the MSB. When the serial mode is used, IOUT0 is data, and IOUT9 is the serial clock. Other pins not  
used in serial mode may be set high or low via the control interface.  
QOUT9-0  
O
O
Quadrature Output. The data on these pins is output synchronous to CLK. New data on the QOUT(9-0) pins is indicated  
by the DATARDY pin. Data may be output parallel or serial mode. In the parallel mode, IOUT9 is the MSB. When the  
serial mode is used, QOUT0 is data.  
DATARDY  
Data Ready. This output is asserted on the first clock cycle that new data is available on the IOUT and QOUT data  
busses (see Output Formatter Section). This pin may be active ‘high’ or ‘low’ depending on the configuration of the I/O  
Formatting/Control Register (see Table 9). In serial mode, DATARDY is asserted one IQ clock before for first bit of serial  
data.  
OEI  
OEQ  
I
I
In-Phase Output Enable. This pin is the three-state control for IOUT9-0. When OEI is ‘high’, the IOUT bus is held in the  
high impedance state.  
Quadrature Output Enable. This pin is the three-state control for QOUT9-0. When OEQ is ‘high’, the QOUT bus is held  
in the high impedance state.  
LOTP  
SSTRB  
0
0
Local Oscillator Test Point. This output is the MSB of the Synthesizer NCO phase accumulator (see Synthesizer/Mixer  
Section). This is provided as a test point for monitoring the frequency of the Synthesizer NCO.  
Sample Strobe. This is the bit rate strobe for the bit rate NCO. SSTRB has two modes of operation: continuous update  
and sampled. In continuous update mode, this is the carry output of the Re-Sampler NCO. In sampled mode, SSTRB  
is active synchronous to the DATARDY signal for parallel output mode. The sampled mode is provided to signal the  
nearest output sample aligned with or following the symbol boundary. This signal can be used with SPH(4-0) below to  
control a resampling filter to time shift its impulse response to align with the symbol boundaries.  
SPH4-0  
0
Sample Phase. These are five of the most significant 8 bits of the Re-Sampler NCO phase accumulator. Which five bits  
of the eight is selected via the Chip Configuration Register (see Table 11). These pins update continuously when the  
SSTRB output is in the continuous update mode. When the SSTRB pin is in the sampled mode, SPH4-0 update only  
when the SSTRB pin is asserted. In the sampled mode, these pins indicate how far the bit phase has advanced past  
the symbol boundary when the output sample updates. SPH4 is the MSB.  
HI/LO  
CLK  
0
I
HI/LO. The output of the Input Level Detector is provided on this pin (see Input Level Detector Section). The sense of  
the HI/LO pin is set via the Chip Configuration Register (see Table 11). This signal can be externally averaged and used  
to control the gain of an amplifier to close an AGC loop around the A/D converter. This type of AGC sets the level based  
on the median value on the input.  
Clock. All I/O’s with the exception of the output enables and the microprocessor interface are synchronous to clock.  
3
HSP50110  
UPPER LIMIT†  
LOWER LIMIT†  
AGC THRESHOLD†  
LOOP GAIN †  
HI/LO OUTPUT SENSE†  
LOOP  
FILTER  
LEVEL  
DETECT  
LEVEL  
DETECT  
THRESHOLD FOR  
EXTERNAL AGC †  
HI/LO  
AGC  
OEI  
LOW PASS FILTERING  
SYNTHESIZER/MIXER  
F
O
R
M
11  
10  
10  
12  
12  
10  
IIN0-9  
CLK  
IOUT0-9  
COMPLEX  
MULTIPLIER  
DATARDY  
10  
11  
A
QOUT0-9  
OEQ  
QIN0-9  
T
ENI  
DECIMATING  
FILTER  
COMPENSATION  
COS  
SIN  
FILTER  
INPUT MODE†  
10  
10  
INPUT FORMAT†  
PH0-1  
32  
8
CENTER  
FREQUENCY†  
DIVIDER  
SYNTHESIZER  
NCO  
CFLD  
COF  
CLK  
PHASE  
OFFSET†  
SHIFT REG  
COFSYNC  
RE-SAMPLER  
NCO  
SSTRB  
SPH0-4  
5
LOTP  
COF EN†  
32  
SAMPLER CENTER  
FREQUENCY†  
WORD WIDTH†  
SOF EN†  
WORD WIDTH†  
SOF  
SOFSYNC  
A0-2  
SHIFT REG  
RE-SAMPLER  
WR  
RD  
MICROPROCESSOR INTERFACE  
C0-7  
† Indicates data downloaded via microprocessor interface  
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF HSP50110  
compares the input signal magnitude to a programmable  
Functional Description  
level and generates an error signal. The error signal can be  
externally averaged to set the gain of an amplifier in front of  
the A/D which closes the AGC loop. The output signal level  
is maintained by an internal AGC loop closed around the  
Low Pass Filtering. The AGC loop gain and gain limits are  
programmable.  
The Digital Quadrature Tuner (DQT) provides many of the  
functions needed for digital demodulation including: carrier  
LO generation, mixing, low-pass filtering, baseband  
sampling, baseband AGC, and IF AGC error detection. A  
block diagram of the DQT is provided in Figure 1. The DQT  
processes a real or complex input at rates up to 52 MSPS.  
The digitized IF is input to the Synthesizer/Mixer where it is  
multiplied by a quadrature LO of user programmable  
frequency. This operation tunes the channel of interest to DC  
where it is extracted by the Low Pass FIR Filtering section.  
The filter bandwidth is set through a user programmable  
decimation factor. The decimation factor is set by the Re-  
Sampler which controls the baseband sampling rate. The  
baseband sample rate can be adjusted by an external  
symbol tracking loop via a serial interface. Similarly, a serial  
interface is provided which allows the frequency of the  
Synthesizer/Mixer’s NCO to be controlled by an external  
carrier tracking loop. The serial interfaces were designed to  
mate with the output of loop filters on the HSP50210 Digital  
Costas Loop.  
Input Controller  
The input controller sets the input sample rate of the  
processing elements. The controller has two operational  
modes which include a Gated Input Mode for processing  
sample rates slower than CLK, and an Interpolated Input  
Mode for increasing the effective time resolution of the  
samples. The mode is selected by setting bit 1 of the I/O  
Formatting Control Register in Table 9.  
In Gated Input Mode, the Input Enable (ENI) controls the  
data flow into the input pipeline and the processing of the  
internal elements. When this input is sampled “low” by CLK,  
the data on IIN0-9 and QIN0-9 is clocked into the processing  
pipeline; when ENI is sampled “high”, the data inputs are  
disabled. The Input Enable is pipelined to the internal  
processing elements so that they are enabled once for each  
time ENI is sampled low. This mode minimizes the  
The DQT provides an input level detector and an internal  
AGC to help maintain the input and output signal  
magnitudes at user specified levels. The input level detector  
4
HSP50110  
processing pipeline latency, and the latency of the part’s  
serial interfaces while conserving power. Note: the  
effective input sample rate to the internal processing  
elements is equal to the frequency with which ENI is  
asserted “low”.  
Note: an external AGC loop using the Input Level  
Detector may go unstable for a real sine wave input  
whose frequency is exactly one quarter of the sample  
rate (F /4). The Level Detector responds to such an  
S
input by producing a square wave output with a 50%  
duty cycle for a wide range of thresholds. This square  
wave integrates to zero, indicating no error for a range  
of input signal amplitudes.  
In Interpolated Input Mode, the ENI input is used to insert  
zeroes between the input data samples. This process  
increases the input sample rate to the processing elements  
which improves the time resolution of the processing chain.  
When ENI is sampled “high” by CLK, a zero is input into the  
processing pipeline. When ENI is sampled “low” the input  
data is fed into the pipeline. Note: Due to the nature of the  
rate change operation, consideration must be given to  
the scaling and interpolation filtering required for a  
particular rate change factor.  
Synthesizer/Mixer  
The Synthesizer/Mixer spectrally shifts the input signal of  
interest to DC for subsequent baseband filtering. This  
function is performed by using a complex multiplier to  
multiply the input with the output of a quadrature numerically  
controlled oscillator (NCO). The multiplier operation is:  
I
= I x cos (ω ) - Q x sin (ω )  
(EQ. 3)  
(EQ. 4)  
OUT  
IN  
c
IN  
c
In either the Gated or Interpolated Input Mode, the  
Synthesizer NCO is gated by the ENI input. This only allows  
clocking of the NCO when external samples are input to the  
processing pipeline. As a result, the NCO frequency must be  
set relative to the input sample rate, not the CLK rate (see  
Synthesizer/Mixer Section). NOTE: Only fixed  
Q
= I x sin (ω ) + Q x cos (ω )  
IN c IN c  
OUT  
The complex multiplier output is rounded to 12 bits. For real  
inputs this operation is similar to that performed by a  
quadrature downconverter. For complex inputs, the  
Synthesizer/Mixer functions as a single-sideband or image  
reject mixer which shifts the frequency of the complex  
samples without generating images.  
interpolation rates should be used when operating the  
part in Interpolated Mode at the Input Controller.  
Input Level Detector  
TO COMPLEX MULTIPLIER  
COS  
10 10  
SIN  
The Input Level Detector generates a one-bit error signal for  
an external IF AGC filter and amp. The error signal is  
generated by comparing the magnitude of the input samples  
to a user programmable threshold. The HI/LO pin is then  
driven “high” or “low” depending the relationship of its  
magnitude to the threshold. The sense of the HI/LO pin is  
programmable so that a magnitude exceeding the threshold  
can either be represented as a “high” or “low” logic state.  
The threshold and the sense of the HI/LO pin are configured  
by loading the appropriate control registers via the  
REG  
REG  
†Controlled via  
microprocessor interface.  
SIN/COS  
ROM  
11  
R
R
E
G
PHASE OFFSET †  
2
8
PH0-1  
+
E
G
REG  
0
LOTP  
Microprocessor Interface (see Tables 7 and 11).  
LOAD †  
REG  
+
MUX  
The high/low outputs can be integrated by an external loop  
filter to close an AGC loop. Using this method the gain of the  
loop forces the median magnitude of the input samples to  
the threshold. When the magnitude of half the samples are  
above the threshold and half are below, the error signal is  
integrated to zero by the loop filter.  
MUX  
COF  
ENABLE †  
PHASE  
ACCUMULATOR  
32  
32  
COF  
0
CF  
REG  
REG  
The algorithm for determining the magnitude of the complex  
input is given by:  
COFSYNC  
COF  
SYNC  
SHIFT REG  
SYNC  
Mag(I,Q) = |I| + .375 x |Q| if |I| > |Q|  
or:  
(EQ. 1)  
R
E
G
CARRIER  
FREQUENCY† FREQUENCY†  
LOAD CARRIER  
CFLD  
Mag(I,Q) = |Q| + .375 x |I| if |Q| > |I|,  
(EQ. 2)  
FIGURE 2. SYNTHESIZER NCO  
Using this algorithm, the magnitude of complex inputs can  
be estimated with an error of <0.55dB or approximately  
6.5%. For real inputs, the magnitude detector reduces to a  
an absolute value detector with negligible error.  
The quadrature outputs of the NCO are generated by driving  
a sine/cosine lookup table with the output of a phase  
accumulator as shown in Figure 2. Each time the phase  
accumulator is clocked, its sum is incremented by the sum of  
5
HSP50110  
the contents of the Carrier Frequency (CF) Register and the  
As an example, a value of 32, (20  
Offset Register would produce a phase offset of 45 .  
), loaded into the Phase  
o
HEX  
Carrier Offset Frequency (COF) Register. As the  
32  
accumulator sum transitions from 0 to 2 , the SIN/COS  
An alternative method for controlling the NCO Phase uses  
ROM produces quadrature outputs whose phase advances  
o
the PH0-1 inputs to shift the phase of NCO’s output by 0 ,  
o
o
from 0 to 360 . The sum of the CF and COF Registers  
represent a phase increment which determines the  
frequency of the quadrature outputs. Large phase  
o
o
o
90 , 180 , or 270 . The PH0-1 inputs are mapped to phase  
shifts as shown in Table 1. The phase may be updated every  
clock supporting the π/2 phase shifts required for modulation  
or despreading of CDMA signals.  
increments take fewer clocks to transition through the sine  
wave cycle which results in a higher frequency NCO output.  
-36  
The output of the complex multiplier is scaled by 2 . See  
“Setting DQT Gains” below.  
The NCO frequency is set by loading the CF and COF  
Registers. The contents of these registers set the NCO  
frequency as given by the following,  
TABLE 1. PH0-1 INPUT PHASE MAPPING  
= F x (CF + COF)/232,  
(EQ. 5)  
PH1-0  
00  
PHASE SHIFT  
F
C
S
o
0
where f is the sample rate set by the Input Controller, CF is  
S
the 32-bit two’s complement value loaded into the Carrier  
Frequency Register, and COF is the 32-bit two’s  
complement value loaded into the Carrier Offset Frequency  
Register. This can be rewritten to have the programmed CF  
and COF value on the left:  
o
01  
90  
o
10  
270  
o
11  
180  
32  
(EQ. 5A)  
AGC  
(CF + COF) = INT[(F /F )2  
]
HEX  
C
S
The level of the Mixer output is gain adjusted by an AGC  
closed around the Low Pass Filtering. The AGC provides the  
coarse gain correction necessary to help maintain the output  
of the HSP50110 at a signal level which maintains an  
acceptable dynamic range. The AGC consists of a Level  
Detector which generates an error signal, a Loop Gain  
multiplier which amplifies the error, and a Loop Filter which  
integrates the error to produce gain correction (see  
Figure 4).  
As an example, if the CF Register is loaded with a value of  
3000 0000 (Hex), the COF Register is loaded with a value of  
1000 0000 (Hex), and the input sample rate is 40 MSPS, an  
the NCO would produce quadrature terms with a frequency  
of 10MHz. When the sum of CF and COF is a negative  
value, the cos/sin vector generated by the NCO rotates  
clockwise which downconverts the upper sideband; when  
the sum is positive, the cos/sin vector rotates  
counterclockwise which upconverts the lower sideband.  
The Level Detector generates an error signal by comparing  
the magnitude of the DQT output against a user  
Note: the input sample rate F is determined by the rate  
S
programmable threshold (see AGC Control Register in Table  
8). In the normal mode of operation, the Level Detector  
outputs a -1 for magnitudes above the threshold and +1 for  
those below the threshold. The ±1 outputs are then multiplied  
by a programmable loop gain to generate the error signal  
integrated by the Loop Filter. The Level Detector uses the  
magnitude estimation algorithm described in the Input Level  
Detector Section. The sense of the Level Detector Output may  
be changed via the Chip Configuration Register, bit 0 (see  
Table 11).  
at which ENI is asserted low (see Input Controller  
Section). If ENI is tied low, the input sample rate is equal  
to the CLK rate.  
The Carrier Frequency Register is loaded via the  
Microprocessor Interface and the Carrier Offset Frequency is  
loaded serially using the COF and COFSYNC inputs. The  
procedure for loading these registers is discussed in the  
Microprocessor Interface Section and the Serial Input  
Section.  
The phase of the NCO’s quadrature outputs can be adjusted  
by adding an offset value to the output of the phase  
The Loop Filter consists of a multiplier, an accumulator and a  
programmable limiter. The multiplier computes the product of  
the output of the Level Detector and the Programmable Loop  
Gain. The accumulator integrates this product to produce the  
AGC gain, and the limiter keeps the gain between preset  
limits (see AGC Control Register, Table 8). The output of the  
AGC Loop Filter Accumulator can be read via the  
accumulator as shown in Figure 2. The offset value can be  
loaded into the Phase Offset (PO) Register or input via the  
PH0-1 inputs. If the PO Register is used, the phase can be  
o
adjusted from -π to π with a resolution of ~1.4 . The phase  
offset is given by the following equation,  
Microprocessor Interface to estimate signal strength (see  
Microprocessor Interface Section).  
φ = π x (PO/128),  
(EQ. 6)  
where PO is the 8-bit two’s complement value loaded into the  
Phase Offset Register (see Phase Offset Register in Table 12).  
The Loop Filter Accumulator uses a pseudo floating point  
format to provide up to ~48dB of gain correction. The format  
6
HSP50110  
of the accumulator output is shown in Figure 3. The AGC  
gain is given by:  
most significant bits of the Loop Filter Accumulator.  
Examples of how to set the limits for a specific output signal  
level are provided in the “Setting DQT Gains” Section below.  
NOTE: A fixed AGC gain may be set by programming  
the upper and lower limits to the same value.  
E
Gain  
= (1.0 + M) x 2  
(EQ. 7)  
AGC  
MAPS TO AGC  
UPPER AND LOWER LIMITS  
256  
240  
224  
208  
192  
176  
160  
144  
128  
112  
96  
80  
64  
48  
32  
16  
0
48  
42  
36  
30  
24  
18  
12  
6
L
2
L
2
L
2
L
2
L
2
L
2
L
2
L
2
2
1
0
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13  
2
2
2
2
2
2
2
2
.
E
E
E
M
M
M
M
X
G
G
G
G
G
G
G
G
dB  
MANTISSA  
0.0 to 0.9375  
PROGRAMMABLE  
LOOP GAIN  
LINEAR  
EXPONENT  
0 TO 7  
MAPS TO µP AGC  
LOOP FILTER ACCUMULATOR PARAMETER  
This Value Can Be Read By The Microprocessor.  
See The Microprocessor Interface Section.  
0
0
16 32 48 64 80 96 112128 144160 176192 208 224 240  
GAIN CONTROL WORD  
(8 MSBs OF LOOP FILTER ACCUMULATOR)  
FIGURE 3. BINARY FORMAT FOR LOOP FILTER  
ACCUMULATOR  
FIGURE 5. GAIN CONTROL TRANSFER FUNCTION  
where M is the 4-bit mantissa value ranging from 0.0 to  
The response time of the AGC is determined by the  
0.9375, and E is the three bit exponent ranging from 0 to 7.  
The result is a piece wise linear transfer function whose  
overall response is logarithmic, as shown in Figure 5. The  
exponent bits provide a coarse gain setting of 2(EEE). This  
corresponds to a gain range from 0dB to 42dB (20 to 27) with  
the MSB representing a 24dB gain, the next bit a 12dB gain,  
and the final bit a 6dB gain. The four mantissa bits map to an  
additional gain of 1.0 to 1.9375 (0 to ~6dB). Together, the  
exponent and the mantissa portion of the limit set a gain  
range from 0 to ~48dB.  
Programmable Loop Gain. The Loop Gain is an unsigned  
8-bit value whose significance relative to the AGC gain is  
shown in Figure 3. The loop gain is added or subtracted from  
the accumulator depending on the output of the Level  
Detector. The accumulator is updated at the output sample  
rate. If the accumulator exceeds the upper or lower limit, the  
accumulator is loaded with that limit. The slew rate of the  
AGC ranges between ~0.001dB and 0.266dB per output  
sample for Loop Gains between 01(HEX) and FF (HEX)  
respectively.  
AGC  
DISABLE †  
AGC L.D. SENSE†  
AGC THRESHOLD †  
The user should exercise care when using maximum loop  
gain when the (x/sin(x)) or the (x/sin(x)) compensation filter is  
3
AGC LOOP FILTER  
enabled. At high decimation rates, the delay through the  
compensation filter may be large enough to induce  
oscillations in the AGC loop. The Basic Architectural  
Configurations Section contains the necessary detailed block  
diagrams to determine the loop delay for different matched  
filter configurations.  
LEVEL  
DETECTOR  
REG  
LIMIT  
REG  
+
LOWER  
GAIN  
LIMIT †  
UPPER  
GAIN  
LIMIT †  
Q DATA  
I DATA  
PROGRAMMABLE  
Low Pass Filtering  
LOOP GAIN †  
The gain corrected signal feeds a Low Pass Filtering Section  
comprised of a Cascaded Integrator Comb (CIC) and  
compensation filter. The filtering section extracts the channel  
of interest while providing decimation to match the output  
sample rate to the channel bandwidth. A variety of filtering  
configurations are possible which include integrate and  
dump, integrate and dump with x/sin(x) compensation, third  
order CIC, and third order CIC with ((x)/sin(x))3  
† Indicates data downloaded via microprocessor interface.  
FIGURE 4. AGC BLOCK DIAGRAM  
The limiter restricts the AGC gain range by keeping the  
accumulator output between the programmed limits. If the  
accumulator exceeds the upper or lower limit, then the  
accumulator is held to that limit. The limits are programmed  
via eight bit words which express the values of the upper and  
lower limits as eight bit pseudo floating point numbers as  
shown in Figure 3 (see AGC Control Register, Table 8). The  
format for the limits is the same as the format of the eight  
compensation. If none of these filtering options are desired,  
the entire filtering section may be bypassed.  
7
HSP50110  
The Integrate and Dump filter exhibits a frequency response  
examples of compensation filter performance for the Integrate  
and dump and third order CIC filter are shown overlaid on the  
frequency responses of the uncompensated filters in Figure 6  
and Figure 7. The coefficients for the compensation filters are  
given in Table 2.  
given by  
I
---  
H(f) = sin(πfR)/sin(πf)  
(EQ. 8)  
R
where f is normalized frequency relative to the input sample  
10  
rate, F , and R is the decimation rate [1]. The decimation  
S
rate is equivalent to the number of samples in the integration  
period. As an example, the frequency response for an  
integrate and dump filter with decimation of 64 is shown in  
Figure 6. The decimation rate is controlled by the  
Re-Sampler and may range in value from 2 to 4096 (see  
Re-Sampler Section).  
0
COMPENSATION  
FILTER  
COMPOSITE FILTER  
-10  
-20  
-30  
-40  
-50  
-60  
CIC  
FILTER  
10  
COMPOSITE FILTER  
0
COMPENSATION  
FILTER  
-10  
CIC  
FILTER  
-20  
-30  
-40  
-50  
-60  
f
f
3f  
2f  
5f  
3f  
7f  
4f  
S
S
S
S
S
S
S
S
2R  
R
2R  
R
2R  
R
2R  
R
SAMPLE TIMES  
NOTE: Example plotted is for R = 64 with 64 samples/symbol.  
FIGURE 7. THIRD ORDER CIC FREQUENCY RESPONSE  
TABLE 2. COMPENSATION FILTER COEFFICIENTS  
3
f
f
3f  
2f  
5f  
3f  
7f  
4f  
S
S
S
S
S
S
S
S
COEFFICIENT INDEX  
x/sin(x) [2]  
[x/sin(x)]  
-1  
2R  
R
2R  
R
2R  
R
2R  
R
0
1
-1  
2
SAMPLE TIMES  
NOTE: Example plotted is for R = 64 with 64 samples/symbol.  
4
FIGURE 6. INTEGRATE AND DUMP FILTER (FIRST ORDER  
CIC) FREQUENCY RESPONSE  
2
-4  
-16  
32  
3
10  
-34  
384  
-34  
10  
-4  
For applications requiring better out of band attenuation, the  
Third Order CIC filter may be selected. This filter has a  
frequency response given by  
4
-64  
136  
-352  
1312  
-352  
136  
-64  
32  
5
3
3
6
H(f) = [sin(πfR)/sin(πf)] [1/R]  
(EQ. 9)  
7
where f is normalized frequency relative to the input sample  
rate, and R is the decimation rate [1]. As with the integrate  
and dump filter, the decimation rate is controlled by the Re-  
Sampler. The decimation rate may range in value from  
2-4096 when using CLK, or 3-4096 when using the Re-  
Sampler NCO as a CLK source to the filter. The frequency  
response for the third order CIC with a decimation rate of 64  
is shown in Figure 7.  
8
9
2
10  
11  
12  
13  
14  
-1  
-16  
4
Compensation filters may be activated to flatten the frequency  
responses of the integrate and dump and third order CIC  
filters. The compensation filters operate at the decimated data  
rate, and flatten the roll off the decimating filters from DC to  
approximately one half of the output sample rate. Together,  
the Integrate and Dump filter and x/sin(x) compensation filter  
typically yield a lowpass frequency response that is flat to  
-1  
The out of band channels and noise attenuated by the  
decimating filters are aliased into the output spectrum as a  
result of the decimating process. A summation of the alias  
terms at each frequency of the output spectrum produce  
alias profiles which can be used to determine the usable  
output bandwidth. A set of profiles representative of what  
would be observed for decimation factors of ~10 or more are  
shown in Figures 8 through 11. The Integrate and Dump  
filter is typically used as a matched filter for square pulses  
0.45F with 0.03dB of ripple, and the third order CIC with  
S
3
((x)/sin(x)) compensation typically yields a flat passband to  
0.45F with 0.08dB of ripple. The overall passband ripple  
S
degrades slightly for decimation rates of less than 10. Some  
8
HSP50110  
and less as a high order decimating filter. This is evident by  
Consider a digital filter with sampling frequency fs, whose  
frequency response shown in Figure 12A, the top spectrum.  
At first glance the usable bandwidth would appear to be the  
3dB bandwidth of the main lobe. This filter is to be  
the narrow alias free part of the output bandwidth as shown  
in Figures 8 and 9. The more rapid roll off of the third order  
CIC produces an output spectrum containing a much higher  
usable bandwidth versus output sample rate as shown in  
decimated to a rate of 1/8 f . We concern ourselves with  
S
Figures 10 and 11. For example, the aliasing noise at F /4  
those elements less than f /2, as shown in Figure 12B. The  
S
S
for the uncompensated third order CIC filter is approximately  
~29dB below the full scale input.  
decimation process will fold the various lobes of the  
frequency response around the new sampling folding  
frequency of f /2R. The first lobe is folded over the dotted line  
S
Understanding the Alias Profile  
and a significant portion of the first lobe appears in the  
passband of the filter. Any unwanted signals in this part of the  
spectrum will appear in the band of interest with the greatest  
amplitude. The second lobe is translated down to be centered  
on the dashed line. The third lobe is spectrally inverted and  
translated to be centered on the dotted line. The fourth lobe is  
simply translated to be centered on the dotted line. If there  
were more lobes to the filter, the process would continue to  
spectrally invert the odd numbered lobes prior to translation to  
For digital filters that utilize decimation techniques to reduce  
the rate of the digital processing, care must be taken to  
understand the ramifications, in the frequency domain, of  
decimation (rate reduction). Of primary concern is the “noise”  
level increase due to signals that may be aliased inside the  
band of interest. The potential magnitude of these signals  
may render significant portions of the previously thought  
usable bandwidth, unusable for applications that require  
significant (>60dB) attenuation of undesired signals.  
f /2R. This process is shown in the “C” portion of Figure 12.  
S
10  
10  
0
FILTER RESPONSE  
0
-10  
-10  
FILTER RESPONSE  
ALIAS PROFILE  
-20  
-20  
ALIAS PROFILE  
-30  
-30  
-40  
-40  
-50  
-60  
-50  
-60  
(EXAMPLE PLOTTED IS FOR R = 64  
WITH 64 SAMPLES/SYMBOL)  
(EXAMPLE PLOTTED IS FOR R = 64  
WITH 64 SAMPLES/SYMBOL)  
0
0
f
f
3f  
f
5f  
3f  
7f  
f
f
f
3f  
f
5f  
3f  
7f  
f
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
16R  
8R  
16R  
4R  
16R  
8R  
16R  
2R  
16R  
8R  
16R  
4R  
16R  
8R  
16R  
2R  
SAMPLE TIMES  
SAMPLE TIMES  
FIGURE 8. ALIAS PROFILE: INTEGRATE/DUMP FILTER, NO  
COMPENSATION  
FIGURE 9. ALIAS PROFILE: INTEGRATE/DUMP FILTER  
WITH COMPENSATION  
10  
0
10  
0
FILTER RESPONSE  
-10  
-10  
-20  
-30  
-40  
-50  
-60  
FILTER RESPONSE  
-20  
-30  
ALIAS PROFILE  
ALIAS PROFILE  
-40  
-50  
-60  
(EXAMPLE PLOTTED IS FOR R = 64  
WITH 64 SAMPLES/SYMBOL)  
(EXAMPLE PLOTTED IS FOR R = 64  
WITH 64 SAMPLES/SYMBOL)  
0
0
f
f
3f  
f
5f  
3f  
7f  
f
f
f
3f  
f
5f  
3f  
7f  
f
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
16R  
8R  
16R  
4R  
16R  
8R  
16R  
2R  
16R  
8R  
16R  
4R  
16R  
8R  
16R  
2R  
SAMPLE TIMES  
SAMPLE TIMES  
FIGURE 10. ALIAS PROFILE: 3RD ORDER CIC, NO  
COMPENSATION  
FIGURE 11. ALIAS PROFILE: 3RD ORDER CIC WITH  
COMPENSATION  
9
HSP50110  
constant for decimation factors of over ~50. A summary of  
equivalent IF B ’s for different filter configurations and  
N
decimation rates is given in Table 3. These noise bandwidths  
are provided so that output SNR can be calculated from input  
SNR. In detection applications this bandwidth indicates the  
detection bandwidth.  
A
B
C
D
TABLE 3. DOUBLE SIDED NOISE EQUIVALENT BANDWIDTH  
FOR DIFFERENT FILTER CONFIGURATIONS AND  
OUTPUT SAMPLE RATES  
3RD  
INTEGRATE/  
DUMP W/  
x/sin(x)  
3RD  
ORDER  
CIC  
ORDER  
CIC W/  
[x/sin(x)]  
INTEGRATE/  
DUMP  
3
DEC  
2
1.0000  
1.0000  
1.0000  
1.0000  
1.0000  
1.0000  
1.0000  
1.0000  
1.0000  
1.0000  
1.0000  
1.0000  
1.0000  
1.0000  
1.0000  
1.0000  
1.3775  
1.3775  
1.3775  
1.3775  
1.3775  
1.3775  
1.3775  
1.3775  
1.3775  
1.3775  
1.3775  
1.3775  
1.3775  
1.3775  
1.3775  
1.3775  
0.6250  
0.5525  
0.5508  
0.5504  
0.5502  
0.5501  
0.5501  
0.5501  
0.5501  
0.5500  
0.5500  
0.5500  
0.5500  
0.5500  
0.5500  
0.5500  
1.3937  
1.0785  
1.0714  
1.0698  
1.0691  
1.0688  
1.0687  
1.0686  
1.0685  
1.0684  
1.0684  
1.0684  
1.0684  
1.0684  
1.0683  
1.0683  
10  
18  
26  
34  
42  
50  
58  
66  
74  
82  
90  
98  
106  
114  
f
f
S
S
f
S
2
2R  
FIGURE 12.  
To create the alias profile, a composite response, the  
components of which are shown in the ”D” portion of  
Figure 12, is made from the sum of all the alias elements.  
The primary use of an alias profile is used to determine what  
bandwidth yields the desired suppression of unwanted  
signals for a particular application.  
Reviewing Figures 9 through 11, note the following  
observations:  
1. The uncompensated I&D (1st order CIC) filter yields  
about 12dB of alias suppression at f /16R. This usable  
S
bandwidth is considerably narrower than the 3dB filter  
bandwidth. The I&D filter is the matched filter for square  
wave data that has not been bandlimited.  
122-  
4096  
2. The compensated I&D filter offers a flatter, wider band-  
width than just the I&D alone. This filter compensates for  
the frequency roll off due to the A/D converter.  
Re-Sampler  
3. The uncompensated 3rd order CIC filter yields over 60dB  
The Re-Sampler sets the output sample rate by controlling  
the sample rate of the decimation filters (see Low Pass Filter  
Section). The output sample rate may be fixed or adjusted  
dynamically to synchronize with baseband waveforms. The  
reduction in sample rate between the Low Pass Filter input  
and output represents the decimation factor.  
of alias suppression at f /16R. Typical application is  
S
found in tuners, where the DQT is followed by a very nar-  
row band filter.  
4. The 3rd order CIC with compensation yields alias sup-  
pression comparable to the 3rd order CIC, but with the  
flatter, wider passband. This filter is selected for most  
SATCOM applications.  
The Decimating filter output is sampled by the programmable  
divider shown in Figure 13. The divider is a counter which is  
decremented each time it is clocked. When the divider reaches  
its terminal count, the output of the decimating filter is sampled.  
The divider may be programmed with a divisor of from 1 to  
4096 (see Table 10 Decimating Filter Configuration Register).  
Which filter is selected, is dependent on the application. It is  
important to utilize these alias responses in calculating the  
filter to be used, so that the signal suppression prediction will  
accurately reflect the digital filter performance.  
Noise Equivalent Bandwidth  
One of two internal clock sources are chosen for the divider  
based on whether a fixed or adjustable sample rate is  
desired. For fixed output sample rates, a clock equal to the  
input sample rate is selected (see Decimating Filter  
Configuration Table 10). For adjustable output sample rates,  
a clock generated by the carry out from the Re-Sampler  
NCO is chosen.  
The noise equivalent bandwidth (B ) performance of the  
N
channel filter is dependent on the combination of Decimation  
Filter and Compensation Filter chosen. For configurations  
using the Integrate and Dump filter, B is constant  
N
regardless of decimation rate. However, for configurations  
which use the third order CIC filter, B converges to a  
N
10  
HSP50110  
Center Frequency Register, and SOF is the 32-bit value  
TO DECIMATING FILTERS  
loaded into the Sample Offset Frequency Register. The SCF  
Register is loaded through the Microprocessor Interface (see  
Microprocessor Interface Section), and the SOF Register is  
loaded serially via the SOF and SOFSYNC inputs (see Serial  
PROGRAMMABLE  
DIVIDER  
MODE †  
SAMPLE PHASE  
OUT CONTROL †  
SSTRB  
SPH0-4  
REG  
Input Section). The sample rate F is a function of the Input  
s
DATARDY  
MUX  
Controller Mode. If the Controller is in Gated Input Mode, F is  
s
the frequency with which ENI is asserted. In Interpolated Input  
Mode, F is the CLK frequency (see Input Controller Section).  
s
SYNC  
CLK  
REG  
32-BIT ADDER  
CARRY OUTPUT  
5
The carry out and 5 of the most significant 8 bits of the  
NCO’s phase accumulator are output to control a resampling  
filter such as the HSP43168. The resampling filter can be  
used to provide finer time (symbol phase) resolution than  
can be achieved by the sampling clock alone. This may be  
needed to improve transmit/receive timing or better, align a  
matched filter’s impulse response with the symbol  
boundaries of a baseband waveform at high symbol rates.  
The carry out of the NCO’s phase accumulator is output on  
SSTRB, and a window of 5 of the 8 most significant 8 bits of  
the Phase Accumulator are output on SPH0-4.  
SHIFTER  
8
0
RE-SAMPLER  
32  
NCO  
REG  
MUX  
LOAD  
RESAMPLER  
NCO †  
+
SOF ENABLE †  
MUX  
32  
32  
0
SOF  
REG  
SCF REG  
SYNC  
Output Formatter  
SOFSYNC  
SOF  
SYNC  
SHIFT REG  
The Output Formatter supports either Word Parallel or Bit  
Serial output modes. The output can be chosen to have a  
two’s complement or offset binary format. The configuration  
is selected by loading the I/O Formatting/Control Register  
(see Table 9).  
SAMPLER  
CENTER  
FREQUENCY †  
LOAD  
ON CF  
WRITE  
† Controlled via microprocessor interface.  
FIGURE 13. RE-SAMPLER  
In parallel output mode, the in-phase and quadrature  
samples are output simultaneously at rates up to the  
maximum CLK. The DATARDY output is asserted on the first  
CLK cycle that new data is available on IOUT0-9 and  
QOUT0-9 as shown in Figure 14. Output enables (OEI,  
OEQ) are provided to individually three-state IOUT0-9 and  
QOUT0-9 for output multiplexing.  
The calculation of the decimation factor depends on whether  
the output sample rate is fixed or adjusted dynamically. For a  
fixed sample rate, the decimation factor is equal to the divisor  
loaded into the programmable divider. For example, if the  
divider is configured with a divisor of 8, the decimation factor  
is 8 (i.e., the output data rate is F /8). If the decimation factor  
s
is adjusted dynamically, it is a function of both the  
programmable divisor and the frequency of carry outs from  
the Re-Sampler NCO (F ) as given by:  
CO  
CLK  
DATARDY  
Decimation Factor =  
(Programmable Divisor) x F /F  
(EQ. 10)  
IOUT9-0/  
QOUT9-0  
s
CO  
For example, if the programmable divisor is 8 and F /F  
s
=
CO  
NOTE: DATARDY may be programmed active high or low.  
40, the decimation factor would be 320.  
FIGURE 14. PARALLEL OUTPUT TIMING  
NOTE: The CIC filter architecture only supports  
decimation factors up to 4096.  
When bit serial output is chosen, two serial output modes are  
provided, Simultaneous I/Q Mode and I Followed by Q Mode.  
In Simultaneous I/Q Mode, the 10-bit I and Q samples are  
output simultaneously on IOUT0 and QOUT0 as shown in  
Figure 15. In I Followed by Q Mode, both samples are output  
on IOUT0 with I samples followed by Q samples as shown in  
Figure 16. In this mode, the I and Q samples are packed into  
separate 16-bit serial words (10 data bits + 6 zero bits). The  
10 data bits are the 10 MSBs of the serial word, and the I  
sample is differentiated from the Q sample by a 1 in the LSB  
position of the 16-bit data word. A continuous serial output  
clock is provided on IOUT9 which is derived by dividing the  
The phase accumulator in the Re-Sampler NCO generates  
the carry outs used to clock the programmable divider. The  
frequency at which carry outs are generated (F ) is  
CO  
determined by the values loaded into the Sampler Center  
Frequency (SCF) and Sampler Offset Frequency (SOF)  
Registers. The relationship between the values loaded into  
these registers and the frequency of the carry outs is given by:  
F
= F x (SCF + SOF)/232  
(EQ. 11)  
CO  
s
where F is the input sample rate of the Low Pass Filter  
s
Section, SCF is the 32-bit value loaded into the Sampler  
11  
HSP50110  
CLK by a programmable factor of 2, 4, or 8. When the  
Gain Distribution  
programmable clock factor is 1, IOUT9 is pulled high, and the  
CLK signal should be used as the clock. The beginning of a  
serial data word is signaled by the assertion of DATARDY one  
serial clock before the first bit of the output word. In I followed  
by Q Mode, DATARDY is asserted prior to each 16-bit data  
word. For added flexibility, the Formatter may be configured to  
output the data words in either MSB or LSB first format.  
The gain distribution in the DQT is shown in Figure 17. These  
gains consist of a combination of fixed, programmable, and  
adaptive gains. The fixed gains are introduced by processing  
elements like the Synthesizer/Mixer and CIC Filter. The  
programmable and adaptive gains are set to compensate for  
the fixed gains as well as variations in input signal strength.  
The bit range of the data path between processing elements  
is shown in Figure 17. The quadrature inputs to the data path  
are 10-bit fractional two’s complement numbers. They are  
multiplied by a 10-bit quadrature sinusoid and rounded to  
IOUT9  
DATARDY  
IOUT0/  
12-bits in the Synthesizer/Mixer. The I and Q legs are then  
-36  
scaled by a fixed gain of 2  
to compensate for the worst  
LSB  
DATARDY LEADS 1st BIT  
MSB  
LSB  
QOUT0  
case gain of the CIC filter. Next, a gain block with an adaptive  
and programmable component is used to set the output signal  
level within the desired range of the 10-bit output (see Setting  
DQT Gains Section). The adaptive component is produced by  
NOTE: Assumes data is being output LSB first.  
FIGURE 15. SERIAL TIMING (SIMULTANEOUS I/Q MODE)  
7
the AGC and has a gain range from 1.0 to 1.9375*2 . The  
programmable component sets the gain range of the CIC  
IOUT9  
0
63  
shifter which may range from 2 to 2 . Care must be taken  
when setting the AGC gain limits and the CIC Shifter gain  
since the sum of these gains could shift the CIC Scaler output  
DATARDY  
IOUT0  
8
-46  
beyond the bit range (-2 to 2 ) of the CIC Filter input. The  
MSB  
LSB  
0
1
MSB  
N
CIC Filter introduces a gain factor given by R where R is the  
I DATA WORD  
Q DATA  
WORD  
I OUTPUT IDENTIFIED  
BY 1 IN LSB OF DATA WORD  
decimation rate of the filter and N is the CIC order. The CIC  
order is either 1 (integrate and dump filter) or 3. Depending on  
configuration, the CIC Filter introduces a gain factor from 2 to  
DATARDY  
LEADS 1st BIT  
0
36  
2
. The output of the CIC Filter is then rounded and limited to  
NOTE: Assumes data is being output MSB first.  
DATARDY may be programmed active high or low.  
1
-9  
an 11-bit window between bit positions 2 to 2 . Values  
outside this range saturate to these 11 bits. The  
FIGURE 16. SERIAL TIMING (I FOLLOWED BY Q MODE)  
Compensation Filter introduces a final gain factor of 1.0, 0.65,  
AGC GAIN  
MANTISSA  
1.0 - 1.9375  
(0.0625 STEPS)  
EXPONENT CIC BARREL  
0
7
SHIFTER  
2 -2  
0
63  
2 -2  
COMPENSATION  
FILTER  
GAIN  
SYNTHESIZER/  
MIXER  
CIC  
SCALER  
CIC  
FILTER  
G = 1.0, 0.65, 0.77  
70  
0
36  
-36  
3
G = 1.0 - 1.9375*2  
G = 2 - 2  
G = 2  
G = 0.9990  
(BYPASS, x/sin(x), (x/sin(x))  
N
(R )  
LIMIT  
= 0dB  
LIMIT  
N
G
= 0dB  
G
= -216.74dB  
G
= G  
G
+
G
= 20log[f /f ]  
G
G
=
G
= 0dB  
dB  
dB  
dB  
dB  
AGC  
SHIFTER  
dB  
S
D
dB  
dB  
3
8
8
-2  
N
-2  
-2  
= 20log[R]  
0dB BYPASS  
-3.74dB  
-2.27dB  
N = 1, 3  
1
1
-2  
-2  
0
0
0
0
0
0
0
2
2
2
-2  
2
-2  
2
BINARY POINT  
OUTPUT  
INPUT  
-1  
-1  
-1  
-1  
-1  
-1  
-1  
2
2
2
2
2
2
2
-35  
-2  
-9  
-10  
-46  
-9  
-9  
-9  
-9  
2
2
2
2
2
2
2
-46  
2
RND  
RND  
RND  
RND  
G = -6.02dB  
BIT RANGE OF DATA PATH  
FIGURE 17. GAIN DISTRIBUTION AND INTERMEDIATE BIT WEIGHTINGS  
12  
HSP50110  
or 0.77 depending on whether the bypass, x/sin(x) or  
(x/sin(x)) configuration is chosen. The Compensation Filter  
NOTE: 10log (x) is used because these items are power  
10  
related.  
3
output is then rounded and limited to a 10-bit output range  
corresponding to bit positions 2 to 2 .  
Thus, the minimum input signal will then be -42.96dB below  
full scale (-30.96dB -12dB for A/D backoff). Note: in this  
example the symbol rate is assumed to be one half of the  
output sample rate (i.e., there are 2 samples per symbol).  
0
-9  
Setting DQT Gains  
The AGC and CIC Shifter gains are programmed to maintain  
the output signal at a desired level. The gain range required  
depends on the signal levels expected at the input and the A/D  
backoff required to prevent signal + noise from saturating the  
A/D. The signal level at the input is based on the input SNR  
which itself is derived from the either output SNR or output  
The output signal is related to the input signal by:  
S
= S x G  
IN MIXER  
x G  
SCALER  
x G  
AGC  
x
(EQ. 13)  
(EQ. 14)  
OUT  
G
x G  
CIC  
x G  
COMP  
SHIFTER  
Using this equation, limits for G  
AGC  
and G  
can be  
SHIFTER  
determined from the minimum and maximum input signal  
conditions as given below (all gains specified in dB):  
E /N . Below are two examples which describe setting the  
S
0
gains using either an output SNR or E /N specification.  
S
0
Min Input Level (Maximum Gain Required):  
In applications based on the transmission of digital data, it is  
useful to specify the DQT’s output in terms of E /N . The  
following example uses this parameter and the others given in  
Table 4 to show how the DQT’s gain settings can be derived.  
S
0
-6.02dB ≥ -42.96 - 6.02 - 216.74 + G  
+ G  
+
AGC  
3 3  
SHIFTER  
6
20 x log((40 x 10 /32 x 10 ) ) - 2.27  
(EQ. 15)  
Max Input Level (Minimum Input Gain Required)  
TABLE 4. EXAMPLE SYSTEM PARAMETERS  
MAIN MENU  
-6.02dB ≤ -12 - 6.02 - 216.74 + G  
+ G +  
SHIFTER  
AGC  
3 3  
6
20 x log((40 x 10 /32 x 10 ) ) - 2.27  
(EQ. 16)  
PARAMETER  
ITEM  
SETTING  
40 MSPS  
32 KSPS  
10MHz  
-3dB  
Input Sample Rate  
(2)  
NOTE: 20log (x) is used because these items are  
10  
amplitude related.  
Output Sample Rate (F  
) (Notes 1, 2)  
(8), (9)  
(10)  
SOUT  
Solving the above inequalities for G  
gain range can be expressed as,  
and G  
, the  
SHIFTER  
AGC  
Input Filter Noise Bandwidth (NBW)  
Minimum Output E /N  
(15)  
S
0
45.20dB < (G  
AGC  
+ G  
) < 76.16dB.  
(EQ. 17)  
SHIFTER  
Signal + Noise Backoff at A/D Input  
Output Signal Magnitude (0 to 1)  
Number of CIC stages  
(18), (19)  
(21)  
12dB  
The shifter gain provides a programmable gain which is a  
factor of 2. Since G ≥ 1.0, G is set as close to  
the minimum gain requirement as possible:  
0.5  
AGC  
SHIFTER  
(11)  
3
N
G
= 2 ,  
(EQ. 18)  
SHIFTER  
3
Compensation Filter  
(11)  
(x/sin(x))  
where  
Noise Eq. Bandwidth of Comp. Filter  
N/A  
34.18kHz  
Real  
(G  
/20)  
(B *F  
)
SOUT  
N = floor(log (10 MIN ))  
2
N
(45.20/20)  
= floor(log (10  
2
)) = 7  
Input Type (Real/Complex)  
(4)  
The limits on the AGC gain can then be determined by  
NOTES:  
1. Two samples per symbol assumed.  
2. Decimation = 40 MSPS/32 KSPS = 1250.  
substituting the shifter gain into Equation 18 above. The  
resulting limits are given by:  
First, the maximum and minimum input signal levels must be  
determined. The maximum input signal level is achieved in a  
noise free environment where the input signal is attenuated by  
12dB as a result of the A/D backoff. The minimum input signal  
3.05dB < G  
AGC  
<34.02dB.  
(EQ. 19)  
In some applications it is more desirable to specify the DQT  
output in terms of SNR. This example, covers derivation of  
the gain settings based on an output SNR of 15dB. The  
other system parameters are given in Table 4.  
is determined by converting the minimum output E /N  
S
0
specification into an Input SNR. Using the example parameters  
As in the previous examples the minimum and maximum  
input signal levels must be determined. The minimum input  
signal strength is determined by from the minimum output  
SNR as given by:  
in Table 4 the minimum input SNR is given by:  
SNR = 10log (E /N ) + 10log (Symbol Rate)  
IN 10 10  
S
0
-10log (NBW)  
10  
3
6
= -3dB + 10log (0.5x32 x 10 ) - 10log (10 x 10 )  
10 10  
SNR = SNR  
IN OUT  
- 10log(NBW) + 10log(B x F  
)
SOUT  
N
= -30.96dB  
(EQ. 12)  
6
3
= 15 - 10log(10 x 10 ) + 10log(34.18 x 10 )  
= -9.66dB  
(EQ. 20)  
13  
HSP50110  
Thus, the minimum input signal will be -21.66dB below full  
scale (-9.66 -12 for A/D Backoff). As before the maximum  
input signal in the absence of noise is -12dB down due to  
A/D backoff.  
Basic Architectural Configurations  
Detailed architectural diagrams are presented in Figures 18  
through 20 for the basic configurations, Integrate/Dump filtering  
with optional compensation, 3rd Order CIC filtering with  
optional compensation, and Decimating Filter bypass. Only one  
of the data paths is shown since the processing on either the  
inphase or quadrature legs is identical. These diagrams are  
useful for determining the throughput pipeline delay or the loop  
delay of the AGC as all the internal registers are shown.  
From Equation 14, the gain relationships for maximum and  
minimum input can be written as follows:  
Min Input Level  
-6.02dB ≥ -21.66 -6.02 - 216.74 + G  
+ G +  
SHIFTER  
AGC  
6
3 3  
20*log((40 x 10 /32 x 10 ) )-2.27  
(EQ. 21)  
All registers with the exception of those denoted by daggers (†)  
are enabled every CLK rate to minimize pipeline latency. The  
registers marked by daggers are enabled at the output sample  
rate as required by the filtering operation performed. The Loop  
Filter accumulator in the AGC is enabled once per output  
sample, and represents a delay of one output sample. The  
accumulators in the CIC filter each represent a delay of one  
CLK, but they are enabled for processing once per input  
sample. In Interpolated Input Mode the accumulators are  
enabled every CLK since the sample rate is determined by the  
CLK rate (see Input Controller Section). In Gated Input Mode,  
the processing delay of the accumulators is one CLK but they  
are only enabled once for each sample gated into the  
processing pipeline. As a result, the latency through the  
accumulators is 3 CLKs rather than 3 input sample periods  
when configured as a 3rd order CIC filter.  
Max Input Level  
-6.02dB ≤ -12 - 6.02 - 216.74 + G  
+ G +  
SHIFTER  
AGC  
3 3  
6
20 x log((40 x 10 /32 x 10 ) ) -2.27  
(EQ. 22)  
Using the upper and lower limits found above, the gain range  
can be expressed as,  
45.20dB < G  
AGC  
+ G  
SHIFTER  
< 54.86dB.  
(EQ. 23)  
Using Equation 2 in the previous example, the shifter gain is  
determined to be 2 , resulting in an AGC gain range of 3.05dB  
7
< G  
<12.72dB.  
(EQ. 24)  
AGC  
14  
†
LEGEND:  
MANTISSA (1.0 - 1.9375)  
0
R R  
E E  
G G  
HI/LO  
R
E
G
ACCUMULATOR  
W/ PROGRAMMABLE  
LIMITS  
ACC = ACCUMULATOR  
LMT = LIMIT  
LEVEL  
DETECT  
7
EXPONENT (2 - 2 )  
SIN/COS  
VECTOR FROM  
CARRIER NCO  
CIC SCALER  
R
= DOWN SAMPLER  
LEVEL  
DETECT  
-36  
CIC SHIFTER  
LOOP  
GAIN  
2
MUX = MULTIPLEXER  
REG = REGISTER  
0
-63  
+
2 -2  
REG  
REG  
IIN0-9/  
QIN0-9  
€† INDICATES ELEMENTS RUNNING  
1ST ORDER CIC (I & D FILTER)  
COMPENSATION  
FILTER  
R
E
G
R
E
G
R R R  
E E E  
G G G  
A
C
C
AT THE OUTPUT SAMPLE RATE  
R
X
31  
SERIALIZE  
-1  
1
COMPLEX  
MULTIPLIER  
†
†
R
E
G
FROM  
PROGRAMMABLE  
DIVIDER  
L
M
T
M
U
X
L
M
T
M
U
X
R R R R R  
E E E E E  
G G G G G  
IOUT0-9/  
QOUT0-9  
11 TAP  
FIR FILTER  
+
FIGURE 18. DATA FLOW FOR INTEGRATE/DUMP CONFIGURATION  
†
LEGEND:  
MANTISSA (1.0 - 1.9375)  
R R  
E E  
G G  
HI/LO  
R
E
G
ACCUMULATOR  
W/ PROGRAMMABLE  
LIMITS  
LEVEL  
DETECT  
ACC = ACCUMULATOR  
LMT = LIMIT  
0
7
EXPONENT (2 - 2 )  
SIN/COS  
VECTOR FROM  
CARRIER NCO  
CIC SCALER  
CIC SHIFTER  
R
= DOWN SAMPLER  
LEVEL  
DETECT  
LOOP  
GAIN  
-36  
0
-63  
2
+
2 -2  
MUX = MULTIPLEXER  
REG = REGISTER  
(TOP BITS ALIGNED)  
REG  
REG  
3RD ORDER CIC FILTER  
COMPENSATION  
FILTER  
IIN0-9/  
QIN0-9  
€† INDICATES ELEMENTS RUNNING  
R
E
G
R
E
G
R R R  
E E E  
G G G  
A
C
C
A
C
C
A
C
C
AT THE OUTPUT SAMPLE RATE  
R
X
55  
-1  
3
-3  
1
SERIALIZE  
IOUT0-9/  
COMPLEX  
MULTIPLIER  
†
R
E
G
†
†
R
E
G
†
FROM  
BIT RATE  
NCO  
QOUT0-9  
R
E
G
L
M
T
M
U
X
L
M
T
M
U
X
R R R R R  
E E E E E  
G G G G G  
15 TAP  
FIR FILTER  
+
+
+
FIGURE 19. DATA FLOW FOR 3RD ORDER CIC CONFIGURATION  
LEGEND:  
MANTISSA (1.0 - 1.9375)  
0
ACC = ACCUMULATOR  
LMT = LIMIT  
R
E
G
ACCUMULATOR  
W/ PROGRAMMABLE  
LIMITS  
LEVEL  
DETECT  
R R  
E E  
G G  
HI/LO  
7
EXPONENT (2 - 2 )  
R
= DOWN SAMPLER  
MUX = MULTIPLEXER  
REG = REGISTER  
SIN/COS  
VECTOR FROM  
CARRIER NCO  
LOOP  
GAIN  
CIC SCALER  
REG  
REG  
LEVEL  
DETECT  
-36  
2
CIC SHIFTER  
SERIALIZE  
+
COMPENSATION  
FILTER  
0
-63  
2 -2  
IIN0-9/  
QIN0-9  
R
E
G
R
E
G
R R R  
E E E  
G G G  
L
M
T
M
U
X
L
M
T
M
U
X
R R R R R  
E E E E E  
G G G G G  
IOUT0-9/  
QOUT0-9  
11-15 TAP  
X
FIR FILTER  
21  
COMPLEX  
MULTIPLIER  
FIGURE 20. DATA FLOW WITH CIC STAGE BYPASSED  
HSP50110  
32-bit holding register and the LSBs of the holding register will  
Serial Input Interfaces  
be zeroed. See Figure 22 for details. Note: serial data must  
be loaded MSB first, and COFSYNC or SOFSYNC should  
not be asserted for more than one CLK cycle.  
Frequency control data for the NCOs contained in the  
Synthesizer/Mixer and the Re-Sampler are loaded through two  
separate serial interfaces. The Carrier Offset Frequency  
Register controlling the Synthesizer NCO is loaded via the COF  
and COFSYNC pins. The Sample Offset Frequency Register  
controlling the Re-Sampler NCO is loaded via the SOF and  
SOFSYNC pins.  
Test Mode  
The Test Mode is used to program each of the output pins to  
“high” or “low” state via the Microprocessor Interface. If this  
mode is enabled, the output pins are individually set or  
cleared through the control bits of the Test Register in Table  
13. When serial output mode is selected, the Test Register  
may be used to set the state of the unused output bits.  
CLK  
COFSYNC/  
SOFSYNC  
COF/  
SOF  
Microprocessor Interface  
MSB  
LSB MSB  
The Microprocessor Interface is used for writing data to the  
DQT’s Control Registers and reading the contents of the  
AGC Loop accumulator (see AGC Section). The  
OTE: Data must be loaded MSB first.  
IGURE 21. SERIAL INPUT TIMING FOR COF AND SOF INPUTS  
Microprocessor Interface consists of a set of four 8-bit  
holding registers and one 8-bit Address Register. These  
registers are accessed via a 3-bit address bus (A0-2) and an  
8-bit data bus (C0-7). The address map for these registers is  
given in Table 5. The registers are loaded by setting up the  
address (A0-2) and data (C0-7) to the rising edge of WR.  
32†  
30  
28  
26  
ASSERTION OF  
COFSYNC, SOFSYNC  
24†  
22  
20  
18  
16†  
14  
12  
10  
8†  
6
4
2
0
DATA TRANSFERRED  
TO HOLDING REGISTER  
TABLE 5. ADDRESS MAP FOR MICROPROCESSOR  
INTERFACE  
(8)  
(24) (32)  
A2-0  
REGISTER DESCRIPTION  
(16)  
0
Holding Register 0. Transfers to bits 7-0 of the 32-bit Desti-  
nation Register. Bit 0 is the LSB of the 32-bit register.  
2
6
10 14 18 22 26 30 34 38 42 46 50 54  
1
2
3
4
Holding Register 1. Transfers to bits 15-8 of a 32-bit Destina-  
tion Register.  
CLK TIMES  
T ††  
D
T ††  
D
Holding Register 2. Transfers to bits 23-16 of a 32-bit Desti-  
nation Register.  
T ††  
D
T ††  
D
Holding Register 3. Transfers to bits 31-24 of a 32-bit  
Destination Register. Bit 31 is the MSB of the 32-bit register.  
Serial word width can be: 8, 16, 24, 32 bits wide.  
† T is determined by the COFSYNC, COFSYNC rate. Note that  
D
T
can be 0, and the fastest rate is with 8-bit word width.  
This is the Destination Address Register. On the fourth CLK  
following a write to this register, the contents of the Holding  
Registers are transferred to the Destination Register. The  
lower 4 bits written to this register are decoded into the Des-  
tination Register address. The destination address map is  
given in Tables 6-15.  
D
FIGURE 22. SERIAL DATA LOAD TO HOLDING REGISTERS  
SEQUENCE  
The procedure for loading data through these two pin  
interfaces is identical. Each serial word has a programmable  
word width of either 8, 16, 24, or 32 bits (see Chip  
The HSP50110 is configured by loading a series of nine 32-bit  
Control Registers via the Microprocessor Interface. A Control  
Register is loaded by first writing the four 8-bit Holding  
Registers and then writing the destination address to the  
Address Register as shown in Figure 23. The Control  
Register Address Map and bit definitions are given in Tables  
6-15. Data is transferred from the Holding Registers to a  
Control Register on the fourth clock following a write to the  
Address Register. As a result, the Holding Registers should  
not be updated any sooner than 4 CLK’s after an Address  
Register write (see Figure 23). NOTE: the unused bits in a  
Control Register need not be loaded into the Holding  
Register.  
Configuration Register in Table 11). On the rising edge CLK,  
data on COF or SOF is clocked into an Input Shift Register.  
The beginning of a serial word is designated by asserting  
either COFSYNC or SOFSYNC “high” one CLK prior to the  
first data bit as shown in Figure 21. The assertion of the  
SOFSYNC starts a count down from the programmed word  
width. On following CLKs, data is shifted into the register until  
the specified number of bits have been input. At this point data  
shifting is disabled and the contents of the register are  
transferred from the Shift Register to the respective 32-bit  
Holding Register. The Shift Register is enabled to accept new  
data on the following CLK. If the serial input word is defined to  
be less than 32 bits, it will be transferred to the MSBs of the  
16  
HSP50110  
For added flexibility, the CFLD input provides an alternative  
Configuration Register can be loaded one CLK after CFLD  
has been loaded on the rising edge of CLK.  
mechanism for transferring data from the Microprocessor  
Interfaces’s Holding Registers to the Center Frequency  
Register. When CFLD is sampled “high” by the rising edge  
of clock, the contents of the Holding Registers are  
transferred to the Center Frequency Register as shown in  
Figure 23. Using this loading mechanism, an update of the  
Center Frequency Register can be synchronized with an  
external event. Caution should be taken when using the  
CFLD since the Holding Register contents will be  
transferred to the Center Frequency Register whenever  
CFLD is asserted. NOTE: CFLD should not be asserted  
any sooner than 2 CLK’s following the last Holding  
Register load. As Shown in Figure 24, the next  
The Microprocessor Interface can be used to read the upper  
8 bits of the AGC Loop Filter Accumulator. The procedure for  
reading the Loop Accumulator consists of first sampling the  
loop accumulator by writing 9 to the Destination Address  
Register and then reading the loop accumulator value on  
C0-7 by asserting RD. The sampled value is enabled for  
output on C0-7 by forcing RD “low” no sooner than 6 CLK’s  
after the writing the Destination Register as shown in  
Figure 25. The 8-bit output corresponds to the 3 exponent  
bits and 5 fractional bits to the right of the binary point (see  
Figure 3). The 3 exponent bits map to C7-5 with C7 being  
the most significant. The fractional bits map to C4-0 in  
decreasing significance from C4 to C0.  
WR  
RD  
DON’T CARE  
0
1
2
3
4
0
1
A0-2  
C0-7  
CLK  
1
2
3
4
LOAD  
CONFIGURATION  
DATA  
LOAD ADDRESS OF  
TARGET CONTROL  
REGISTER AND  
WAIT 4 CLKs  
LOAD NEXT  
CONFIGURATION  
REGISTER  
EARLIEST TIME  
ANOTHER LOAD  
CAN BEGIN  
NOTE: These processor signals are representative. The actual shape of the waveforms will be set by the microprocessor used. Verify that the mi-  
croprocessor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. While the microprocessor  
waveforms are not required to be synchronous to CLK, they are shown as synchronous waveforms for clarity in the illustration.  
FIGURE 23. CONTROL REGISTER LOADING SEQUENCE  
1
4
5
6
2
3
1
2
CLK  
WR  
CLK  
WR  
RD  
CFLD  
A0-2  
C0-7  
DON’T CARE  
A0-2  
C0-7  
4
9
0
1
2
3
0
1
2
3
THREE-STATE  
INPUT BUS  
LOAD ADDRESS  
OF TARGET  
CONTROL REGISTER  
AND WAIT 6 CLK’S  
LOAD NEXT  
CONFIGURATION  
REGISTER  
ASSERT RD  
TO ENABLE DATA  
OUTPUT ON C0-7  
LOAD  
CONFIGURATION  
DATA  
NEXT CLK  
FOLLOWING  
CFLD  
NOTE: These processor signals are meant to be representative.  
The actual shape of the waveforms will be set by the microprocessor  
used. Verify that the processor waveforms meet the parameters in  
the Waveforms Section of this data sheet to ensure proper operation.  
The Processor waveforms are not required to be synchronous to  
CLK. They are shown that way to clarify the illustration.  
NOTE: These processor signals are meant to be representative.  
The actual shape of the waveforms will be set by the microprocessor  
used. Verify that the processor waveforms meet the parameters in  
the Waveforms Section of this data sheet to ensure proper operation.  
The Processor waveforms are not required to be synchronous to  
CLK. They are shown that way to clarify the illustration.  
FIGURE 24. CENTER FREQUENCY CONTROL REGISTER  
LOADING SEQUENCE USING CF LOAD  
FIGURE 25. AGC READ SEQUENCE  
17  
HSP50110  
TABLE 6. CENTER FREQUENCY REGISTER  
DESTINATION ADDRESS = 0  
BIT  
POSITIONS  
FUNCTION  
DESCRIPTION  
31-0  
Center Frequency  
This register controls the center frequency of the Synthesizer/Mixer NCO. This 32-bit two’s complement  
value sets the center frequency as described in the Synthesizer/Mixer Section. Center  
F
32  
C
F
S
˙
– COF  
H
-------  
Center Frequency = CF  
=
2
H
H
Format: [XXXXXXXX]H  
Range: (0000000 - FFFFFFF)H.  
TABLE 7. SAMPLER CENTER FREQUENCY REGISTER  
DESTINATION ADDRESS = 1  
BIT  
POSITION  
FUNCTION  
DESCRIPTION  
31-0  
Sampler Center  
Frequency  
This register controls the center frequency of the Re-Sampler NCO. This 32-bit value together with the  
setting of a programmable divider set the decimation factor of the CIC Filter (see Re-Sampler and Low  
Pass Filter Sections).  
F
32  
NCO  
F
S
---------------  
SamplerCenter Frequency = SCF  
=
2
–SCOF  
H.  
H
H
Format: [XXXXXXXX]H  
Range: (0000000 - FFFFFFF)H.  
TABLE 7. INPUT THRESHOLD REGISTER  
DESTINATION ADDRESS = 2  
BIT  
POSITION  
FUNCTION  
DESCRIPTION  
7-0  
Input Level Detector  
Threshold  
This register sets the magnitude threshold for the Input Level Detector (see Input Level Detector Section).  
This 8-bit value is a fractional unsigned number whose format is given by:  
0
-1 -2 -3 -4 -5 -6 -7  
2 . 2  
2
2
2
2
2
2 .  
The possible threshold values range from 0 to 1.9961 (00 - FF) . The magnitude range for complex inputs  
H
is 0.0 - 1.4142 while that for real inputs is 0.0 - 1.0. Threshold values of greater than 1.4142 will never be  
exceeded.  
31-8  
Reserved.  
TABLE 8. AGC CONTROL REGISTER  
DESTINATION ADDRESS = 3  
BIT  
POSITION  
FUNCTION  
DESCRIPTION  
7-0  
AGC Level Detector  
Threshold  
Magnitude threshold for the AGC Level Detector (see AGC Section). The magnitude threshold is repre-  
sented as an 8-bit fractional unsigned value with the following format:  
0
-1 -2 -3 -4 -5 -6 -7  
2 . 2  
2
2
2
2
2
2 .  
The possible threshold values range from 0 to 1.9961. However, the usable range of threshold values  
span from 0 to 1.4142, since full scale outputs on both I and Q correspond to a magnitude of  
2
2
I
+ Q  
=
2 = 1.4142 . Threshold values of greater than 1.4142 will force the AGC gain to the upper limit.  
15-8  
Loop Filter Upper Limit Upper limit for Loop Filter’s accumulator (see AGC Section). The three most significant bits are the expo-  
(Maximum Gain)  
nent and the five least significant bits represent the mantissa (see Figure 3). The three exponent bits map  
to bit positions 15-13 (15 is the MSB) and the five mantissa bits map to bit positions 12-8 (12 is the MSB).  
(EEE.MMMMM)  
2.  
23-16  
31-24  
Loop Filter Lower Limit Lower limit for Loop Filter’s accumulator (see AGC Section). The format is the same as that for the upper  
(Minimum Gain)  
limit described above. The 3 exponent bits map to bit positions 23-21 (23 is the MSB) and the mantissa  
bits map to bit positions 20-16 (20 is the MSB). (EEE.MMMMM)  
2.  
Programmable Loop  
Gain  
Programmable part of Loop Gain word (see AGC Section). The Loop Gain value increments or decre-  
-6 -13  
ments the Loop Filter’s Accumulator at bit positions 2 through 2  
gain is loaded into bit positions 31-24 (31 is the MSB and maps to the 2 position in the Accumulator).  
(GGGGGGGG)  
as shown in Figure 3. The 8-bit loop  
-6  
2.  
18  
HSP50110  
TABLE 9. I/O FORMATTING/CONTROL  
DESTINATION ADDRESS = 4  
BIT  
POSITION  
FUNCTION  
Input Format  
DESCRIPTION  
0
1
2
0 = Two’s complement input format, 1 = Offset binary input format.  
Note: if a real input with offset binary weighting is used, the unused quadrature input pins should be tied  
to 1000000000.  
Input Mode  
0 = Input Controller operates in Interpolated Input Mode.  
1 = Input Controller operates in Gated Input Mode.  
(See Input Controller Section).  
Serial/Parallel Output  
Select  
1 = Serial Output, 0 = Parallel Output. (See Output Formatter Section).  
3
Test Enable  
0 = Test Mode Disabled, 1 = Test Mode Enabled. (See Test Mode Section).  
5-4  
Serial Output Clock  
Select  
Bits 5-4  
0 0  
Serial Output Clock Rate  
CLK (Serial Output Clock Pin = High)  
0 1  
Clk/2  
1 0  
1 1  
CLK/4  
CLK/8  
(See Output Formatter Section).  
6
7
Serial Output Mode  
1 = I Followed by Q Mode, 0 = Simultaneous I and Q Mode. (See Output Formatter Section)  
1 = MSB First, 0 = LSB First.  
Serial Output Word  
Orientation  
8
9
Output Data Format  
DATARDY Polarity  
1 = Offset Binary, 0 = Two’s Complement.  
1 = Active Low, 0 = Active High.  
This applies to both serial and parallel output modes. (See Output Formatter Section).  
10  
Output Clock Polarity  
1 = High to Low clock transition at midsample.  
0 = Low to High clock transition at midsample.  
31-11  
Reserved.  
TABLE 10. DECIMATING FILTER CONFIGURATION REGISTER  
DESTINATION ADDRESS = 5  
BIT  
POSITION  
FUNCTION  
DESCRIPTION  
N
5-0  
CIC Shifter Gain  
These 6 bits set the fixed gain of the CIC shifter. The gain factor is of the form, 2 , where N is the valued  
0
63  
stored in this location. A gain range from 2 to 2 is provided. Since the CIC shifter sets the signal level  
at the input to the CIC FIlter, care must be taken so that the signal is not shifted outside of the input bit  
range of the filter. (See Gain Distribution Section).  
17-6  
Programmable  
Divider  
These 12 bits specify the divisor for the programmable divider in the Re-Sampler. The actual divisor is  
equal to the 12-bit value +1 for a total range of 1 to 4096. For example, a value of 7 would produce a  
sampling rate of 1/8 the CLK or 1/8 the carry-out frequency of the Re-Sampler NCO depending on con-  
figuration.  
(See Re-Sampler).  
SOURCE  
CLK  
ReSampler  
PROGRAMMABLE DIVIDER RANGE  
1-4096  
2-4096  
18  
Programmable  
Divider Clock Source  
1 = Divider clocked at sample rate of data input to the Low Pass Filter.  
0 = Divider clocked by Re-Sampler NCO.  
(See Re-Sampler).  
20-19  
CIC Filter  
0 0 3 stage CIC filter.  
Configuration  
0 1 1 stage CIC (Integrate and dump) filter.  
1 X bypass CIC.  
When a 3 stage CIC filter is chosen, a decimation factor >3 must be used if the Re-Sampler NCO is used  
to set the output sampling rate. (See Re-Sampler Section and Low Pass Filtering Section).  
22-21  
Compensation  
Filtering  
0 0 x/sinx filtering.  
0 1 (x/sinx) filtering.  
3
1 X bypass compensation filter.  
(See Low Pass Filtering Section).  
19  
HSP50110  
TABLE 10. DECIMATING FILTER CONFIGURATION REGISTER (Continued)  
DESTINATION ADDRESS = 5  
BIT  
POSITION  
FUNCTION  
DESCRIPTION  
31-23  
Reserved.  
TABLE 11. CHIP CONFIGURATION REGISTER  
DESTINATION ADDRESS = 6  
BIT  
POSITION  
FUNCTION  
DESCRIPTION  
0
HI/LO Output Sense  
1 = HI/LO output of 1 means input > threshold.  
0 = HI/LO output of 1 means input ≤ threshold.  
(See Input Level Detector Section).  
1
2
AGC Disable  
1 = AGC disabled, gain forced to 1.0 (0dB), 0 = Normal operation.  
(See AGC Section).  
AGC Level Detector  
Sense  
1 = Error signal is 1 when output > threshold, -1 otherwise.  
0 = Error signal is -1 when output > threshold, 1 otherwise.  
Set to 0 for normal operation. (See AGC Section).  
4-3  
6-5  
Carrier Offset  
Frequency Word Width 0 1 = 16 bits  
1 0 = 24 bits  
0 0 = 8 bits  
1 1 = 32 bits  
(See Synthesizer/Mixer Section).  
Sample Rate Offset  
0 0 = 8 bits  
Frequency Word Width 0 1 = 16 bits  
1 0 = 24 bits  
1 1 = 32 bits  
(See Re-Sampler Section).  
7
8
9
Carrier Offset  
Frequency Enable  
1 = Enable Offset Frequency, 0 = Zero Offset Frequency.  
(See Synthesizer/Mixer Section).  
Sample Rate Offset  
Frequency Enable  
1 = Enable Offset Frequency, 0 = Zero Offset Frequency.  
(See Re-Sampler Section).  
Load Synthesizer NCO 1 = Accumulation enabled.  
0 = Feedback in accumulator is zeroed.  
(See Synthesizer/Mixer Section) Set to 1 for normal operation.  
10  
Load Re-Sampler NCO 1 = Accumulation enabled.  
0 = Feedback in accumulator is zeroed.  
(See Re-Sampler Section) Set to 1 for normal operation.  
12-11  
Sample Phase Output Selects 5 of the 8 MSBs of the Re-Sampler NCO’s phase accumulator for output on SPH0-4. (See Re-  
Select  
Sampler Section).  
0 0 Bits 28:24.  
0 1 Bits 29:25.  
1 0 Bits 30:26.  
1 1 Bits 31:27.  
13  
14  
Sample Phase  
Output Control  
Selects whether the sample phase output pins and SSTRB update continuously or only when the DA-  
TARDY is active. (See Re-Sampler Section).  
1 = Continuous Update.  
0 = Updated by DATARDY.  
Clear Accumulators  
Writing a 1 to the Clear Accumulator bit forces the contents of all accumulators to 0. Accumulators will  
remain at 0 until a 0 is written to this bit. The following accumulators are affected by this bit.  
• Carrier NCO Accumulator  
• Cascode CIC Filter Accumulator  
• AGC Loop Filter Accumulator  
• Serial Output Shifter Counter  
• Serial Output Clock Logic  
• ReSampler NCO Carry Output Programmable Divider  
31-15  
Reserved.  
20  
HSP50110  
TABLE 12. PHASE OFFSET REGISTER  
DESTINATION ADDRESS = 7  
BIT  
POSITION  
FUNCTION  
Phase Offset  
DESCRIPTION  
7-0  
This 8 bit two’s complement value specifies a carrier phase offset of π(n/128) where n is the two’s com-  
plement value. This provides a range of phase offsets from -π to π*(127/128). (See Synthesizer/Mixer  
Section).  
31-8  
Reserved.  
TABLE 13. TEST REGISTER  
DESTINATION ADDRESS = 8  
BIT  
POSITION  
FUNCTION  
Force SPH4-0  
DESCRIPTION  
4-0  
When Test Mode enabled*, SPH4-0 is forced to the values programmed in these bit locations. Bit position  
4 maps to SPH4. (See Test Mode Section).  
5
6
Force SSTRB  
Force HI/LO  
When Test Mode enabled*, SSTRB is forced to state of this bit.  
When Test Mode enabled*, HI/LO is forced to state of this bit.  
16-7  
Force IOUT9-0  
When Test Mode enabled*, IOUT9-0 if forced to the values programmed in these bit locations. Bit position  
16 maps to IOUT9.  
17  
18  
Force DATARDY  
Force LOTP  
When Test Mode enabled*, DATARDY is forced to state of this bit.  
When Test Mode enabled*, LOTP is forced to state of this bit.  
28-19  
Force QOUT9-0  
When Test Mode enabled*, QOUT9-0 is forced to the values programmed in these bit locations. Bit posi-  
tion 16 maps to QOUT9.  
31-29  
Reserved.  
* Test Mode Enable is Destination Address = 4, bit-3.  
TABLE 14. AGC SAMPLE STROBE REGISTER  
DESTINATION ADDRESS = 9  
BIT  
POSITION  
FUNCTION  
AGC Read  
DESCRIPTION  
7-0  
Writing this address samples the accumulator in the AGC’s Loop Filter. The procedure for reading the  
sampled value out of the part on C0-7 is discussed in the Microprocessor Interface Section. (See Micro-  
processor Interface Section).  
References  
[1] Hogenauer, Eugene, “An Economical Class of Digital  
Filters for Decimation and Interpolation”, IEEE  
Transactions on Acoustics, Speech and Signal  
Processing, Vol. ASSP-29 No. 2, April 1981.  
[2] Samueli, Henry “The Design of Multiplierless FIR filters  
for Compensating D/A Converter Frequency Response  
Distortion”, IEEE Transaction Circuits and Systems,  
Vol. 35, No. 8, August 1988.  
21  
HSP50110  
Absolute Maximum Ratings  
Thermal Information (Typical)  
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V  
Input, Output Voltage . . . . . . . . . . . . . . . . .GND -0.5V to V +0.5V  
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 3  
Thermal Resistance (Typical, Note 3)  
θ
( C/W)  
JA  
CC  
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
23  
o
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C  
o
o
Maximum Storage Temperature. . . . . . . . . . . . . . . . -65 C to 150 C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C  
o
Operating Conditions  
(PLCC - Lead Tips Only)  
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.75V to +5.25V  
Temperature Range  
o
o
Die Characteristics  
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C  
o
o
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C  
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38,000 Gates  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
3. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
o
o
o
o
DC Electrical Specifications  
PARAMETER  
V
= 5.0V ±5%, T = 0 to 70 C Commercial, T = -40 to 85 C Industrial  
CC  
A
A
SYMBOL  
TEST CONDITIONS  
MIN  
MAX  
UNITS  
Power Supply Current  
I
V
= Max, CLK = 52.6MHz  
-
350  
mA  
CCOP  
CC  
Notes 4, 5  
Standby Power Supply Current  
Input Leakage Current  
Output Leakage Current  
Clock Input High  
I
V
V
V
V
V
V
V
= Max, Outputs Not Loaded  
-
-10  
-10  
3.0  
-
500  
10  
10  
-
µA  
µA  
V
CCSB  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
I
= Max, Input = 0V or V  
= Max, Input = 0V or V  
= Max, CLK  
I
CC  
I
O
CC  
V
V
IHC  
Clock Input Low  
V
= Min, CLK  
0.8  
-
V
ILC  
Logical One Input Voltage  
Logical Zero Input Voltage  
Logical One Output Voltage  
Logical Zero Output Voltage  
Input Capacitance  
V
= Max  
2.0  
-
V
IH  
V
= Min  
0.8  
-
V
IL  
V
I
I
= -400µA, V  
= Min  
2.6  
-
V
OH  
OH  
OL  
CC  
V
= 2mA, V  
CC  
= Min  
0.4  
10  
10  
V
OL  
C
CLK = 1MHz  
All measurements referenced to GND.  
-
pF  
pF  
IN  
Output Capacitance  
C
-
o
OUT  
T
= 25 C, Note 6  
A
NOTES:  
4. Power supply current is proportional to frequency. Typical rating is 7mA/MHz.  
5. Output load per test circuit and C = 40pF.  
L
6. Not tested, but characterized at initial design and at major process/design changes.  
o
o
o
o
AC Electrical Specifications Note 8, V = 5.0V ±5%, T = 0 to 70 C Commercial, T = -40 to 85 C Industrial  
CC  
A
A
-52 (52.6MHz)  
PARAMETER  
SYMBOL  
NOTES  
MIN  
MAX  
UNITS  
ns  
CLK Period  
CLK High  
CLK Low  
T
T
19  
7
-
-
-
-
CP  
ns  
CH  
T
7
ns  
CL  
Setup Time IIN9-0, QIN9-0, ENI, PH1-0, CFLD, COF, SOF, COFSYNC,  
and SOFSYNC to CLK  
T
7
ns  
DS  
Hold Time IIN9-0, QIN9-0, ENI, PH1-0, CFLD, COF, SOF,  
COFSYNC, and SOFSYNC from CLK  
T
1
-
ns  
DH  
Setup Time A0-2, C0-7 to Rising Edge of WR  
Hold Time A0-2, C0-7 from Rising Edge of WR  
T
T
15  
0
-
-
ns  
ns  
WS  
WH  
22  
HSP50110  
o
o
o
o
AC Electrical Specifications Note 8, V = 5.0V ±5%, T = 0 to 70 C Commercial, T = -40 to 85 C Industrial (Continued)  
CC  
A
A
-52 (52.6MHz)  
PARAMETER  
SYMBOL  
NOTES  
MIN  
MAX  
UNITS  
ns  
CLK to IOUT9-0, QOUT9-0, DATARDY, LOTP, SSTRB, SPH4-0, HI/LO  
T
-
16  
16  
16  
-
8
-
DO  
WR High  
T
ns  
WRH  
WR Low  
T
-
ns  
WRL  
RD Low  
T
-
ns  
RDL  
RDO  
ROD  
RD LOW to Data Valid  
RD HIGH to Output Disable  
Output Enable  
WR to CLK  
T
T
15  
8
8
-
ns  
Note 8  
-
ns  
T
-
ns  
OE  
T
Note 9  
Note 8  
Note 8  
8
ns  
WC  
Output Disable Time  
Output Rise, Fall Time  
NOTES:  
T
-
8
3
ns  
OD  
T
-
ns  
RF  
7. AC tests performed with C = 40pF, I = 2mA, and I  
OL OH  
= -400µA. Input reference level for CLK is 2.0V, all other inputs 1.5V.  
L
Test V = 3.0V, V  
= 4.0V, V = 0V.  
IH  
IHC  
IL  
8. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.  
9. Set time to ensure action initiated by WR or SERCLK will be seen by a particular clock.  
AC Test Load Circuit  
S1  
DUT  
C †  
L
±
IOH  
1.5V  
IOL  
EQUIVALENT CIRCUIT  
SWITCH S1 OPEN FOR I  
CCSB  
AND I  
CCOP  
† Test head capacitance.  
23  
HSP50110  
Waveforms  
t
CP  
t
t
CH  
CL  
CLK  
t
t
DS  
DH  
IIN9-0, QIN9-0,  
ENI, PH1-0,  
CFLD, COF,  
SOF, COFSYNC,  
SOFSYNC  
t
t
WRH  
WRL  
IOUT9-0, QOUT9-0,  
WR  
DATARDY, LOTP,  
SSTRB, SPH4-0,  
HI/LO  
t
DO  
t
t
WS  
WH  
t
WC  
C0-7, A0-2  
WR  
FIGURE 26. TIMING RELATIVE TO WR  
FIGURE 27. TIMING RELATIVE TO CLK  
OEI  
OEQ  
1.5V  
1.5V  
t
OD  
t
OE  
t
RF  
t
RF  
1.7V  
1.3V  
OUTI9-0  
OUTQ9-0  
2.0V  
0.8V  
FIGURE 28. OUTPUT RISE AND FALL TIMES  
FIGURE 29. OUTPUT ENABLE/DISABLE  
t
RDL  
RD  
C0-7  
t
t
ROD  
RDO  
FIGURE 30. TIMING RELATIVE TO READ  
24  
HSP50110  
Plastic Leaded Chip Carrier Packages (PLCC)  
0.042 (1.07)  
0.048 (1.22)  
N84.1.15 (JEDEC MS-018AF ISSUE A)  
0.042 (1.07)  
0.056 (1.42)  
0.004 (0.10)  
C
84 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE  
PIN (1) IDENTIFIER  
0.025 (0.64)  
0.045 (1.14)  
0.050 (1.27) TP  
INCHES  
MILLIMETERS  
R
C
L
SYMBOL  
MIN  
MAX  
MIN  
4.20  
MAX  
4.57  
NOTES  
A
A1  
D
0.165  
0.090  
1.185  
1.150  
0.541  
1.185  
1.150  
0.541  
0.180  
0.120  
1.195  
1.158  
0.569  
1.195  
1.158  
0.569  
-
2.29  
3.04  
-
-
D2/E2  
D2/E2  
30.10  
29.21  
13.75  
30.10  
29.21  
13.75  
30.35  
29.41  
14.45  
30.35  
29.41  
14.45  
C
L
D1  
D2  
E
3
E1 E  
4, 5  
-
VIEW “A”  
E1  
E2  
N
3
4, 5  
6
0.020 (0.51)  
MIN  
84  
84  
A1  
D1  
D
Rev. 2 11/97  
A
SEATING  
PLANE  
0.020 (0.51) MAX  
3 PLCS  
-C-  
0.026 (0.66)  
0.032 (0.81)  
0.013 (0.33)  
0.021 (0.53)  
0.025 (0.64)  
MIN  
0.045 (1.14)  
MIN  
VIEW “A” TYP.  
NOTES:  
1. Controlling dimension: INCH. Converted millimeter dimensions are  
not necessarily exact.  
2. Dimensions and tolerancing per ANSI Y14.5M-1982.  
3. Dimensions D1 and E1 do not include mold protrusions. Allowable  
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1  
and E1 include mold mismatch and are measured at the extreme  
material condition at the body parting line.  
-C-  
4. To be measured at seating plane  
contact point.  
5. Centerline to be determined where center leads exit plastic body.  
6. “N” is the number of terminal positions.  
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.  
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-  
ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.  
No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Intersil Ltd.  
2401 Palm Bay Rd., Mail Stop 53-204  
Palm Bay, FL 32905  
TEL: (321) 724-7000  
FAX: (321) 724-7240  
Mercure Center  
8F-2, 96, Sec. 1, Chien-kuo North,  
Taipei, Taiwan 104  
Republic of China  
TEL: 886-2-2515-8508  
FAX: 886-2-2515-8369  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
25  

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