HSP50210JC-52_技术文档

HSP50210

Data Sheet

January 1999

File Number 3652.4

Digital Costas Loop

Features

The Digital Costas Loop (DCL) performs many of the

baseband processing tasks required for the demodulation of

BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM

waveforms. These tasks include matched ﬁltering, carrier

tracking, symbol synchronization, AGC, and soft decision

slicing. The DCL is designed for use with the HSP50110

Digital Quadrature Tuner to provide a two chip solution for

digital down conversion and demodulation.

• Clock Rates Up to 52MHz

• Selectable Matched Filtering with Root Raised Cosine or

Integrate and Dump Filter

• Second Order Carrier and Symbol Tracking Loop

Filters

• Automatic Gain Control (AGC)

• Discriminator for FM/FSK Detection and Discriminator

Aided Acquisition

The DCL processes the In-phase (I) and quadrature (Q)

components of a baseband signal which have been digitized

to 10 bits. As shown in the block diagram, the main signal

path consists of a complex multiplier, selectable matched

ﬁlters, gain multipliers, cartesian-to-polar converter, and soft

decision slicer. The complex multiplier mixes the I and Q

inputs with the output of a quadrature NCO. Following the

mix function, selectable matched ﬁlters are provided which

perform integrate and dump or root raised cosine ﬁltering

(α ~ 0.40). The matched ﬁlter output is routed to the slicer,

which generates 3-bit soft decisions, and to the cartesian-to-

polar converter, which generates the magnitude and phase

terms required by the AGC and Carrier Tracking Loops.

• Swept Acquisition with Programmable Limits

• Lock Detector

• Data Quality and Signal Level Measurements

• Cartesian to Polar Converter

• 8-Bit Microprocessor Control - Status Interface

• Designed to work with the HSP50110 Digital

Quadrature Tuner

• 84 Lead PLCC

Applications

The PLL system solution is completed by the HSP50210

error detectors and second order Loop Filters that provide

carrier tracking and symbol synchronization signals. In

applications where the DCL is used with the HSP50110,

these control loops are closed through a serial interface

between the two parts. To maintain the demodulator

performance with varying signal power and SNR, an internal

AGC loop is provided to establish an optimal signal level at

the input to the slicer and to the cartesian-to-polar converter.

• Satellite Receivers and Modems

• BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM

Demodulators

• Digital Carrier Tracking

• Related Products: HSP50110 Digital Quadrature Tuner,

D/A Converters HI5721, HI5731, HI5741

• HSP50110/210EVAL Digital Demod Evaluation Board

Block Diagram

CARRIER

TRACK

CONTROL

(COF)

CARRIER ACQ/TRK

LOOP FILTER

CARRIER PHASE

ERROR DETECT

LOCK

DETECT

LKINT

LEVEL

HI/LO

NCO

SIN

LOOP

LEVEL

DETECT

THRESH

FILTER

DETECT

COS

A

10

I SER OR

OUT(9-0)

10

MAGNITUDE

I

8

RRC

FILTER

8

I

(9-0)

IN

INTEGRATE/

DUMP

CARTESIAN

TO

POLAR

PHASE

3

SERCLK

OR CLK

8

10

INTEGRATE/

DUMP

10

Q SER OR

Q

RRC

FILTER

3

SLICER

Q

(9-0)

IN

B

OUT(9-0)

Q

SYMBOL

TRACK

(SOF)

SYMBOL

PHASE

ERROR

DETECT

I

SYMBOL

SMBLCLK

CONTROL

TRACKING

LOOP FILTER

CONTROL/

STATUS

BUS

OEA

OEB

13

CONTROL

INTERFACE

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

3-253

HSP50210

Pinout

84 LEAD PLCC

TOP VIEW

11 10

9

8

7

6

5

4

3

2

1 84 83 82 81 80 79 78 77 76 75

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

74

73

72

71

70

69

68

67

66

IIN5

IIN4

AOUT3

AOUT2

IIN3

AOUT1

AOUT0

SMBLCLK

VCC

IIN2

GND

IIN1

CLK

IIN0

GND

SYNC

QIN9

QIN8

BOUT9

BOUT8

BOUT7

BOUT6

65

64

QIN7

QIN6

63

62

61

60

59

58

57

56

55

54

QIN5

QIN4

BOUT5

GND

VCC

BOUT4

BOUT3

BOUT2

BOUT1

BOUT0

OEB

QIN3

QIN2

QIN1

QIN0

SOFSYNC

SOF

VCC

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Ordering Information

TEMP.

PKG.

NO.

o

PART NUMBER RANGE ( C)

PACKAGE

84 Lead PLCC

HSP50210JC-52

HSP50210JI-52

0 to 70

N84.1.15

-40 to 85

3-254

HSP50210

Pin Description

NAME

TYPE

DESCRIPTION

V

-

I

+5V Power Supply.

Ground.

CC

GND

IIN9-0

In-Phase Parallel Input. Data may be two’s complement or offset binary format (see Table 14). These inputs are

sampled by CLK when the SYNC signal is active Low. IIN9 is the MSB. See Input Controller Section.

QIN9-0

SYNC

COF

I

Quadrature Parallel Input. Data may be two’s complement or offset binary format (see Table 14). These inputs are

sampled by CLK when the SYNC signal is active Low. QIN9 is the MSB. See Input Controller Section.

Data Sync. When SYNC is asserted “Low”, data on IIN9-0 and QIN9-0 is clocked into the processing pipeline by the

rising edge of CLK.

O

Carrier Offset Frequency. The frequency term generated by the Carrier Tracking Loop Filter is output serially via this

pin. The new offset frequency is shifted out MSB ﬁrst by CLK or SLOCLK starting with the clock cycle after the

assertion of COFSYNC.

COFSYNC

SOF

O

Carrier Offset Frequency Sync. This signal is asserted one CLK or SLOCLK cycle before the MSB of the serial data

word. (Programmable Polarity, see Table 41, bit 11).

Sampler Offset Frequency. Sample frequency correction term generated by the Symbol Tracking Loop Filter is output

serially via this pin. The frequency word is shifted out MSB ﬁrst by CLK or SLOCLK starting with the clock cycle after

assertion of SOFSYNC.

SOFSYNC

A2-0

O

I

Sampler Offset Frequency Sync. This signal is asserted one CLK or SLOCLK cycle before the MSB of the serial

data word. (Programmable Polarity, see Table 41, bit 12).

Address Bus. The address on these pins specify a target register for reading or writing (see Microprocessor Interface

Section). A0 is the LSB.

C7-0

I/O

Microprocessor Interface Data Bus. This bi-directional bus is used for reading and writing to the processor interface.

These are the data I/O pins for the processor interface. C0 is the LSB.

WR

RD

I

Write. This is the write strobe for the processor interface (see Microprocessor Interface Section).

Read. This is the read enable for the processor interface (see Microprocessor Interface Section).

FZ_ST

Freeze Symbol Tracking Loop. Asserting this pin “high” zeroes the sampling error into the Symbol Tracking Loop

Filter (see Symbol Tracking Loop Filter Section).

FZ_CT

LKINT

I

Freeze Carrier Tracking Loop. Asserting this pin “high” zeroes the carrier Phase Error input to the Carrier Tracking

Loop Filter.

O

Lock Detect Interrupt. This pin is asserted “high” for at least 4 CLK cycles when the Lock Detector Integration cycle

is ﬁnished (see Lock Detector Section). Used as an interrupt for a processor. The Lock Detect Interrupt may be

asserted “high” longer than 4 CLK cycles, depending on the Lock Detector mode.

THRESH

SLOCLK

O

Threshold Exceeded. This output is asserted “low” when the magnitude out of the Cartesian to Polar converter

exceeds the programmable Power Detect Threshold (see Table 15 and AGC Section).

Slow Clock. Optional serial clock used for outputting data from the Carrier and Symbol Tracking Loop Filters. The

clock is programmable and has a 50% duty cycle. Note: Not used when the HSP50110 is used with the

HSP50210 (see Table 41).

ISER

I

In-Phase Serial Input. Serial data input for In-Phase Data. Data on this pin is shifted in MSB ﬁrst and is synchronous

to SERCLK (see Input Controller Section).

QSER

Quadrature Serial Input. Serial data input for Quadrature Data. Data on this pin is shifted in MSB ﬁrst and is

synchronous to SERCLK (see Input Controller Section).

SSYNC

SERCLK

AOUT9-0

BOUT9-0

SMBLCLK

OEA

I

Serial Word Sync. This input is asserted “high” one CLK before the ﬁrst data bit of the serial word (see Figure 2).

Serial Clock. May be asynchronous to other clocks. Used to clock in serial data (see Input Controller Section).

A Output. Data on this output depend on the configuration of Output Selector. AOUT9 is the MSB (see Table 42).

B Output. Data on this output depend on the configuration of Output Selector. BOUT9 is the MSB (see Table 42).

Symbol Clock. 50% duty cycle clock aligned with soft bit decisions (see Figure 19).

O

I

A Output Enable. This pin is the three-state control pin for the AOUT9-0. When OEA is high, the AOUT9-0 is high

impedance.

OEB

I

B Output Enable. This pin is the three-state control pin for the BOUT9-0. When OEB is high, the AOUT9-0 is high

impedance.

HI/LO

0

HI/LO. The output of the Input Level Detector is provided on this pin (see Input Level Detector Section). This signal

can be externally averaged and used to control the gain of an ampliﬁer to close an AGC loop around the A/D con-

verter. This type of AGC sets the level based on the median value on the input.

CLK

I

System Clock. Asynchronous to the processor interface and serial inputs.

3-255

HSP50210

If serial input mode is selected, the I and Q data enters via

Functional Description

the ISER and QSER pins using SERCLK and SSYNC. The

beginning of a serial word is designated by asserting

SSYNC ‘high’ one SERCLK prior to the ﬁrst data bit, as

shown in Figure 2. On the following SERCLK’s, data is

shifted into the register until all 10 bits have been input. Data

shifting is then disabled and the contents of the register are

held until the next assertion of SSYNC. The assertion of a

SSYNC transfers data into the processing pipeline, and the

Shift Register is enabled to accept new data on the following

SERCLK. When data is transferred to the processing

pipeline by SSYNC, a processing enable is generated which

follows the data through the pipeline. This enable allows the

delay through processing elements (like the loop ﬁlters) to be

minimized since their pipeline delay is expressed in CLKs

not SSYNC periods. Note: SSYNC should not be

The HSP50210 Digital Costas Loop (DCL) contains most of

the baseband processing functions needed to implement a

digital Costas Loop Demodulator. These functions include

LO generation/mixing, matched ﬁltering, AGC, carrier phase

and frequency error detection, timing error detection, carrier

loop ﬁltering, bit sync loop ﬁltering, lock detection,

acquisition/tracking control, and soft decision slicing for

forward error correction algorithms. While the DCL is

designed to work with the HSP50110 Digital Quadrature

Tuner (DQT) as a variable rate PSK demodulator for satellite

demodulation, functions on the chip are common to many

communications receivers.

The DCL provides the processing blocks for the three

tracking loops commonly found in a data demodulator: the

Automatic Gain Control (AGC) loop, the Carrier Tracking

Loop, and a Symbol Tracking Loop. The AGC loop adjusts

for input signal power variations caused by path loss or

signal-to-noise variations. The carrier tracking loop removes

the frequency and phase uncertainties in the carrier due to

oscillator inaccuracies and doppler. The symbol tracking

loop removes the frequency and phase uncertainties in the

data and generates a recovered clock synchronous with the

received data. Each loop consists of an error detector, a loop

ﬁlter, and a frequency or gain adjustment/control. The AGC

loop is internal to the DCL, while the symbol and carrier

tracking loops are closed external to the DCL. When the

DCL is used together with the HSP50110, the tracking loops

are closed around the baseband ﬁltering to center the signal

in the ﬁlter bandwidth. In addition, the AGC function is

divided between the two chips with the HSP50110 providing

the coarse AGC, and the HSP50210 providing the ﬁne or

ﬁnal AGC.

asserted for more than one SERCLK cycle.

SERCLK

SSYNC

ISER/

MSB

SSYNC LEADS 1st DATA BIT

MSB

QSER

NOTE: Data must be loaded MSB ﬁrst.

FIGURE 2. SERIAL INPUT TIMING FOR ISER AND QSER INPUTS

Input Level Detector

The Input Level Detector generates a one-bit error signal for

an external IF AGC ﬁlter and ampliﬁer. The error signal is

generated by comparing the magnitude of the input samples

to a user programmable threshold. The HI/LO pin is then

driven “high” or “low” depending on the relationship of its

magnitude to the threshold. The sense of the HI/LO pin is

programmable so that a magnitude exceeding the threshold

can either be represented as a “high” or “low” logic state.

The Input Level Detector (HI/LO output) threshold and the

sense are set by the Data Path Conﬁguration Control

Register bits 16-23 and 13 (see Table 14). Note: The Input

Level Detector is typically not used in applications

which use the HSP50210 with the HSP50110.

A top level block diagram of the HSP50210 is shown in

Figure 1. This diagram shows the major blocks and the

multiplexers used to reconﬁgure the data path for various

architectures.

Input Controller

In-Phase (I) and Quadrature (Q) data enters the part through

the Input Controller. The 10-bit data enters in either serial or

parallel fashion using either two’s complement or offset

binary format. The input mode and binary format is set in the

Data Path Conﬁguration Control Register, bits 14 and 15

(see Table 14).

The high/low outputs can be integrated by an external loop

ﬁlter to close an AGC loop. Using this method, the gain of

the loop forces the median magnitude of the input samples

to the threshold. When the magnitude of half of the samples

is above the threshold (and half is below), the error signal is

integrated to zero by the loop ﬁlter.

If Parallel Input mode is selected, I and Q data are clocked

into the part through IIN0-9 and QIN0-9 respectively. Data

enters the processing pipeline when the input enable

(SYNC) is sampled “low” by the processing clock (CLK). The

enable signal is pipelined with the data to the various

processing elements to minimize pipeline delay where

possible. As a result, the pipeline delay through the AGC,

Carrier Tracking, and Symbol Tracking Loop Filters is

measured in CLKs; not input data samples.

The magnitude of the complex input is estimated by:

(EQ. 1)

Mag (I, Q) = I + 0.375 × Q if I > Q and

Mag (I, Q) = Q + 0.375 × I if Q > I

3-257

HSP50210

NCO/Mixer

The NCO/Mixer performs a complex multiply between the

baseband input and the output of a quadrature NCO

(Numerically Controlled Oscillator). When the HSP50210

(DQT) is used with the HSP50110 (DCL), the NCO/Mixer

shortens the Carrier Tracking Loop (i.e., minimizes pipeline

delay around the loop) while providing wide loop

Carrier Tracking Loop. Large phase increments take fewer

clocks to step through the sine wave cycle, which results in a

higher frequency NCO output.

The CF Register sets the NCO frequency with the following

equation:

bandwidths. This becomes important when operating at

symbol rates near the maximum range of the part.

32

(EQ. 4)

F

= f

× (CF) ⁄ 2

CLK

C

32

CF = INT[(F ⁄ f

)2 ]H

CLK

C

There are three conﬁgurations possible for closing the

Carrier Tracking Loop when the DQT and the DCL are used

together. The ﬁrst conﬁguration utilizes the NCO on the DQT

and bypasses the NCO in the DCL. The Data Path

Conﬁguration Control Register (see Table 14), bit 10, and

Carrier Loop Filter Control Register #1 (see Table 20), bit 6,

are used to bypass the DCL NCO/Mixer and route the Loop

ﬁlter outputs, respectively. The DQT provides maximum

ﬂexibility in NCO control with respect to frequency and

phase offsets.

where f

CLK

is the CLK frequency, and CF is the 32-bit two’s

complement hexadecimal value loaded into the Carrier

Frequency Register. As an example, if the CF Register is

loaded with a value of 4000 0000 (Hex), and the CLK

frequency is 40MHz, the NCO would produce quadrature

terms with a frequency of 10MHz. When CF is a negative

value, a clockwise cos/sin vector rotation is produced. When

CF is positive, a counterclockwise vector rotation is

produced.

The second conﬁguration feeds the lead Carrier Loop ﬁlter

term to the DCL NCO/Mixer, and the lag Loop ﬁlter Term to

the DQT NCO. This reduces the loop transport delay while

maintaining wide loop bandwidths and reasonable loop

damping factors. This conﬁguration is especially useful in

SATCOM applications with medium to high symbol rates.

The Carrier Loop Filter Control Register #1, bit 5, is where

the lead/lag destination is set.

NOTE: The NCO is set to a ﬁxed frequency by programming the

upper and lower limits of the Carrier Tracking Loop Filter to the

same value and zeroing the lead gain.

Matched Filtering

The HSP50210 provides two selectable matched ﬁlters: a

Root Raised Cosine Filter (RRC) and an Integrate and

Dump (I&D) ﬁlter. These are shown in Figure 3. The RRC

ﬁlter is provided for shaped data pulses and the I&D ﬁlter is

provided for square wave data. The ﬁlters may be cascaded

for better adjacent channel rejection for square wave data. If

these two ﬁlters do not meet baseband ﬁltering

requirements, then they can be bypassed and an external

digital ﬁlter (such as the HSP43168 Dual FIR Filter or the

HSP43124 Serial I/O Filter) used to implement the desired

matched ﬁlter. The desired ﬁlter conﬁguration is set in the

Data Path Conﬁguration Control Register, bits 1-7 (see

Table 14).

The ﬁnal conﬁguration feeds both the lead and lag Carrier

Loop Filter terms back to the DCL NCO/Mixer. This provides

the shortest transport delay. The DCL NCO/Mixer provides

only for frequency/phase control from the Carrier Loop ﬁlter.

The center frequency of this NCO/Mixer is set to the average

of the Upper and Lower Carrier Loop Limits programmable

parameters. These parameters are set in the two control

registers bearing their names (see Tables 22 and 23).

The NCO/Mixer uses a complex multiplier to multiply the

baseband input by the output of a quadrature NCO. This

operation is represented by:

The sample rate of the baseband input depends on the

symbol rate and ﬁltering conﬁguration chosen. In

I

= I cos(ω )–Q sin(ω

IN IN C

)

(EQ. 2)

(EQ. 3)

OUT

C

conﬁgurations which bypass both ﬁlters or use only the RRC

Filter, the input sample rate must be twice the symbol rate. In

conﬁgurations which use the I&D Filter, the input sample rate

is decimated by the I&D Filter, down to two samples per

symbol. I&D conﬁgurations support input sample rates up to

32 times the input symbol rate.

Q

= I sin(ω ) + Q cos(ω )

OUT

IN

C

IN

C

Equation 3 illustrates how the complex multiplier implicitly

performs the summing function when the DCL is conﬁgured

as a modulator. The quadrature outputs of the NCO are

generated by driving a sine/cosine look-up table with the

output of a phase accumulator as shown in Figure 3. Each

time the phase accumulator is clocked, its sum is

The RRC ﬁlter is a ﬁxed coefﬁcient 15 Tap FIR ﬁlter. It has

~40% excess bandwidth beyond Nyquist which equates to

α = ~0.4 shape factor. The ﬁlter frequency response is

shown in Figure 4 and Figure 5. In addition, the 9-bit ﬁlter

coefﬁcients are listed as integer values in Table 1. The noise

equivalent bandwidth of the RRC ﬁlter and other ﬁlter

conﬁgurations possible with the HSP50110/210 chipset are

given in Appendix A.

incremented by the contents of the Carrier Frequency (CF)

32

Register. As the accumulator sum increments from 0 to 2

the SIN/COS ROM produces quadrature outputs whose

,

o

phase advances from 0 to 360 . The CF Register contains a

32-bit phase increment which is updated with the output of

3-259

HSP50210

TABLE 1. ROOT RAISED COSINE COEFFICIENTS

0

COEFFICIENT INDEX

COEFFICIENT

-20

0

1

2

-2

-40

-60

2

1

3

8

4

-16

-14

86

160

86

-14

-16

8

-80

5

-100

6

0

f

2f

CLK

3f

CLK

4f

CLK

f

CLK

10

2

7

FREQUENCY (NORMALIZED TO INPUT SAMPLE RATE)

8

FIGURE 4. RRC FILTER IN HSP50210

9

10

11

12

13

14

0

-0.18

-0.36

-0.54

-0.72

-0.90

1

-2

2

The I&D ﬁlter consists of an accumulator, a programmable

shifter and a two sample summer as shown in Figure 3. The

programmable shifter is provided to compensate for the gain

introduced by the accumulator (see Table 14). The

accumulator provides Integrate and Dump Filtering for

decimation factors up to 16. The two sample summer

provides the moving average required for an additional

decimation factor of 2. A decimation factor of 1 (bypass), 2,

4, 8, 16, or 32 may be selected. At the maximum decimation

rate, a baseband signal sampled at 32 times the symbol rate

can be ﬁltered.

SHOWN BELOW

ENLARGED FOR CLARITY

f

2f

3f

4f

f

CLK

0

25

5

0

-0.07

-0.14

-0.21

-0.28

-0.35

The output of the two sample summer is demultiplexed into

two sample streams at the symbol rate. The demultiplexed

data streams from the I and Q processing paths are fed to

the Symbol Tracking Block and Soft decision slicer. The

multiplexed data streams on I and Q are provided as one of

the selectable inputs for the Cartesian to Polar Converter.

Cartesian/Polar Converter

f

3f

CLK

f

5f

CLK

3f

CLK

The Cartesian/Polar Converter maps samples on the I and Q

processing paths to their equivalent phase/magnitude

representation. The magnitude conversion is equivalent to:

CLK

40

CLK

20

CLK

10

0

40

20

FREQUENCY (NORMALIZED TO INPUT SAMPLE RATE)

2

(EQ. 5)

Mag (I, Q) = (0.81) (I + Q ),

FIGURE 5. PASSBAND RIPPLE OF RRC FILTER IN HSP50210

where 0.81 is the gain of the conversion process. The

magnitude output is an 8-bit unsigned value ranging from 0.0

to 1.9922.

3-260

HSP50210

The phase conversion is equivalent to:

The I/Q data path selected for input to the Cartesian to Polar

converter determines the input data rate of the AGC and

carrier tracking loops. If the I/Q data path out of the Integrate

and Dump Filter is selected, the AGC is fed with magnitude

values produced by the end-symbol samples. Magnitude

values produced by midsymbol samples are not used

because these samples occur on symbol transitions, resulting

in poor signal magnitude estimates. The Carrier Tracking

block is fed with phase values generated from both the end

and mid-symbol samples. The carrier tracking loop filter,

however, is only fed with Phase Error terms generated by the

end symbol samples. If the input of the I&D is selected for

input to the coordinate converter, the control loops are fed

with data at the I/Q data rate. The desired data path input to

the Cartesian to Polar converter is specified in the Data Path

Configuration Control Register, bit 8 (see Table 14).

(EQ. 6)

–1

Phase (I, Q) = tan (Q ⁄ I),

-1

where tan ( ) is the arctangent function. The phase

conversion output is an 8-bit two’s complement output which

ranges from -1.0 to 0.9922 (80 to 7f HEX, respectively). The

-1 to almost 1 range of the phase output represents phase

values from -π to π, respectively. An example of the I/Q to

phase mapping is shown in Figure 6. The phase and

magnitude values may be output via the Output Selector bits

0-3 (see Table 42).

1.0

0.5

0

AGC

The AGC loop operates on the main data path (I and Q) and

performs three signal level adjusting functions: 1)

maximizing dynamic range, 2) compensating for SNR

variations, and 3) maintaining an optimal level into the Soft

Decision Slicer. The AGC Loop Block Diagram, shown in

Figure 7, consists of an Error Detector, a Loop Filter, and

Signal Gain Adjusters (multipliers). The AGC Error Detector

generates an error signal by subtracting the programmable

AGC threshold from the magnitude output of the Cartesian

to Polar Converter. This difference signal is scaled (gain

adjusted via multiplier and shifter), then ﬁltered (integrated)

by the AGC Loop Filter to generate the gain correction to the

I and Q signals at the multipliers. If a ﬁxed gain is desired,

set the upper and lower limits equal.

-0.5

-1.0

-π

-π/2

0

π/2

π

INPUT PHASE

FIGURE 6A. I INPUT TO CARTESIAN/POLAR CONVERTER

1.0

0.5

0

The AGC responds to the magnitude of the sum of all the

signals in the bandpass of the narrowest ﬁlter preceding the

Cartesian to Polar Coordinate Converter. This ﬁlter may be

the Integrate and Dump ﬁlter shown in Figure 8, the RRC

ﬁlter upstream in the HSP50210 data path, or some other

ﬁlter outside the DCL chip. The magnitude signal usually

contains several components: 1) the signal of interest

component, 2) the noise component, and 3) interfering

signals component. At high SNR’s the signal of interest is

signiﬁcantly greater than the other components. At lower

SNR’s, components 2 or 3 may become greater than the

signal of interest. Narrowing the filter bandwidth is the

primary technique used to mitigate magnitude contributions

of component 3. This will also improve the SNR by

reducing the magnitude contributions of element 2.

Consideration of the range of signal amplitudes expected

into the HSP50210, in conjunction with a gain distribution

analysis, will provide the necessary insight to set the signal

level into the Soft Decision Slicer to yield optimum

performance. Note: Failure to consider the variations

due to noise or interfering signals, can result in signal

limiting in the HSP50210 processing algorithms, which

will degrade the system Bit Error Rate performance.

-0.5

-1.0

-π

-π/2

0

π/2

π

INPUT PHASE

FIGURE 6B. Q INPUT TO CARTESIAN/POLAR CONVERTER

1.0

0.5

0

-0.5

-1.0

-π

-π/2

0

π/2

π

INPUT PHASE

FIGURE 6C. CARTESIAN/POLAR CONVERTER PHASE OUTPUT

3-261

HSP50210

The AGC Loop is conﬁgured by the Power Detect Threshold

Register, bits 24-30 (see Table 16). The composite range of

the AGC loop Gain is 0.0000 to [0.9375][2-7]. This will scale

the AGC error signal to a range of 0.000 to

and AGC Loop Parameters Control Registers (see Tables 15

and 16). Seven programmable parameters must be set to

conﬁgure the AGC Loop and its status outputs. Two

(1.1455)(0.9375)(2-7) = 1.07297(2-7).

parameters, the Power Threshold and the AGC Threshold

are associated with the Error Detector and are represented

TABLE 2. AGC LOOP GAIN BINARY MANTISSA TO DECIMAL

SCALED MANTISSA MAPPING

0

-1 -2 -3 -4 -

in 8-bit fractional unsigned binary format: 2 .2 2 2 2 2

5 -6 -7.

BINARY

CODE

DECIMAL

SCALED

BINARY

CODE

DECIMAL

SCALED

2 2 . While the format provides a range from 0 - 1.9961

for the thresholds, the Cartesian to Polar Converter scales

the I and Q input magnitudes by 0.81. Thus, if a full scale

(±1) complex (I and Q) input signal is presented to the

(MMMM)

MANTISSA

(MMMM)

MANTISSA

0000

0001

0010

0011

0100

0101

0110

0111

0.0000

0.0625

0.1250

0.1875

0.2500

0.3125

0.3750

0.4375

1000

1001

1010

1011

1100

1101

1110

1111

0.5000

0.5625

0.6250

0.6875

0.7500

0.8125

0.8750

0.9375

2

converter, the output will be √(0.81) + (0.81) = 1.1455. The

AGC Threshold parameter value is the desired magnitude of

the signal as it enters the Soft Decision Slicer. It is the

parameter that will determine the error signal in the AGC

loop. The Power Threshold, on the other hand, determines

only the power threshold at which the THRESH signal is

asserted. If the signal magnitude exceeds the threshold,

then the THRESH is asserted. This may be used for signal

detection, power detection or external AGC around the A/D

converter. The AGC Threshold parameter is set in the AGC

Loop Parameters Control Register, bits 16-23 (see Table 16).

The Power Threshold parameter is set in the Power Detect

Threshold Control Register, bits 0-7 (see Table 15). Note

that these two threshold parameters are not required to be

set to identical or even related values, since they perform

independent functions

TABLE 3. AGC LOOP BINARY EXPONENT TO SCALED

DECIMAL EXPONENT MAPPING

BINARY CODE

(EEE)

DECIMAL/ HEX

EXPONENT

DECIMAL SCALED

EXPONENT

-7

2

000

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

-8

2

The Enable AGC parameter sets the AGC Error Detector

output to zero if asserted and to normal error detection

output when not asserted. This control bit is set in the AGC

Loop Parameter Control Register, bit 31 (see Table 16). This

bit is used to disable the AGC loop.

-9

2

-10

2

-11

2

-12

2

The remaining AGC parameters determine the AGC loop

characteristics: gain tracking, tracking rate and tracking limits.

The AGC Loop gain is set via two parameters: AGC Loop

Gain Exponent and AGC Loop Gain Mantissa. In general, the

higher the loop gain, the faster signal level acquisition and

tracking, but this must be tempered by the specific signal

characteristics of the application and the remaining

-13

2

-14

2

programmable loop parameters. For the HSP50210, the AGC

Loop Gain provides for a variable attenuation of the input to

the loop filter. The AGC gain mantissa is a 4-bit value which

provides error signal scaling from 0.000 to 0.9375, with a

resolution of 0.0625. Table 2 details the discrete set of

decimal values possible for the AGC Loop Gain mantissa. The

-7

-14

exponent provides a shift factor scaling from 2 to 2

.

Table 3 details the discrete set of decimal values possible for

the AGC Loop Gain Exponent. When combined, the exponent

and mantissa provide a loop gain defined as:

–4

–(7 + E)

(EQ. 7)

AGC Loop Gain: G

= [(M)(2 )][(2

)]

AGC

where M is a binary number with a range from 0 to 15 and E

is a 3-bit binary value from 0 to 7. M and E are the

parameters set in the AGC Loop Parameters Control

3-262

HSP50210

AGC LOOP FILTER

AGC LOOP

AGC ERROR DETECT

R

AGC LOOP

GAIN

AGC

UPPER

LIMIT †

GAIN

LOWER

LIMIT †

EXPONENT †

E

MANTISSA †

THRESH

COMPARE

-7

-14

G

(0.000 TO 0.9375)

)

(2 TO 2

POWER

THRSHLD †

S

L

R

I

R

E

G

R

E

G

M

U

X

H

I

READ

REG

+

-

E

+

M

F

T

G

I

GAIN

ERROR

T

“0”

-7

0.000 TO 1.07297(2

)

AGC THRSHLD †

E

AGC GAIN = (1.0 + M) x 2

ENABLE AGC †

1.64

-----------

2

1.0000 TO 15.8572 = G

dcloutlvl = agc thresh

where dcloutlvl is the

AGC

CART/POLAR INPUT SELECT†

(0 TO 24dB)

CARTESIAN TO POLAR

GAIN

ADJUST

1.64

G = -----------

2

magnitude output expressed

in dB from Full Scale (dBFS)

1.0

G

0.8

AGC

M

U

X

2

I +Q

MAGNITUDE

(0 - 1.1455)

L

I

I&D FILTER

Q

-1

M

I

PHASE

TAN

( )

I

Q

T

† Indicates a microprocessor control signal.

FIGURE 7. AGC LOOP BLOCK DIAGRAM

The AGC Loop Filter integrates the scaled error signal to

provide a correction control term to the multipliers in the I and

Q path. The loop filter accumulator has internal upper and

lower limiters. The upper eight bits of the accumulator output

map to an exponent and mantissa format that is used to set

these upper and lower limits. The format, illustrated in Figure

8, is used for the AGC Upper Limit, AGC Lower Limit and the

Correction Control Term (AGC output). This format should not

be confused with the similar format used for the AGC Loop

Gain. The input to the AGC Loop Filter is included in Figure 8

to show the relative weighting of the input to output of the loop

filter. The loop filter input is represented as the eleven letter

“G”s. Lower case “e” and “m” detail the format for the AGC

Upper and Lower Limits. This change in type case should help

keep the AGC Limits and AGC Gain formats from being

confused. The AGC Upper and Lower Limits are set in the

AGC Loop Parameters Control Register, bits 0-15, (see Table

16). This 6-bit unsigned mantissa format provides for an AGC

output control range from 0.0000 to 0.9844, with a resolution

of 0.015625. The 2-bit exponent format provides an AGC

output control range from 1 to 8. The decimal values for each

of the 64 binary mantissa values is detailed in Table 4, while

Table 5 details the decimal value for the 4 exponent values.

The AGC Output is implemented in the multiplier according

to Equation 8.

e

Out

= (1.0 + m

)(2 )

(EQ. 8A)

(EQ. 8B)

AGC – linear

AGC

e

= 20 log [(1.0 + m

)(2 )]

AGC – dB

AGC

where m and e are the binary values for mantissa and

exponent found in Tables 4 and 5.

NOTE:This format is identical to the format used to program the

AGC Upper and Lower Limits, but in this usage it is not a pro-

grammed value. It is a representation of the digital AGC output

number which is presented to the Gain Adjuster (multipliers) to

correct the gain of the I and Q data signals in the main data path.

These equations yield a composite (mantissa and

exponent) AGC output range of 0.0000 to 1.9844(2 ) which

3

is a logarithmic range from 0 to 24dB. Figure 9 has graphed

the results of Equation 8 for both the linear and logarithmic

equations. Figure 9 also has a linear estimate of the

logarithmic equation. This linear approximation will be used

in calculating the AGC response time.

1

0

-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18

2 2 .2

2

e e .m m m

m

G

FIGURE 8. AGC OUTPUT AND AGC LIMITS BIT WEIGHTING

3-263

HSP50210

TABLE 4. AGC GAIN MANTISSA TO DECIMAL MAPPING

24

16

DECIMAL

VALUE

OF AGC

DECIMAL

VALUE

OF AGC

18

12

6

BINARY CODE

(MMMMMM

BINARY CODE

12

8

GAIN dB

LINEAR ESTIMATE IN dB

)

MANTISSA (MMMMMM

)

MANTISSA

AGC

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

0.000000

0.015625

0.031250

0.046875

0.062500

0.078125

0.093750

0.109375

0.125000

0.140625

0.156250

0.171875

0.187500

0.203125

0.218750

0.234375

0.250000

0.265625

0.281250

0.296875

0.312500

0.328125

0.343750

0.359375

0.375000

0.390625

0.406250

0.421875

0.437500

0.453125

0.468750

0.484375

100000

0.500000

0.515625

0.531250

0.546875

0.562500

0.578125

0.593750

0.609375

0.625000

0.640625

0.656250

0.671875

0.687500

0.703125

0.718750

0.734375

0.750000

0.765625

0.781250

0.796875

0.812500

0.828125

0.843750

0.859375

0.875000

0.890625

0.906250

0.921875

0.937500

0.953125

0.968750

0.984375

GAIN

LINEAR

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

4

1

0

GAIN CONTROL WORD

(8 MSBs OF LOOP FILTER ACCUMULATOR)

FIGURE 9. GAIN CONTROL TRANSFER FUNCTION

There are two techniques for setting a fixed gain for the

AGC. The first is to set Control Word 2 bit 31 = 1. This

precludes any error update of present AGC gain value. The

second is to set the upper and lower AGC limits to the

desired gain using Figure 9. The upper and lower limits

have the same value for this case.

The HSP50210 provides two mechanisms for monitoring

signal strength. The first, which involved the THRESH

signal, has already been described. The second

mechanism is via the Microprocessor Interface. The 8 most

significant bits of the AGC loop filter output can be read by

a microprocessor. Refer to the Microprocessor Interface

Section for details of how to read this value. This AGC

value has the format described in Figure 8.

AGC Bit Weighting and Loop Response

The AGC loop response is a function of the programmable

gain, the bit weightings inherent in the connection of each

element of the loop, the AGC Loop ﬁlter limits and the

magnitude of the input gain error step. Table 6 details the bit

weighting between each element of the AGC Loop from the

error detector through the weighting at the gain adjuster in

the signal path. The AGC Loop Gain sets the growth rate of

the sum in the loop ﬁlter accumulator. The Loop ﬁlter output

growth rate determines how quickly the AGC loop traces the

transfer function shown previously in Figure 9. To calculate

the rate at which the AGC can adjust over a given period of

time, a gain step is introduced to the gain error detector and

the amount of change that is observed between clocks at the

AGC Level Adjusters (multipliers) is the AGC response time

in dB per symbol.This AGC loop will respond immediately

with the greatest correction term, then asymptotically

approach zero correction.

TABLE 5. AGC GAIN EXPONENT TO DECIMAL MAPPING

DECIMAL/ HEX

EXPONENT

DECIMAL SCALED

EXPONENT

BINARY CODE

0

00

01

10

11

0

1

2

3

2

We begin calculation of the loop response with a full scale

error detector input of ±1. This error input is scaled by the

Cartesian to Polar converter, the error detector and the AGC

Loop Gain, accumulated in the loop filter, limited and output to

the gain adjusters. The AGC loop tries to make the error

correction as quickly as possible, but is limited by the AGC

1

2

3

2

3-264

HSP50210

Loop Gain and potentially, the AGC limits. The maximum AGC

only exponent terms of the various gains will be sufficient to

yield a rough order of magnitude of the range of the AGC

Loop response. The results are shaded in the last column of

Table 6 and provided in detail in Equations 9A and 9B.

response is the maximum gain adjustment made in any given

clock cycle. This involves applying maximum Loop gain and

setting the AGC limits as wide as possible. A calculation using

TABLE 6. AGC BIT WEIGHTING

AGC

LOOP

FILTER

GAIN BITS

KEPT

AGC LOOP

FILTER

GAIN

MULIPLIER

(OUTPUT)

AGC

OUTPUT

AND AGC

AGC

ACCUM

BIT

GAIN

ERROR

BIT

GAIN

ERROR

INPUT

AGC LOOP

FILTER GAIN

(MANTISSA)

AGC GAIN

SHIFT

= 0

SHIFT LIMITS BIT RESOLUTION

POSITION

WEIGHT

(rnd)

= 7

WEIGHT

(dB)

22

21

20

19

18

17

16

15

14

13

12

11

10

9

Shifter →

E

1

0

12

6

Multiplier →

M

•

-1

-2

3

1.5

-3

0.75

-4

0.375

-5

0.1875

1

0•

1

-6

0.09375

0.04688

0.02344

0.01172

0.00586

0.00293

0.00146

0.000732

0.000366

0.000183

0.0000916

0.0000458

0.0000229

0.0000114

0.00000572

0.00000286

0-7

-8

G

2

-9

3

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

4

5

8

8(S)

7

= 1(S)

= 0•

= 1

0.

x

12(S)

= 1

1

6

7

11

10

9

11

10

9

= 0•

= 1

= 2

= 3

= 4

= 5

= 6

0•

1

2

3

4

5

6

x

5

= 2

x

4

= 3

x

8

3

= 4

7

2

= 5

6

1

= 6

5

0

= 7

4

3

2

1

0

AGC Response

= Input (Cartesian to Polar Converter Gain)(Error Detector Gain)(AGC Loop Gain)(AGC Output Weighting)

MAX

-7

-9

(EQ. 9A)

AGC Response

MAX

= ±1(0.5)(0.5)(2 )(24) = ±1(2 )(24) = 0.04688dB/symbol time

where (0.5) is the MSB of the 0.81 scaling in the Cartesian to Polar Coordinate Converter, (0.5) is the MSB of the mantissa of the

-7

Loop Gain, (2 ) is the maximum shift gain, and 24 is the maximum loop ﬁlter gain.

A similar procedure is used to calculate the minimum AGC response rate.

-14

-16

AGC Response

MIN

= ±1(0.5)(0.5)(2 )(24) = ±1(2 )(24) = 0.000366dB/symbol time

(EQ. 9B)

Thus, the expected range for the AGC rate is approximately 0.0004 to 0.0469dB/symbol time.

3-265

HSP50210

AGC GAIN

MANTISSA

1.0 - 1.9844

(0.0156 STEPS)

EXPONENT

0

3

2 -2

INTEGRATE AND

DUMP FILTER

3

G = 1.0 - 1.9844*2

INT/DUMP

SHIFTER

SYNTHESIZER/

MIXER

RRC

FILTER

INT/DUMP

ACCUMULATOR

SAMPLE PAIR

SUMMER

0

-4

G = 1.0, 0.5 (NOTE 1)

G = 1.0, 1.13 (NOTE 2)

G = 1-16

G = 2 - 2

G = 0.5, 1.0 (NOTE 3)

L

I

M

I

L

I

M

I

8

/

PART

INPUT

INPUT TO

SOFT DECISION

SLICER

G

AGC

T

5

-2

4

AND

4

2

-2

2

-2

2

SYMBOL TRACKING

BLOCK

3

2

1

0

3

2

1

0

2

1

0

2

1

-2

2

(NOTE 4)

0

-2

2

-2

2

-2

2

-2

BINARY

POINT

-1

-9

-1

-9

-1

2

-10

-7

-11

-6

2

-7

RND

2

RND

INPUT TO CARTESIAN TO POLAR CONVERTER

IF AGC OUTPUT SELECTED

INPUT TO CARTESIAN TO POLAR CONVERTER

IF INT/DUMP OUTPUT SELECTED

NOTES:

1. If the Mixer is enabled the result of the complex multiply is scaled by two (G = 0.5). If the mixer is bypassed, the data passes unmodified (G = 1.0).

2. If the Root Raised Cosine Filter is enabled, a gain of G = 1.13 is introduced. If the RRC filters bypassed, the gain is unity.

-7

3. If the integrate and Dump Filter is bypassed the Sample Pair summer has a gain of G = 1.0 and the 2 -bit position is set to 1. If the integrate

and dump is enabled, the sample pair sum is scaled by one half (G = 0.5).

4. The negative sign on the MSBs indicates use of 2’s complement data format.

FIGURE 10. GAIN DISTRIBUTION AND INTERMEDIATE BIT WEIGHTINGS

Following the AGC, the signal path is limited to 8 bits and

Gain Distribution

passed through the Integrate and Dump Filter en route to the

The gain distribution in the DCL is shown in Figure 10.

Soft Decision Slicer and Symbol Tracking Block.The I&D Filter

These gains consist of a combination of ﬁxed,

uses an accumulator together with a sample pair summer to

programmable, and adaptive gains. The ﬁxed gains are

achieve the desired decimation rate. The I&D shifter is

introduced by processing elements such as the Mixer and

provided to compensate for the gain introduced by the I&D

Square Root of Root Raised Cosine Filter. The adaptive

Accumulator. The accumulator introduces gain equal to the

gains are set to compensate for variations in input signal

decimation factor R, and the shifter gain can be set to 1/R. For

strength.

example, if the I&D Filter decimation of 16 is chosen the I&D

Accumulator will accumulate 8 samples before dumping,

which produces a gain of 8. Thus, for unity gain, the I&D

Shifter would be set for a gain of 2 . The Sample Pair

The main signal path, with processing block gains and path

bit weightings, is shown in Figure 10. The quadrature inputs

to the HSP50210 are 10-bit fractional two’s complement

numbers with relative bit weightings, as shown in the

Figure 10. The ﬁrst element in the processing chain is the

Mixer, which scales the quadrature outputs of the complex

multiplier by 1/2 providing a gain of G = 0.5. If the Mixer is

bypassed, the signal is passed unmodiﬁed with a gain of 1.0.

Following the mixer, the quadrature signal is passed to the

ﬁxed coefﬁcient RRC ﬁltering block, which has a gain of 1.13

if enabled and 1.0 if bypassed. Next, the AGC supplies gain

to maintain an optimal signal level at the input to the Soft

Decision Slicer, Cartesian to Polar Converter, and the

Symbol Tracking Loop. The gain supplied by the AGC

-3

Summer is unity gain since its output is scaled by one-half.

Symbol Tracking

The symbol tracking loop adjusts the baseband sampling

frequency to force sampling of the baseband waveform at

optimal points for data decisions. The key elements of this

loop are the Sampling Error Detector and Symbol Tracking

Loop Filter shown in Figure 11. The output of these two blocks

is a frequency correction term which is used to adjust the

baseband sample frequency external to the HSP50210. In

typical applications, the frequency correction term is fed back

to the HSP50110 to adjust baseband sampling via the

Resampling NCO (see HSP50110 Datasheet).

3

ranges from 1.0 to 1.9844*2 .

3-266

HSP50210

Output Section). In basic configurations, the SOF output of

the HSP50210 is connected to the SOF input of the

HSP50110.

Sampling Error Detector

The Sampling Error Detector is a decision based error

detector which determines sampling errors on both the I and

Q processing paths. The detector assumes that it is fed with

samples of the baseband waveform taken in the middle of

the symbol period (mid-symbol sample) and between

symbols (end-symbol sample) as shown in Figure 12. The

sampling error is a measure of how far the mid-symbol

sample is from the symbol transition mid-point. The

transition mid-point is half way between two symbol

decisions. The detector makes symbol decisions by

comparing the end-symbol samples against a selectable

threshold set (see Modulation Order Select bits 9-10 in Table

28). The error term is generated by subtracting the mid-

symbol sample from the transition mid-point. The sign of the

error term is negated for negatively sloped symbol

transitions. If no symbol transitions are detected the error

detector output is zeroed. Errors on both the I and Q

processing paths are summed and divided by two if Double

Rail error detection is selected (see Symbol Tracking

Conﬁguration Control Register, bit 8: Table 28).

Two sets of registers are provided to store the loop gain

parameters associated with acquisition and tracking. The

appropriate loop gain parameters are selected manually via

the Microprocessor Interface or automatically via the Carrier

Lock Detector. The loop ﬁlter’s lead and lag gain terms are

represented as a mantissa and exponent. The mantissa is a

4-bit value which weights the loop ﬁlter input from 1.0 to

1.9375. The exponent deﬁnes a shift factor that provides

-1

-32

additional weighting from 2 to 2 . Together the loop gain

-32

mantissa and exponent provide a gain range between 2

and ~1.0 as given by,

-4 -(32 -E)

Lead/Lag Gain = (1.0+M*2 )*2

(EQ. 10)

where M = a 4-bit binary number from 0 to 15, and E is a 5-bit

binary value ranging from 0 to 31. For example, if M = 0101

-26

and E = 00110, the Gain = 1.3125*2 . They are stored in the

Control Registers described in Table 31 and Table 32.

A limiter is provided on the lag accumulator output to keep the

baseband sample rate within a user defined range (see Table

29 and Table 30). If the lag accumulator exceeds either the

upper or lower limit, the accumulator is loaded with the limit.

For additional loop filter control, the loop filter output can be

frozen by asserting the FZ_ST pin which null the sampling

error term into the loop filter. The lag accumulator can be

initialized to a particular value and can be read via the

microprocessor interface as described in the Section

The sampling Error Detector provides an error accumulator

to compensate for the processing rate of the loop ﬁlter. The

error detector generates outputs at the symbol rate, but the

loop ﬁlter can only accept inputs every eight f

clocks.

CLK

Thus, if the symbol rate is faster than 1/8 CLK, the error

accumulator should be used to accumulate the error until the

loop ﬁlter is ready for a new input. If the error accumulator is

not used when the symbol rate exceeds 1/8 CLK, some error

outputs will be missed. For example, if f

= 40MHz, then

“Reading from the Microprocessor Interface”, and Table 33.

The symbol tracking loop filter bit weighting is identical to the

carrier tracking loop bit weighting, shown in Figures 9 and 10.

CLK

error accumulation is required for symbol rates greater than

5 MSPS (f /8). Note: The loop ﬁlter lead gain term

CLK

must be scaled accordingly if the accumulator is used.

Soft Decision Slicer

The Soft Decision Slicer encodes the I/Q end-symbol

samples into 3-bit soft decisions. The input to the slicer is

assumed to be a bi-polar (2ary) baseband signal

END-SYMBOL

SAMPLE

MID-SYMBOL

SAMPLE

X

EXPECTED

representing encoded values of either ‘1’ or ‘0’. The most

signiﬁcant bit of the 3-bit soft decision represents a hard

decision with respect to the mid-point between the expected

symbol values. The 2 LSBs represent a level of conﬁdence

in the decision. They are determined by comparing the

magnitude of the slicer input to multiples (1x, 2x, and 3x) of a

programmable soft decision threshold (see Figure 13).

SAMPLING

ERROR

SYMBOL

LEVELS

X

TRANSITION

MIDPOINT

FIGURE 12. TRACKING ERROR ASSOCIATED WITH BASE-

BAND SAMPLING ON EITHER I OR Q RAIL

(BPSK/QPSK)

Symbol Tracking Loop Filter

The Symbol Tracking Loop Filter is a second order lead/lag

filter. The sampling error is weighted by the lag gain and

accumulated to give the integral response (see Figure 11).

The Lag Accumulator output is summed with the sampling

error weighted by the Lead Gain. The result is a frequency

term which is output serially, via the SOF output, to the

NCO/VCO controlling the baseband sample rate (see Serial

3-268

HSP50210

TABLE 7. SLICER INPUT TO OUTPUT MAPPING

HARD DECISION

THRESHOLD

SLICER INPUT MAGNITUDE

RELATIVE TO

‘1’ DECISION

‘0’ DECISION

‘0’

‘1’

STRONGER

WEAKER

STRONGER

PROBABILITY

DENSITY

FUNCTION

+

-

>

≤

>

≤

<

≤

>

≤

<

≤

>

011

010

001

000

100

101

110

111

011

010

001

000

111

110

101

100

0.5

-0.5

0.0

FS

MSB-1

1/2

1/3

-

MSB

THRESHOLD

-

0

-

MSB-1

THRESHOLD

1/3

1/2

MSB

Carrier Phase Error Detector

-FS

The Carrier Phase Error is computed by removing the

phase modulation from the phase output of the Cartesian

to Polar Converter. To remove the modulation, the phase

term is rotated and multiplied (modulo 2π) to fold the Phase

FIGURE 13. OVERLAY OF THE HARD/SOFT DECISION

THRESHOLDS ON THE SYMBOL PROBABILITY

DENSITY FUNCTIONS (PDFs) FOR BPSK/QPSK

SIGNALS)

o

Error into an arc centered about 0 but encompasses the

whole plane, as shown in Figure 14. The phase rotation is

performed by adding a 4-bit two’s complement phase offset

(resolution 22.5 ) to the 4 MSBs of the 8-bit phase term.

The soft decision threshold represents a range of

magnitude values from 0.0 to ~0.5. Note: Since the input

to the slicer has a range of 0.0 to ~1.0, the threshold

setting should be set to less than 1.0/3 = 0.33. This

avoids saturation. The slicer decisions are output in either

a two’s complement or sign/magnitude format (see Soft

Decision Slicer Configuration Control Register, bit 7: Table

40). The slicer input to output mapping for a range of input

magnitudes is given in Table 7. For example, a negative

input to the slicer whose magnitude is greater than twice

the programmable threshold but less than 3x the threshold

would produce a sign/magnitude output of 110 (BINARY).

The I and Q inputs to the slicer are encoded into 3-bit soft

decisions ISOFT(2-0) and QSOFT(3-0). These signals are

routed to the OUTA(9-4) outputs by the Output

o

The multiplication is performed by left shifting the result

from 0-3 positions with the MSB’s discarded and zeros

inserted into the LSB’s. For example, Carrier Phase Error

produces I/Q constellation points which are rotated from

the expected constellation points as shown in Figure 14. By

o

adding an offset of 45 (0010 0000 binary) and multiplying

by 4 (left shift by two positions) the phase modulation is

o

removed, and the error is folded into a 90 arc centered at

o

0 . The left axis represents a decision boundary of ±45 C,

o

implying the vertical axis is ±22.5 as shown in Figure 14.

The phase offset and shift factors required for different PSK

orders is given in Table 8. Configuration of the Carrier

Phase Error Detector is done via the Carrier Phase Error

Detector Control Register, bits 0-5, (see Table 17). The

Phase Error term may be selected for output via the Output

Selector Configuration Control Register, bits 0-3 (see

Table 42).

Configuration Control Register Selector bits 0-3 (see

Table 42).

3-269

HSP50210

In applications where Phase Error terms are generated

operation by the Control Registers described in Tables 20

to 27.

faster than the processing rate of the Carrier Loop Filter, an

error accumulator is provided to accumulate errors until the

loop ﬁlter is ready for a new input. Phase Error terms are

generated at the rate I/Q samples are input to the Cartesian

to Polar Converter. However, the Carrier Loop Filter can not

The Carrier Tracking Loop is closed by using the loop ﬁlter

output to control the NCO or VCO used to down convert the

channel of interest. In basic conﬁgurations, the frequency

correction term controls the Synthesizer NCO in the

HSP50110 Digital Quadrature Tuner via the COF and

COFSYNC pins of the HSP50210’s serial interface (see

Serial Output Section). In applications where the carrier

tracking is performed using the NCO on board the

HSP50210, the loop ﬁlter output is fed to the on-board NCO

as a frequency control.

accept new input faster than CLK/6 since six CLK(f

)

CLK

clock edges are required to complete its processing cycle. If

the error accumulator is not used and the I/Q sample rate

exceeds CLK/6, error terms will be missed.

NOTE: The carrier Phase Error terms input to the loop ﬁlter are

only generated from the end-symbol samples when the output

of the I&D ﬁlter is selected for input to the Cartesian-to-Polar

converter.

The gain for the lead and lag paths of the Carrier Loop Filter

are set through a programmable mantissa and exponent.

The mantissa is a 4-bit value which weights the loop ﬁlter

input from 1.0 to 1.9375. The exponent deﬁnes a shift factor

NOTE: The loop ﬁlter lead gain term must be scaled accordingly

if the accumulator is used.

o

-1

-32

90

Q

that provides additional weighting from 2 to 2 . Together

EXPECTED

CONSTELLATION

POINT

θ

E

o

the loop gain mantissa and exponent provide a gain range

-32

X

between 2

and ~1.0 as given by,

-4 -(32 -E)

ACTUAL

CONSTELLATION

POINT

I

o

±180

0

Lead/Lag Gain = (1.0+M*2 )*2

(EQ. 11)

DECISION

REGION

BOUNDARY

where M = a 4-bit binary number from 0 to 15, and E is

a 5-bit binary value ranging from 0 to 31. For example, if

o

-90

INPUT TO CARTESIAN/POLAR CONVERTER

-26

M = 0101 and E = 00110, the Gain = 1.3125*2 . The loop

o

22.5

Q

90

gain mantissa and exponent are set in the Carrier Loop Gain

Control Registers (see Tables 24 - 25).

Q

DECISION

REGION

o

DECISION

REGION

45

X

θ

E

I

BOUNDARY

I

o

The Phase Error input to the Carrier Loop Filter is an 8-bit

fractional two’s complement number between ~1.0 to -1.0

±180

0

±45

0

X

θ

E

0

-1 -2 -3 -4 -5 -6 -7

X

o

(Format -2 . 2 2 2 2 2 2 2 ). Some LSB’s are zero

for BPSK, QPSK and 8-PSK. If minimum loop gain is used,

o

-90

-22.5

-32

the Phase Error is shifted in signiﬁcance by 2 . With

o

MULTIPLICATION BY 4

PHASE ROTATION BY 45

(MODULO 2π)

maximum loop gain, the Phase Error is passed almost

unattenuated. The output of the Carrier Loop ﬁlter is a 40-bit

fractional two’s complement number between ~1.0 and -1.0

o

PROJECTION OF PHASE ERROR (θ ) ABOUT 0

E

FIGURE 14. PHASE ERROR DETECTOR OPERATION (QPSK)

0

-1 -2 -3

-39 -40

(Format -2 . 2 2 2 ..... 2

2

). In typical applications,

the 32 MSBs of the loop filter output represent the

frequency control word needed to adjust the down

converting NCO for phase lock. Tables 9 and 10 illustrate

the bit weighting of the Carrier Loop Filter into the NCO for

both tracking and acquisition sweep modes.

TABLE 8. BASIC PHASE ERROR DETECTOR SETTINGS

PHASE ER-

MODULATION

TYPE

PHASE

OFFSET

SHIFT

FACTOR

ROR

RANGE

CW

0^o(00 HEX)

0 (no shift)

1 (left shift 1)

2 (left shift 2)

±180

±90

±45

±22

A limiter is provided on the Carrier lag accumulator output to

keep frequency tracking within a user deﬁned range (see

Tables 22 - 23). If the lag accumulator exceeds either the

upper or lower limit the accumulator is loaded with the limit.

For additional loop ﬁlter control, the Carrier Loop Filter

output can be frozen by asserting the FZ_CT pin which nulls

the Phase Error term into the loop ﬁlter. Also, the lag

accumulator can be initialized to a particular value via the

Microprocessor Interface as described in Table 27 and can

be read via the microprocessor interface as described in

“Reading from the Microprocessor Interface Section”.

BPSK

QPSK

8-PSK

45^o(20 HEX)

o

22.5 (10 HEX) 3 (left shift 3)

Carrier Loop Filter

The Carrier Loop Filter is second order lead/lag ﬁlter as

shown in Figure 14. The loop ﬁlter is similar to the Symbol

Tracking Loop Filter except for the additional terms from the

AFC Loop Filter and the Frequency Sweep Block. The

output of the Lag Accumulator is summed with the weighted

Phase Error term on the lead path to produce a frequency

control term. The Carrier Loop Filter is conﬁgured for

3-270

HSP50210

TABLE 9. BIT WEIGHTING IN THE CARRIER LOOP FILTER TO THE NCO - TRACKING

BITS

φe

OUTPUT

BIT

WEIGHT

(AND

ACCOM.)

MANTISSA

GAIN

MULT

OUT

KEPT

(RND)

SHIFT

NCO BIT

WEIGHT

FREQUENCY

RESOLUTION

SHIFT = 0 SHIFT 32 COUNTS

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

0

f

CLK

Obtained with a shift of 31 and a Gain of 01.1111 (~2) →

(8)

7.

6

- shift31

- shift30

- shift29

- shift28

- shift27

- shift26

- shift25

- shift24

- shift23

- shift22

- shift21

- shift20

- shift19

- shift18

- shift17

- shift16

- shift15

- shift14

- shift13

- shift12

- shift11

- shift10

- shift9

1

f

/2

/4

/8

CLK

2

3

5

4

f

/16

/32

/64

CLK

4

5

CLK

3

6

2

7

f

/128

/256

/512

CLK

1

8

CLK

0

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

f

/1024

/2048

/4096

CLK

/8192

14

f

/2

CLK

15

16

17

18

19

10

21

22

23

24

25

26

27

28

29

30

31

32

34

35

36

37

38

39

40

- shift8

- shift7

17

- shift6

(12)

(11)

(10)

(9)

(8)

7.

16

15

14

13

12

11.

10

9

17

16

15

14

13

12.

11

10

9

= (12)

= (11)

= (10)

= (9)

= (8)

= 7.

= 6

(12)

(11)

(10)

(9)

(8)

7.

- shift5

- shift4

- shift3

- shift2

8

0

1.

x

- shift1

7

- shift0

6

5

x

= 5

5

4

x

8

= 4

4

3

x

7

8

= 3

3

2

6

7

= 2

2

1

5

6

= 1

1

0

4

5

= 0

0

3

(RND)

2

1

0

3-272

HSP50210

TABLE 10. BIT WEIGHTING IN THE CARRIER LOOP FILTER TO THE NCO - SWEEP

OUTPUT

BIT

WEIGHT

SWEEP

MANTISSA GAIN

FREQUENCY

RESOLUTION

φe

SHIFT = 0 SHIFT = 32

SHIFT COUNTS

NCO BIT WEIGHT

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

0

f

CLK

Shift 27 and Gain = 01.1111 →

(8)

7.

6

- shift28

- shift27

- shift26

- shift25

- shift24

- shift23

- shift22

- shift21

- shift20

- shift19

- shift18

- shift17

- shift16

- shift15

- shift14

- shift13

- shift12

- shift11

- shift10

- shift9

1

f

/2

/4

/8

CLK

2

3

5

4

f

/16

/32

/64

CLK

4

5

CLK

3

6

2

7

f

/128

/256

/512

CLK

1

8

CLK

0

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

f

/1024

/2048

/4096

CLK

/8192

14

f

/2

CLK

15

16

17

18

19

10

21

22

23

24

25

26

27

28

29

30

31

32

34

35

36

37

38

39

40

- shift8

- shift7

- shift6

- shift5

- shift4

- shift3

- shift2

(12)

(11)

(10)

(9)

(8)

7.

0

1.

x

z

5

4.

3

- shift1

- shift0

2

8

1

7

0

6

5

4

3

2

1

0

NOTE:

-29

5. SW

= 2

at 1% FLB, 4M , 0.075Hz/Baud = 12Kbps.

clk

min

3-273

HSP50210

by setting the offset and shift terms to zero (see Frequency

Frequency Sweep Block

Error Detector Control Register; Table 19). The frequency error

term may be selected for output via the Output Select Block.

(See Serial Output Configuration Control Register, Table 42).

The Frequency Sweep Block is used during carrier acquisition

to sweep the range of carrier uncertainty. The Sweep Block is

loaded with a programmable value which is input to the lag path

of the Carrier Tracking Loop Filter when frequency sweep is

enabled. The sweep value is accumulated by the loop filter’s lag

accumulator which causes a frequency sweep between the

accumulator’s upper and lower limits. When one of the limits is

reached, the sweep value is inverted to sweep the frequency

back toward the other limit. The Frequency Sweep Block is

controlled by the Lock Detector and is only enabled during

carrier acquisition (see Lock Detector Control Section).

Automatic Frequency Control (AFC)

Loop Filter

The AFC Loop Filter supplies a frequency correction term to

the lag path of the Carrier Loop filter. The frequency

correction term is generated by weighting the output of the

Frequency Error Detector by a user programmable weight

(see Sweep/AFC Control Register; Table 26). Note: If AFC is

not desired, the frequency error term to the loop filter is

nulled via the Carrier Tracking Configuration Control

Register #2 (see Table 21).

A stepped acquisition mode is provided for microprocessor

controlled acquisition. In the stepped acquisition mode, the lag

accumulator is incremented or decremented by the

programmed sweep value each time the lock detector is

restarted during acquisition. This technique prevents the loop

from sweeping past the lock point before the microprocessor

can respond. Typically in stepped acquisition mode, the step

value is set to a percentage of the loop bandwidth. A dwell

counter is also provided for stepped acquisition. This counter

holds off the lock detector integration from 1 to 129 symbols to

allow the loop to settle before starting the integration.

Serial Output Interfaces

Frequency control data for Carrier and Symbol Tracking is

output from the DCL through two separate serial interfaces.

The Carrier Offset frequency control is output via the COF

and COFSYNC pins. The Symbol Tracking Offset frequency

control is output via the SOF and SOFSYNC pins. A

SLOCLK is provided to allow for reduced serial rate data

exchanges. The timing relationship of these signals is shown

in Figure 16.

The sweep value is set via a programmable mantissa and

-(28 - EEEEE)

exponent. The format is 01.MMMM * 2

where

MMMM is the 4-bit mantissa and EEEEE is the 5-bit exponent

and the weighting is relative to the MSB of the NCO control

word. In swept acquisition mode, the sweep value is the amount

that the carrier lag accumulator is incremented or decremented

each time a new filter output is calculated (sweep rate/N). In

stepped acquisition mode, it is the amount the lag accumulator

is incremented or decremented each time that the lock detector

is restarted. (See Frequency Sweep/AFC Control Loop Control

Register, Table 26.)

CLK

COFSYNC/

SOFSYNC

COF/

SOF

MSB

LSB MSB

NOTE: Data must be loaded MSB ﬁrst.

FIGURE 16. SERIAL OUTPUT TIMING FOR COF AND SOF

OUTPUTS

Carrier Frequency Detector

Each serial word has a programmable word width of either 8,

12, 16, 20, 24, 28, 32, or 40 bits (see Table 41, CW27, bits

4-6 for COF and bits 0-2 for SOF). The polarity of the sync

signals is programmable and is set in CW27 bit 12 for SOF

and bit 11 for COF. The polarity of the serial clock to the

serial data is programmed via CW27 bit 10. If reduced rate

frequency updates is required, the SLOCLK rate is selected

via CW27 bit 7 and the rate is set via CW27 bits 8-9, to be

either CLK/2, CLK/4, CLK/8 or CLK/16. Note that if the DCL

is used with the HSP50110 DQT, then the SLOCLK cannot

be used, i.e. the serial clock must be set to be CLK.

The Frequency Detector generates a frequency term for use

in Automatic Frequency Control (AFC) configurations. The

Frequency Detector (discriminator) subtracts a previous

Phase Error sample from the current one (d/dt) to produce a

term proportional to the carrier frequency. The discriminator

gain is adjusted by programming a variable delay (1-16)

between the samples subtracted (see Frequency Detector

Control Register; Table 18).

NOTE: The input to the discriminator corresponds to phase terms

taken from baseband samples at either the SYNC rate or twice

symbol rate depending on the input source chosen for the Carte-

sian to Polar converter.

Lock Detector

Carrier Frequency Error Detector

The Lock Detector consists of the Dwell Counter, Integration

Counter, Phase Error Accumulator, False Lock/Frequency

Accumulator, Gain Error Accumulator and the Lock Detect

State Machine (see Figure 16). The function of the Lock

Detector is to monitor the baseband symbols and to decide

whether the Carrier Tracking Loop is locked to the input

The Frequency Error Detector is used to generate a frequency

error term for FSK modulated wave forms. The error is

computed by adding an offset and shifting the frequency

detector output in a manner similar to that used by the Phase

Error Detector. For PSK demodulation, this block is bypassed

3-274

HSP50210

signal. Note: The Symbol Tracking Loop locks

The False Lock Detector is used to indicate false lock on

square wave data in a high SNR environment. A false lock

condition is detected by monitoring the ﬁnal integration stage

in the Q branch of the Integrate and Dump Filter (see Figure

3). If the magnitude of the integration over the symbol period

is less than the integration over half a symbol period, a

possible false lock condition is detected; (integration over a

symbol period has gone from end-bit to end-bit, while

integration over half the symbol period has gone from the

previous end-bit to mid-bit). By accumulating the number of

these occurrences over the Integration Period, the Lock

Detector State Machine determines whether a false lock

condition exists. The False Lock Accumulator is used to

accumulate the number of possible false lock occurrences

over the Integration Period. The False Lock Accumulator can

also be conﬁgured to accumulate the output of the

independently; under most circumstances, it will lock

before the Carrier Tracking Loop locks up. Based on the

in-lock/out-of-lock decision, either the Acquisition or Tracking

parameters are selected in the Carrier Tracking Loop, the

Symbol Tracking Loop and in the Lock Detector itself. The

Lock Detector can be conﬁgured either to make the “lock”

decision automatically using the State Machine Control

Mode, or to collect the necessary data so that an external

microprocessor can control the acquisition/tracking process

via the Microprocessor Control Mode (see Figure 22).

In State Machine Control Mode, the Lock Detector State

Machine monitors the outputs of the Phase Error Accumulator

and the False Lock Accumulator to determine the Lock

Detector state. Accumulation effectively averages the Phase

Error and false lock count, reducing their variance. Lock is

detected by accumulating the magnitude of the Phase Error

over a predetermined interval up to 1025 symbols (the

Integration Time). When the Carrier Loop is locked, the

Integration Period will end before an overflow occurs in the

Phase Error Accumulator. At the beginning of a lock detection

cycle, the Phase Error Accumulator and the Integration Counter

are loaded with their respective pre-load values. With each end

bit sample, the Phase Error Accumulator adds the magnitude of

the current Phase Error to its accumulated sum, while the

Integration Counter decrements one count. The Lock Detector

State Machine monitors the overflow bit of the Phase Error

Accumulator and the output of the Integration Counter. If the

Phase Error Accumulator overflows before the Integration

Counter reaches zero, then the accumulated Phase Error is too

large for the Carrier Tracking Loop to be in lock and the Lock

Detector State Machine goes into the Search state (see Lock

Detector State Machine below). In the search state, the loop

parameters are reloaded with “Acquisition” rather than

“Tracking” values. When the Phase Accumulator overflows or

when the Integration Counter reaches zero, the Integration

Counter and the accumulators are re-initialized and the process

begins again. The Integration Counter Pre-load corresponds to

the number of symbols over which to integrate. The Phase

Error Preload corresponds to the distance the Phase Error

Accumulator starts away from overflow. This distance divided

by the Integration Period equals the average Phase Error. The

pre-load value is calculated using:

Frequency Error Detector (see Lock Detection Conﬁguration

Control Register bit 27: Table 34).

The Gain Error Accumulator provides a mechanism to

estimate data quality (E /N ). The accumulator integrates

s

o

the magnitude of the gain error of the end-bit samples, over

the Integration Period. Note: The Gain Error end-bit data

is valid only after lock has been declared, and the

demod is the tracking mode. The accumulated value

gives an indication of the variance about the ideal

constellation points. The accumulator output is read via the

Microprocessor Interface. The Gain Error Accumulator is

always pre-loaded with zero.

For applications where stepped acquisition is used, a Dwell

Counter is provided. In this mode, the lag accumulator in the

Carrier Loop Filter is stepped to a new frequency after each

Lock Detector integration. The Dwell Counter is used to hold

off Lock Accumulator integration until the loop has a chance

to settle.

Lock Detector Control

The selection of acquisition and tracking modes is controlled

by either the internal state machine or an external

microprocessor. The internal state machine monitors the

rollover of the Phase Error Accumulator and the False Lock

Accumulator relative to the Integration Counter. Depending

on whether the accumulators or counter roll over ﬁrst, the

acquisition or tracking parameters are selected for the Loop

Filters and the Lock Detector Accumulators. In addition, the

state machine controls the frequency sweep input to the

Carrier Tracking Loop.

Preload =

Full Scale

(EQ. 12)

Lock Threshold

----------------------------------------------

Full Scale Phase

The ﬂow of the acquisition control is shown in the State

Diagram in Figure 17. The state machine controls the

acquisition process as described below:

–

x 128 x Integration Count

where

18

Search. The frequency uncertainty is swept by enabling the

Frequency Sweep Block to the lag path of the Carrier

Tracking Loop Filter. The acquisition parameters are enabled

to the Loop Filters and the Lock Detector Accumulators.

Phase lock is obtained when the Lock Counter rolls over

before the Phase Error Accumulator (average Phase Error is

less than the lock threshold).

Full scale = 2 -1

o

Full scale phase = 180 for CW, 90 for BPSK, 45 for QPSK,

etc;

o

Lock Threshold <45 for BPSK, <22.5 for QPSK, etc.

(typical after shift); and Integration Count = Integration

Period measured in symbol times.

3-275

HSP50210

Verify. Once phase lock is obtained, the frequency sweep is

disabled and the tracking parameters are enabled. Lock is

veriﬁed if the accumulated Phase Error is below the

threshold for a programmable number of Integration Periods.

False lock conditions are also monitored by comparing the

roll over of the False Lock Accumulator to that of the

Integration Counter. If the False Lock Accumulator rolls over

before the Integration Counter, a false lock condition exists.

are monitored by an external processor to determine when

lock has been achieved. In this mode the accumulator pre-

loads are typically set to zero and the accumulator output is

compared in the processor against a threshold equal to the

maximum Phase Error per sample times the number of

samples per Integration Period. The accumulators stop after

each Integration Period to hold their outputs for reading via

the Microprocessor Interface (see Read Enable Address Map;

Table 11). The accumulators are restarted by writing the

Initialize Lock Detector Control address (see Initialize Lock

Detector Control Register: Table 44). To simplify the processor

interface, the LKINT output is provided to interrupt the

processor when the accumulator integration period is

complete. The processor controls the use of the

False Lock. Once a false lock has been determined, the

Frequency Sweep block is enabled to move the carrier

tracking beyond the false lock region. The Frequency Sweep

is performed for a programmable number of Integration

Periods before returning to the search state.

Lock. When phase lock has been veriﬁed, the Lock status

output is asserted and the False Lock Detector is disabled.

The lock state is maintained as long as the Integration

Counter rolls over before the Phase Error Accumulator.

acquisition/tracking parameters and lock status line by setting

the appropriate bits in the Acquisition/Tracking Configuration

Control Register (see Table 37). In addition, the frequency

sweep function is enabled via the Microprocessor Interface.

If the acquisition and tracking process is controlled externally,

the Phase Error Accumulator and False Lock Accumulators

PHASE

ERROR

PHASE

ERROR

FALSE

LOCK

PRELOAD PRELOAD

ACQ TRACK

FALSE

LOCK

DWELL

COUNT

ACQ

INT

“0”

TRACK

PERIOD PERIOD PRELOAD PRELOAD

ACQ TRACK ACQ TRACK

GAIN

ERROR

FALSE LOCK/

FREQUENCY

ERROR

PHASE

ERROR

MUX

“0”

|X|

DWELL

INTEGRATION

COUNTER

+

COUNTER

TC

START

TC

REG

SWEPT

OVERFLOW

LOCK DETECTOR STATE MACHINE

ACQUIRE/

TRACK

FIGURE 17. LOCK DETECTOR BLOCK DIAGRAM

3-276

HSP50210

PHASE ERROR ACCUMULATOR

FINISHES BEFORE

INTEGRATION COUNTER

SEARCH

INTEGRATION COUNTER

FINISHES BEFORE

PHASE ERROR ACCUMULATOR

PHASE ERROR

ACCUMULATOR

PHASE ERROR

FINISHES BEFORE

ACCUMULATOR

FINISHES BEFORE

INTEGRATION

COUNTER

INTEGRATION COUNTER

INTEGRATION

COUNTER

FINISHES BEFORE

PHASE ERROR

ACCUMULATOR

AND VERIFY

INTEGRATION

COUNTER FINISHES

BEFORE

PHASE ERROR

ACCUMULATOR

LOCK

VERIFY

COUNTER DONE

INTEGRATION COUNTER

FINISHES BEFORE

PHASE ERROR

ACCUMULATOR AND

VERIFY COUNTER

NOT DONE

FALSE LOCK

FALSE

LOCK COUNTER

DONE

ACCUMULATOR

BEFORE

LOCK COUNTER

FALSE

LOCK

FALSE

LOCK COUNTER

NOT DONE

FIGURE 18. ACQUISITION/TRACKING STATE DIAGRAM

Serial Output Controller

CLK/

SLOCLK

The frequency correction terms generated by the Symbol

and Carrier Loop Filters are output through two separate

serial interfaces. The symbol frequency offset used to close

the symbol Tracking Loop is output via the SOF and

SOFSYNC outputs. The carrier offset frequency used to

close the Carrier Tracking Loop is output via the COF and

COFSYNC outputs.

COFSYNC/

SOFSYNC

COF/

SOF

MSB

NOTE: COFSYNC and SOFSYNC shown Configured as active

“High”.

The serial output timing, identical for both of the loop ﬁlter

outputs, is shown in Figure 18. The data word is output MSB

ﬁrst starting with the ﬁrst rising edge of either CLK or

SLOCLK that follows the assertion of sync (COFSYNC or

SOFSYNC). The HSP50210 is conﬁgured to output the

serial data with either CLK or SLOCLK (see Serial Output

Conﬁguration Control Registers bit 7, Table 41). The

SLOCLK output is a programmable sub-multiple of CLK

which is provided for applications requiring a slower serial

clock. In applications where the HSP50210 is used with the

HSP50110, both parts must be supplied with the same CLK

and the HSP50210 is conﬁgured to use CLK as the serial

clock. The serial output can be conﬁgured for word

containing from 8 to 40 bits.

FIGURE 19. SERIAL OUTPUT TIMING FOR COF AND SOF

OUTPUTS

Output Selector

The output selector determines which internal signals are

multiplexed to the AOUT9-0 and BOUT9-0 outputs. Fifteen

different output options are provided: ISOFT(2:0), QSOFT(2:0),

IEND(7:1), QEND(7:1), AGC(7:1), MAG(7:0), Phase(7:0),

FREQERR(7:1), GAINERR(7:1), BITPHERR(7:1),

CARPHERR(7:1), LKACC(6:0), LKCNT(6:0), NCOCOS(9:0),

and STATUS (6:0). These are detailed in the Output Selector

Configuration Control Register, bits 0-3 (see Table 42).

3-277

HSP50210

TABLE 11. READ/WRITE ADDRESS MAP FOR

The status bit deﬁnition is:

MICROPROCESSOR INTERFACE (Continued)

STATUS BIT

DEFINITION

R/

W

A2-0

DESCRIPTION

6

5

4

3

2

1

Carrier Tracking Loop Lock

Acq/Trk

W

101 Read Address Register. The address loaded into this

register speciﬁes an internal read point as given the by

address map in Table 12. Addresses outside the range

0-4 are invalid.

Frequency Sweep Direction

High Power

R

000 Selects output holding register bits 7-0 for output on

C7-0 respectively. Bit 0 is the LSB of the internal hold-

ing register.

Low Power

Data Rdy

R

001 Selects output holding register bits 15-8 for output on

C7-0, respectively.

To simplify the output interface, a symbol clock (SMBLCLK)

is output which is synchronous to the soft bit decisions

produced by the Slicer. The SMBLCLK is a 50% duty cycle

clock whose rising edge is centered in the middle of the

output data period for both the soft bit decisions and the end-

symbol samples, as shown in Figure 19.

010 Selects output holding register bits 23-16 for output on

C7-0, respectively.

011 Selects output holding register bits 31-24 for output on

C7-0, respectively. Bit 31 is the MSB.

100 Multiplexes 8 bits of internal status out on C7-0. See

Table 13 for bit map.

SMBLCLK

ISOFT2-0/

QSOFT2-0/

IEND7-1/

Data is read from an Internal Status Register and a series of

output holding registers. The output holding registers range

in size from 8 to 32 bits, and their contents are multiplexed

out a byte at a time on C7-0 by controlling A2-0 and

asserting RD. The addresses listed in Table 11 with the R

indicator provide the address map used for reading data

from the Microprocessor Interface.

QEND7-1

FIGURE 20. OUTPUT DATA CLOCK TIMING

Microprocessor Interface

The Microprocessor Interface is used to write the

HSP50210’s Control Registers and monitor various read

points within the demodulator. Data written to the interface is

loaded into a set of four 8-bit holding registers, one Write

Address Register, or one Read Address Register. These

registers are accessed via the 3-bit address bus (A0-2) and

an 8-bit data bus (C0-7) as shown in Table 11. The R/W

column indicates whether the data is read from or written to

the given address.

Writing to the Microprocessor Interface

The HSP50210 is configured for operation by loading a set

of thirty-two control registers which range in size from 0 to

32 bits. They are loaded by first writing the configuration

data to the Microprocessor interface’s four holding registers

and then writing the target address to the Write Address

Register as shown in Figure 19. The Control Register

Address Map and bit definitions are given in Tables 14 - 45.

The configuration data is transferred from the holding

registers to the target control register on the fourth clock

following a write to the address register. As a result, the

holding registers should not be updated any sooner than 4

CLKs after an address register write (see Figure 20).

TABLE 11. READ/WRITE ADDRESS MAP FOR

MICROPROCESSOR INTERFACE

R/

W

A2-0

DESCRIPTION

W

000 Input Holding Register 0. Transfers to bits 7-0 of the

target control register. Bit 0 is the LSB of the target

register.

NOTE: The holding registers which map to the unused bits of a

particular control register do not have to be loaded.

W

001 Input Holding Register 1. Transfers to bits 15-8 of the

target control register.

Reading from the Microprocessor Interface

010 Input Holding Register 2. Transfers to bits 23-16 of a

32-bit target control register.

The Microprocessor Interface is used to monitor

demodulator operation by providing the ability to read the

accumulator contents in the Lock Detector and Loop

Filters. In addition, the interface is used to monitor the

HSP50210’s Internal Status Register. More clearly, the

following data is available to be read:

011 Input Holding Register 3. Transfers to bits 31-24 of the

target control register. Bit 31 is the MSB of the 32-bit

register.

W

100 Write Address Register. The register is loaded with the

address of the control register targeted for update.

The address map for the control registers is given in

Tables 1C-32C.

NOTE: Addresses outside the range 0-31 are invalid.

3-278

HSP50210

TABLE 12. READ ENABLE ADDRESS MAP

#

REGISTERS

DEFINITION

ADDRESS

HOLDING REGISTER ENABLE

(4)

32-Bit Carrier Loop Letter Lag Acc. Output

0

Carrier Loop Filter Lag Accumulator. Enables output

of holding register containing 32 MSBs of the lag

accumulator.

32-Bit Symbol Tracking Loop Letter Lag Acc. Output

8-Bit AGC Loop Letter Output

(1)

1

Symbol Tracking Loop Filter Lag Accumulator.

Enables output of holding register containing 32

MSBs of the lag accumulator.

(2)

16-Bit Lock Detector φe Acc. Output

16-Bit Lock Detector GE Acc. Output

16-Bit Lock Detector FL/FE Acc. Output

8-Bit Internal Status

(2)

2

3

AGC GAIN. Enables output of holding register

containing 8 MSBs of the AGC accumulator.

(2)

Lock Detector 1. The 16 MSBs of the Lock

Detector’s Phase Error Accumulator and the 16

MSB’s of the False Lock Accumulator are enabled

for output. The accumulator contents are selected

for output as follows, A2-0 = 3 (decimal) selects

MSByte of the Phase Error Accumulator, A2-0 = 2

(decimal) selects LSByte of the Phase Error

Accumulator, A2-0 = 1 (decimal) selects MSByte of

the False Lock Accumulator, and A2-0 = 0 (decimal)

selects LSByte of the False Lock Accumulator.

(1)

Total = 16

A different read procedure is required depending on

whether the Lock Detector Accumulators, loop filter

accumulators, or the Status Register is to be read. The

read procedures are summarized in Figures 21 - 23.

The accumulators in the AGC Loop Filter, Carrier Loop

Filter and Symbol Tracking Loop can be read via the

Microprocessor Interface. Since these accumulators are

free running, their contents must be loaded into output

holding registers before they can be read. Each

4

Lock Detector 2. Enables the 16 MSBs of the Lock

Detector’s Gain Error Accumulator for output. The

MSByte of the accumulator is selected for output by

setting A2-0 = 1, and the LSByte is selected by

A2-0 = 0.

accumulator has its own output holding register. The three

holding registers are updated by loading 29 (decimal) into

the Write Address Register of the Microprocessor Interface.

The output of a particular holding register is then enabled

for reading by loading its address into the Read Address

Register (see Tables 13 and 14). The holding register

addresses for the loop filter accumulators range from 0 to 4

as given in Table 12. The contents of the output holding

registers are multiplexed out a byte at a time on C7-0 by

changing A2-0 and asserting RD (see Read/Write Address

Map in Table 11).

The contents of the three accumulators in the Lock Detector

can also be read via the Microprocessor Interface. However,

the Lock Detector must be stopped before a read can be

performed. In State Machine Control Mode, the Lock

Detector is stopped by loading 24 (decimal) into the Write

Address Register. In Microprocessor Control Mode, the Lock

Detector stops after each Integration Period. To determine

when the Lock Detector has stopped and is ready for

reading, bits 7 and 6 of the Internal Status Register (SR7&6)

must be monitored (see Table 15). The control sequence for

reading a Lock Detector Accumulator is shown in Figure 22.

The control sequence for reading a Lock Detector

Accumulator using the LKINT signal is shown in Figure 23.

An 8-bit Internal Status Register (SR7-0) can also be

monitored via the Microprocessor interface. The Status

Register indicates loop filter and Lock Detector status as

listed in Table 13. The Status Register contents are output

on C7-0 by setting A2-0 to 100(binary) an asserting RD as

shown in Figure 24. The register contents are updated

each CLK.

3-279

HSP50210

WR

RD

DON’T CARE

0

1

2

3

4

0

1

A0-2

C0-7

CLK

1

2

3

4

EARLIEST TIME ANOTHER

LOAD CAN BEGIN

NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify

that the processor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. The Processor wave-

forms are not required to be synchronous to CLK. They are shown that way to clarify the illustration.

FIGURE 21. CONTROL REGISTER LOADING SEQUENCE

WR

RD

DON’T CARE

ADDRESS IS ASYNCHRONOUS TO CLK

A0-2

C0-7

4

5

0

3

2

1

0

DATA IS

29

MSB

LSB

ASYNCHRONOUS

TO CLK

1

2

3

4

5

6

CLK

1

2

3

4

5

LOAD OUTPUT ENABLE

HOLDING REG HOLDING

WAIT

6 CLKs

READ

DELAY

TO

RD

REG

FOR

READ

ASSERT

NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify

that the processor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. The Processor wave-

forms are not required to be synchronous to CLK. They are shown that way to clarify the illustration.

1

2

3

4

5

Load the Write Address Register with 29

dec

to load the output holding registers.

Enable Carrier Loop Filter Lag Accumulator holding register for reading.

Select the MSByte of the output holding register for output.

Assert RD low to output data on C0-7. (Must wait for 6 CLKs after loading the holding registers).

Select other bytes of holding register by changing A0-2 and asserting RD.

FIGURE 22. LOOP FILTER ACCUMULATOR READ SEQUENCE

3-280

HSP50210

WR

RD

4

5

3

4

3

2

1

0

4

A0-2

C0-7

24

30

25

PE

FL

MSW

FL

LSW

MSW

LSW

SR7=0

SR7=1

CLK

SR-7

10

1

2

3 4

5

6 7

8

6

8

6

8

6

8

9

HALT LD

AT END OF

CYCLE

ENABLE

INTERNAL

LOCK DETECTION STATUS READS

RESET

LOCK

RESTART

LOCK

LD REG. STATUS READS

FOR READING

DETECTOR DETECTOR

NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify

that the processor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. The Processor wave-

forms are not required to be synchronous to CLK. They are shown that way to clarify the illustration.

1

Load the Write Address Register with 24

to halt the Lock Detector after the current integration cycle. This disables the reload of the integration

counter in the lock detector. The verify counter is not reset and will resume at the stopped value when the lock detector is restarted.

dec

2

3

4

5

6

7

8

9

Load the Read Address Register with 3

to enable the Lock Detector Phase Error Accumulator for reading.

dec

Read Internal Status Register to monitor SR-7 to determine when the Lock Detector is stopped and ready to be read.

SR-7 goes high, indicating the Lock Detector integration cycle is complete, and ready to be read.

Read Internal Status Register and ﬁnd SR-7 = 1; the Lock Detector is ready to be read.

Change Read address to (3; 2; 1; 0) for (Phase Error MSW; PE LSW; False Lock MSW; FL LSW) read.

End of Internal Status Valid Data.

Assert RD to Read Lock Detector Status

Load The Write Address Register with 30

machine mode).

to initialize Lock Detector Accumulators and Reset the Integration counters. (Not needed for state

to restart the Lock Detector.

dec

10

Load the Write Address Register with 25

dec

FIGURE 23. PROCESSOR MONITORING INTERNAL STATUS/READING LOCK DETECTOR

TABLE 13. INTERNAL STATUS REGISTER (SR7-0) BIT MAP

BIT

BIT DESCRIPTION

BIT

BIT DESCRIPTION

7

6

5

Lock Detector Stopped and Ready for Reading

(State Machine Control Mode).

0 = Lock Detector not stopped.

3

Lock. Carrier Lock state achieved by Lock Detector.

0 = Not locked.

1 = Locked.

1 = Lock Detector stopped, ready for read.

2

Acquisition/Track. Indicates whether the Lock Detector is in

acquisition or tracking mode.

0 = Tracking Mode.

Lock Detector Stopped and Ready for Reading

(Microprocessor Control Mode).

0 = Lock Detector not stopped.

1 = Acquisition Mode.

1 = Lock Detector stopped, ready for read.

1

0

Reserved.

Carrier Loop Filter Lag Accumulator Load Complete. This bit

is used to determine when a 32-bit load of Carrier Lag Accu-

mulator is complete. The accumulator load is initialized by

loading the Write Address Register with 13 (decimal) as de-

scribed in Table 27.

Frequency Sweep Direction, deﬁned for upper sideband sig-

nals.

0 = UP.

1 = DOWN.

0 = Load not complete.

1 = Load complete.

4

Symbol Tracking Loop Filter Lag Accumulator Load

Complete. This bit is used to determine when a 32-bit load

of Symbol Track Lag Accumulator is complete. The

accumulator load is initialized by loading the Write Address

Register with 19 (decimal) as described in Table 33.

0 = Load not complete.

1 = Load complete.

3-281

HSP50210

WR

RD

A0-2

5

3

2

1

0

4

PE

FL

MSW

FL

LSW

C0-7

30

25

MSW

LSW

CLK

SR-7

LKINT

1

2

3

4

5

6

5

6

5

6

5

7

8

9

10

NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify

that the processor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. The Processor wave-

forms are not required to be synchronous to CLK. They are shown that way to clarify the illustration.

1

2

3

4

5

6

7

8

LKINT Asserts Indicating End of Lock Detector Accumulation Cycle; Accumulators Ready to Read.

Set A0-2 to 5 for Reading Lock Detector.

Load Read Address Register with 3

to enable the Lock Detector Phase Error Accumulator for Reading

dec

Set A0-2 to 3 for Phase Error (PE) Read.

Assert RD and read (Phase Error (PE) MSW; PE LSW; False Lock (FL) MSW; FL LSW).

Change Read Address to (2; 1; 0) to read various Lock Detection values.

Change Address to 4 to Initialize the Lock Detector.

Load Write Address Register with 30

mode).

to initialize the Lock Detector Accumulators and Reset Integration Counters. (Only has an effect in µP

dec

9

Keep Address to 4 to Restart the Lock Detector.

10

Load Write Address Register with 25

dec

to restart the Lock Detector. (Only necessary if not in the µP mode).

FIGURE 24. PROCESSOR INTERRUPT MONITOR/LOCK DETECTOR READ

.

CLK

RD

A0-2

4

C7-0

STATUS CAN CHANGE EVERY CLK

FIGURE 25. INTERNAL STATUS REGISTER READ

3-282

HSP50210

TABLE 14. DATA PATH CONFIGURATION CONTROL REGISTER

DESTINATION ADDRESS = 0

BIT

POSITION

FUNCTION

Reserved

DESCRIPTION

Reserved. Set to 0 for proper operation.

31-27

26-24

Integrate/Dump Shifter

Gain

These bits set the shifter attenuation in the Integrate/Dump Filter.

0

000 = No Shift (Gain = 2 ).

001 = Right Shift 1 (Gain = 2 ).

010 = Right Shift 2 (Gain = 2 ).

011 = Right Shift 3 (Gain = 2 ).

-1

-2

-3

-4

100 = Right Shift 4 (Gain = 2 ).

Other Codes are invalid.

23-16

Input Level Detector

Threshold

This register sets the magnitude threshold for the Input Level Detector (see Input Level Detector

Section). This 8-bit value is a fractional unsigned number whose format is given by:

0

-1 -2 -3 -4 -5 -6 -7

2 . 2 2 .

2

The possible threshold values range from 0 to 1.9961 (00 - FF hex). The magnitude range for complex

inputs is 0.0 - 1.4142 while that for real inputs is 0.0 - 1.0. Note: The algorithm used to estimate

threshold produces a maximum output of 1.375, therefore a threshold of greater than 1.375 will

never be exceeded.

15

14

13

12

11

10

9

Input Data Format Select 0 = Two’s Complement Input .

1 = Offset binary Input.

Serial/Parallel Input

Select

0 = Parallel Input.

1 = Serial Input.

Input Level Detector

Output Select

0 = HI/LO output of 1 means input ≤ threshold .

1 = HI/LO output of 1 means input > threshold.

Q Input to Complex

Multiplier

0 = QIN9-0 enabled to Complex Multiplier.

1 = Q input to Complex Multiplier zeroed.

I Input to Complex

Multiplier

0 = IIN9-0 enabled to Complex Multiplier.

1 = I input to complex multiplier set to negative full scale (200 Hex).

Complex Multiplier

Bypass

0 = Data enabled to Complex Multiplier (Multiplied by output of NCO).

1 = Complex Multiplier Bypassed.

Demodulation/Loop

Filter Mode

Select

0 = Error detector outputs routed to Loop Filters (Normal Mode of Operation).

1 = Part functions as dual Loop Filters. The IIN9-0 input is routed to the Symbol Loop Filter; the QIN9-

0 input is routed to the Carrier Loop Filter. Data is gated into the Loop Filters with the assertion of SYNC.

8

7

6

Cartesian/Polar Input

Select

0 = Enable output of AGC Multiplier to Cartesian to Polar Converter.

1 = Enable output of Integrate and Dump Filter to the Cartesian to Polar Converter.

RRC Filter Enable

0 = Enable RRC filter.

1 = Bypass RRC filter.

Integrate and Dump

Filter Test Mode

0 = End-Symbol Samples routed to Output Formatter.

1 = Both End and Mid Symbol routed to Output Formatter: End-symbol samples occur when

SMBLCLK is high; Mid-Symbol samples occur when SMBLCLK is low.

5

Integrate and Dump

Input Select

0 = Input taken from output of Frequency Discriminator (FSK routing).

1 = Input taken from output of AGC Multiplier (Select this setting for PSK demodulation).

4-1

Integrate and Dump

Decimation Select

Bit 4 is the MSB.

1000 = No Decimation (no accumulation, no sample pair summing).

0000 = Decimation by 2 (no accumulation, sample pair summing).

0001 = Decimation by 4 (accumulate 2 samples, sample pair summing).

0010 = Decimation by 8 (accumulate 4 samples, sample pair summing).

0011 = Decimation by 16 (accumulate 8 samples, sample pair summing).

0100 = Decimation by 32 (accumulate 16 samples, sample pair summing).

All other codes are invalid.

0

OQPSK Data

0 = Disables Q channel data delay.

De-Skew Select

1 = Delays Q Channel by 1/2 Symbol time to remove OQPSK stagger.

3-283

HSP50210

TABLE 15. POWER DETECT THRESHOLD CONTROL REGISTER

DESTINATION ADDRESS = 1

BIT

POSITION

FUNCTION

Not Used

DESCRIPTION

31-8

7-0

No programming required.

Power Threshold

The THRESH output is driven low when the magnitude output of the Cartesian to Polar Converter

exceeds the threshold programmed here. The threshold is represented as an 8-bit fractional unsigned

value with the following format:

0

-1 -2 -3 -4 -5 -6 -7

2 . 2

2

2 .

Using this format, the possible range of threshold values is between 0 to 1.9961. Bit position 7 is the MSB.

TABLE 16. AGC LOOP PARAMETERS CONTROL REGISTER

DESTINATION ADDRESS = 2

BIT

POSITION

FUNCTION

DESCRIPTION

31

Enable AGC

0 = Gain error enabled to AGC Loop Filter.

1 = Gain error into AGC Loop Filter set to zero.

30-28

AGC Loop Gain

Exponent (E)

These bits set the loop gain exponent as given by:

-(7 + EEE)

AGC Loop Gain Exponent = 2

-7

-14

where EEE corresponds to the 3-bit binary value programmed here. Thus, a gain range from 2 to 2

may be achieved for EEE = 000 to 111 Binary. Bit position 30 is the MSB. See Table 3.

27-24

23-16

AGC Loop Gain

Mantissa (M)

The loop gain mantissa is represented as a 4-bit unsigned value with the following format:

-1 -2 -3 -4

AGC Loop Gain Mantissa = 0. 2

2 2 2 ; 0.MMMM.

This format provides a mantissa range from 0.0 to 0.9375 for mantissa settings from 0000 to 1111 Binary.

Bit position 27 is the MSB. Mantissa resolution = 0.0625. See Table 2.

AGC Threshold

The AGC gain error is generated by subtracting the threshold value programmed here from the

magnitude value out of the Cartesian to Polar Converter. The binary format for the AGC Threshold is the

same as that for the Power Threshold given in Table 15.

AGC THRESHOLD

VALUE

RESULTING OUTPUT

LEVEL (dBFS)

1.1453 (42h)

0.8108 (67h)

0.5740 (49h)

0.4064 (34h)

0.2877 (24h)

0

-3

-6

-9

-12

15-8

7-0

AGC Upper Limit

AGC Lower Limit

The upper 8 bits of the AGC Accumulator set the AGC gain as given by Equation 8A. The value

programmed here sets upper limit for AGC gain by specifying a limit for the upper 8 bits of the AGC

accumulator. If the accumulated sum exceeds the upper limit, the accumulator is loaded with the limit.

These bits are packed as eemmmmmm where the e’s correspond to the exponent bits and the m’s

correspond to the mantissa bits of Equation 8 (see also Figure 8). Bit position 15 is the MSB. By setting the

AGC upper and lower limits to the same value, the AGC can be set to a fixed gain.

The value programmed here sets the lower limit for the upper 8 bits of the AGC accumulator in a manner

similar to that described for the upper limit. If the accumulated sum falls below the lower limit, the

accumulator is loaded with the limit. The format for these bits is as described for the upper limit. By setting

the AGC upper and lower limits to the same value, the AGC can be set to a fixed gain.

TABLE 17. CARRIER PHASE ERROR DETECTOR CONTROL REGISTER

DESTINATION ADDRESS = 3

BIT

POSITION

FUNCTION

Not Used

DESCRIPTION

No programming required.

31-8

7-6

Reserved

Reserved. Set to 0 for proper operation.

3-284

HSP50210

TABLE 17. CARRIER PHASE ERROR DETECTOR CONTROL REGISTER (Continued)

DESTINATION ADDRESS = 3

BIT

POSITION

FUNCTION

DESCRIPTION

5-2

Phase Offset

These bits set the phase offset added (modulo 2π) to the phase output of the Cartesian to Polar

Converter. The phase offset is represented as a 4-bit fractional 2’s Complement value with the following

binary format:

0

-1 -2 -3.

Phase Offset = -2 . 2

2

This format provides a range from 0.875 to -1 (0111 to 1000) which corresponds to phase offset settings

o

from 7π/8 to -π respectively. Resolution of 22.5 is provided. Bit position 5 is the MSB.

1-0

Shift Factor

The bits set the left shift required by the Carrier Phase Error Detector. These two bits specify a left shift

of 0, 1, 2 or 3 places. MSBs are discarded and LSBs are zero-filled. Bit 1 is the MSB.

TABLE 18. FREQUENCY DETECTOR CONTROL REGISTER

DESTINATION ADDRESS = 4

BIT

POSITION

FUNCTION

DESCRIPTION

No programming required.

31-8

7-3

Not Used

Reserved

Reserved. Set to 0 for proper operation.

2-0

Discriminator Delay

The frequency detector (discriminator) computes frequency by subtracting a delayed phase term from

the current phase term (dθ/dt). A programmable delay is used to set the discriminator gain. These bits

set the delay as given by:

K

Delay = 2 ,

where K is the 3-bit value programmed here. Delays of 1, 2, 4, 8, and 16 are possible.

TABLE 19. FREQUENCY ERROR DETECTOR CONTROL REGISTER

DESTINATION ADDRESS = 5

BIT

POSITION

FUNCTION

Not Used

DESCRIPTION

31-8

7-3

No programming required.

Frequency Offset

These bits set the frequency offset added (modulo) to the frequency output of the discriminator. The frequency

offset is represented as a 5-bit fractional 2’s complement value with the following binary format:

0

-1 -2 -3 -4.

Frequency Offset = -2 . 2

2 2 2

This format provides a range from 0.9375 to -1.0 (0111 to 1000). The range and resolution of the

frequency offset depend on the discriminator delay and input rate. The frequency offset is added to the

5 MSBs of the discriminator output. Note: Set the frequency offset to 0 when using frequency aided

acquisition with PSK waveforms.

2-0

Shift Factor

These bits set the left shift required by the Frequency Error Detector. These two bits set a left shift of 0,

1, 2, 3, or 4 places. Bit 2 is the MSB. Values greater than 4 are invalid. Note: Set the shift factor to 0

when using frequency aided acquisition with PSK waveforms.

TABLE 20. CARRIER LOOP FILTER CONTROL REGISTER #1

DESTINATION ADDRESS = 6

BIT

POSITION

FUNCTION

Not Used

DESCRIPTION

No programming required.

31-8

7

6

Reserved

Reserved. Set to 0 for proper operation.

Lead/Lag to Serial

Output Routing

0 = The Carrier Loop Filter’s Lag Accumulator is routed to the Serial Output Controller.

1 = The lead and lag paths in the Carrier Loop Filter are summed and routed to the Serial Output

Controller.

5

Lead/Lag to Internal

NCO Routing

0 = Sum of lead and lag paths routed to the internal NCO. (32 MSBs of sum are routed).

1 = The lead term is routed to the internal NCO. (32 MSBs of lead term are routed).

3-285

HSP50210

TABLE 20. CARRIER LOOP FILTER CONTROL REGISTER #1 (Continued)

DESTINATION ADDRESS = 6

BIT

POSITION

FUNCTION

DESCRIPTION

4-0

Error Accumulation

These bits set the number of phase and frequency error measurements that are accumulated before the

Carrier and AFC Loop Filters are run. Since the Loop Filters can only accept new inputs every 6 CLKs

(normally at the symbol rate), the error accumulation is required to ensure that no phase or frequency

error outputs are missed when error terms are generated at a rate greater than 1/6 CLK (see Carrier

Phase Error Detector Section). The 5-bit value programmed here should be set to one less than the

desired number of error terms to accumulate. For example, setting these bits to 0011 (BINARY) would

cause 4 error terms to be accumulated. A total range from 1 to 32 is provided.

When error accumulation is used, divide the Lead Gain by the number of errors accumulated. Note that

the LAG Gain does not need to be scaled since it increases to compensate for the delay, since it is an

accumulator.

TABLE 21. CARRIER LOOP FILTER CONTROL REGISTER #2

DESTINATION ADDRESS = 7

BIT

POSITION

FUNCTION

Not Used

DESCRIPTION

No programming required.

31-8

7-6

5

Reserved

Reserved. Set to 0 for proper operation.

Lead Phase Error

Enable

0 = Carrier Phase Error enabled to lead processing path of loop filter.

1 = Carrier Phase Error to lead processing path of loop filter zeroed.

4

3

2

1

0

Lag Phase Error

Enable

0 = Carrier Phase Error enabled to lag processing path of loop filter.

1 = Carrier Phase Error to lag processing path of loop filter zeroed (First Order Loop).

AFC Enable

0 = Frequency error enabled to lag processing path of Carrier Loop Filter.

1 = Frequency error zeroed.

Carrier Sweep Enable 0 = Frequency sweep input to the lag path of the Carrier Loop Filter enabled.

1 = Sweep input to Carrier Loop Filter zeroed.

Invert Carrier Phase

Error

0 = Carrier Phase Error is normal into Carrier Loop Filter.

1 = Carrier Phase Error is inverted into Carrier Loop Filter.

Invert Carrier

Frequency Error

0 = Carrier Frequency Error is normal into AFC loop filter.

1 = Carrier Frequency Error is inverted into AFC Loop filter.

TABLE 22. CARRIER LOOP FILTER UPPER LIMIT CONTROL REGISTER

DESTINATION ADDRESS = 8

BIT

POSITION

FUNCTION

DESCRIPTION

31-0

Carrier Loop Filter

Upper limit

The 32-bit two’s complement value programmed here sets the upper sweep and tracking limit of the Carrier

Loop Filter by setting the upper limit of the loop filter’s lag accumulator. If the limit is exceeded, the upper 32

bits of the 40-bit accumulator are set to the limit, and the 8 LSBs are set to zero.

TABLE 23. CARRIER LOOP FILTER LOWER LIMIT CONTROL REGISTER

DESTINATION ADDRESS = 9

BIT

POSITION

FUNCTION

DESCRIPTION

31-0

Carrier Loop Filter

Lower limit

The 32-bit two’s complement value programmed here sets the Lower sweep and tracking limit of the Carrier

Loop Filter by setting the lower limit of the loop filter’s lag accumulator. If the running sum falls below the limit,

the upper 32 bits of the 40-bit accumulator are set to the limit, and the 8 LSBs are set to zero.

3-286

HSP50210

TABLE 24. CARRIER LOOP FILTER GAIN (ACQ) CONTROL REGISTER

DESTINATION ADDRESS = 10

BIT

POSITION

FUNCTION

Not Used

DESCRIPTION

No programming required.

31-24

23-18

17-14

Reserved

Reserved. Set to 0 for proper operation.

Carrier Lead Gain

Mantissa (Acquisition) Lead Gain Mantissa = 0 1. 2

These bits are the 4 fractional bits of the lead gain mantissa shown below.

-1 -2 -3 -4.

2 2 2

This format provides a mantissa range from 1.0 to 1.9375 for mantissa settings from 0000 to 1111 Binary.

Bit position 17 is the MSB.

13-9

Carrier Lead Gain

Exponent (Acquisition)

These bits set the lead gain exponent as given by:

-(32-E).

Carrier Lead Gain Exponent = 2

where E corresponds to the 5-bit binary value programmed here. Thus, a gain range from

-1

-32

2

to 2

(relative to the MSB position of the NCO control word) may be achieved for E = 11111 to 00000

Binary. Bit position 13 is the MSB.

8-5

4-0

Carrier Lag Gain

Mantissa (Acquisition)

Format same as lead gain mantissa. Bit position 8 is the MSB.

Carrier Lag Gain

Format same as lead gain exponent. Bit position 4 is the MSB.

Exponent (Acquisition)

TABLE 25. CARRIER LOOP FILTER GAIN (TRK) CONTROL REGISTER

DESTINATION ADDRESS = 11

BIT

POSITION

FUNCTION

Not Used

DESCRIPTION

No Programming required.

31-24

23-18

17-14

Reserved

Reserved. Set to 0 for proper operation.

Carrier Lead Gain

Mantissa (Track)

Format same as lead gain mantissa (see Table 24). Bit position 17 is the MSB.

13-9

8-5

Carrier Lead Gain

Exponent (Track)

Format same as lead gain exponent (see Table 24). Bit position 13 is the MSB.

Format same as lead gain mantissa (see Table 24). Bit position 8 is the MSB.

Format same as lead gain exponent (see Table 24). Bit position 4 is the MSB.

Carrier Lag Gain

Mantissa (Track)

4-0

Carrier Lag Gain

Exponent (Track)

TABLE 26. FREQUENCY SWEEP/ AFC LOOP CONTROL REGISTER

DESTINATION ADDRESS = 12

BIT

POSITION

FUNCTION

DESCRIPTION

31-27

26-23

Reserved

Reserved. Set to 0 for proper operation.

Sweep Rate Mantissa Sets carrier track sweep rate used during acquisition (see Frequency Sweep Block Section). Format

(Acquisition) same as lead gain mantissa (see Table 24). Bit position 22 is the MSB.

22-18

Sweep Rate Exponent Sets carrier track sweep rate used during acquisition (see Frequency Sweep Block Section). Format

(Acquisition)

same as lead gain exponent (see Table 24). Bit position 22 is the MSB. M = 0000,

-28

E = 00000 is 2

.

17-14

13-9

AFC Gain Mantissa

(Acquisition)

Sets Frequency Error Gain. Format same as lead gain mantissa (see Table 24). Bit position 11 is the

MSB.

AFC Gain Exponent

(Acquisition)

Sets Frequency Error Gain. Format same as lead gain exponent (see Table 24). Bit position 4 is the MSB.

3-287

HSP50210

TABLE 26. FREQUENCY SWEEP/ AFC LOOP CONTROL REGISTER (Continued)

DESTINATION ADDRESS = 12

BIT

POSITION

FUNCTION

DESCRIPTION

8-5

AFC Gain Mantissa

(Track)

Sets Frequency Error Gain. Format same as lead gain mantissa (see Table 24). Bit position 11 is the

MSB.

4-0

AFC Gain Exponent

(Track)

Sets Frequency Error Gain. Format same as lead gain exponent (see Table 24). Bit position 4 is the MSB.

TABLE 27. CARRIER LAG ACCUMULATOR INITIALIZATION CONTROL REGISTER

DESTINATION ADDRESS = 13

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

Carrier Lag

Accumulator

Initialization

Writing this address initializes the lag accumulator with the contents of the 4 Microprocessor Interface

Holding Registers at the start of the next Carrier Loop FIlter Computation cycle. The contents of the hold-

ing registers should not be changed until after the start of a new compute cycle, since the current contents

of the holding registers are loaded at the compute cycle start. The Microprocessor Interface can be used

to read an Internal Status Register which signals when the lag accumulator load is complete (see Micro-

processor Interface Section). The contents of the holding registers are loaded into the 32 MSBs of the

lag accumulator and the 8 LSBs are zeroed.

It is good practice to load the LAG Accumulators at the very end of a conﬁguration load sequence.

TABLE 28. SYMBOL TRACKING LOOP CONFIGURATION CONTROL REGISTER

DESTINATION ADDRESS = 14

BIT

POSITION

FUNCTION

DESCRIPTION

31-16

15-13

12-11

Not Used

Reserved

No programming required.

Reserved. Set to 0 for proper operation.

Sampling Error Shift

Factor

The sampling error shifter is provided to left shift the sampling error to full scale before input to the Symbol

Tracking Loop Filter. The magnitude of the sampling error varies with the number of symbol decision levels,

and a left shift of 1 to 4 places is provided as required by modulation order. Suggested settings are provided

below:

00 = x2 2 levels on each rail (BPSK, QPSK).

01 = x4 4 levels on each rail (8 PSK).

10 = x8 8 levels on each rail.

11 = x16 16 levels on each rail.

Note: Saturation is provided in case of overﬂow.

10-9

Modulation Order

Select

These bits set the threshold levels used by the symbol decision blocks in the Sampling Error detector. The

end-symbol samples on either the I or Q processing path are compared against the selected threshold set

to determine the expected symbol value used in calculating the transition midpoint. The threshold levels

can be set for up to 16ary signals on both the I and Q processing path. The decision thresholds are set as

given below.

00 = 2ary signal (Use this setting for BPSK, QPSK, and OQPSK signals).

01 = 4ary signal.

10 = 8ary signal.

11 = 16ary signal.

The threshold levels are determined by equally dividing up the signal range by the order of the signal. For

example, a 2ary signal would divide the ~1.0 to -1.0 signal range by two forcing threshold at 0.0. A 4ary

signal would have thresholds at:

-0.5, 0, and +0.5.

3-288

HSP50210

TABLE 28. SYMBOL TRACKING LOOP CONFIGURATION CONTROL REGISTER (Continued)

DESTINATION ADDRESS = 14

BIT

POSITION

FUNCTION

DESCRIPTION

8

Single/Double Rail

Sampling Error

This bit sets whether sampling error is derived from symbol transitions on just the I rail (single rail) or both

the I&Q rails (dual rail). In single rail operation sampling error from the Q rail is nulled and only the I rail is

used. In dual rail operation the sampling error from both the I an Q rails is summed and then scaled by one

half.

0 = Dual Rail Operation.

1 = Single Rail Operation.

Note: Set to 1 for BPSK operation and 0 for QPSK operation.

7-3

Sampling Error

Accumulation

These bits set the number of sampling error measurements to accumulate before running the Symbol Loop

Filter. The loop ﬁlter requires 8 CLKs to compute an output. The sampling error detector generates error

terms at the symbol rate. Thus, the error accumulator must be used if the symbol rate exceeds 1/8 CLK to

ensure that no error terms are missed (see Sampling Error Detector Section). The 5-bit value programmed

here is set to one less than the desired number of error terms to accumulate. For example, setting these

bits to 00011 (BINARY) would cause 4 error terms to be accumulated. A total range from 1 to 32 is provided.

2

1

0

Lead Sampling Error 0 = Sampling error enabled to lead path of loop ﬁlter.

Enable

1 = Sampling error to lead path of loop ﬁlter zeroed.

Lag Sampling Error

Enable

0 = Sampling error enabled to lag path of loop ﬁlter.

1 = Sampling error to lag path of loop ﬁlter zeroed (First Order Loop).

Invert Sampling Error 0 = Sampling error normal.

1 = Sampling error inverted.

TABLE 29. SYMBOL TRACKING LOOP FILTER UPPER LIMIT CONTROL REGISTER

DESTINATION ADDRESS = 15

BIT

POSITION

FUNCTION

DESCRIPTION

31-0

Symbol Tracking

Loop Filter Upper

Limit

The 32-bit two’s complement value programmed here sets the upper tracking limit of the Symbol Tracking Loop

Filter by setting the upper limit of the loop filter’s lag accumulator. If the limit is exceeded, the upper 32 bits of the

40-bit accumulator are set to the limit, and the 8 LSBs are set to zero.

TABLE 30. SYMBOL TRACKING LOOP FILTER LOWER LIMIT CONTROL REGISTER

DESTINATION ADDRESS = 16

BIT

POSITION

FUNCTION

DESCRIPTION

31-0

Symbol Tracking

Loop Filter Lower

Limit

The 32-bit two’s complement value programmed here sets the Lower tracking limit of the Symbol Tracking Loop

Filter by setting the lower limit of the loop filter’s lag accumulator. If the running sum falls below the limit, the upper

32 bits of the 40-bit accumulator are set to the limit, and the 8 LSBs are set to zero.

TABLE 31. SYMBOL TRACKING LOOP FILTER GAIN (ACQ) CONTROL REGISTER

DESTINATION ADDRESS = 17

BIT

POSITION

FUNCTION

DESCRIPTION

31-24

23-18

17-14

Not Used

Reserved

No programming required.

Reserved. Set to 0 for proper operation.

Symbol Tracking

Lead Gain Mantissa

(Acquisition)

These bits are the 4 fractional bits of the lead gain mantissa shown below:

-1 -2 -3 -4.

Symbol Tracking Lead Gain Mantissa = 01. 2

2 2 2

This format provides a mantissa range from 1.0 to 1.9375 for mantissa settings from 0000 to 1111 Binary.

Bit position 17 is the MSB.

3-289

HSP50210

TABLE 31. SYMBOL TRACKING LOOP FILTER GAIN (ACQ) CONTROL REGISTER (Continued)

DESTINATION ADDRESS = 17

BIT

POSITION

FUNCTION

DESCRIPTION

These bits set the lead gain exponent as given by:

13-9

Symbol Tracking

Lead Gain Exponent

(Acquisition)

-(32-E),

Symbol Tracking Lead Gain Exponent = 2

where E corresponds to the 5-bit binary value programmed here. Thus, a gain range from

-1 -32

2

to 2

relative to the MSB position of the NCO control word may be achieved for E = 11111 to 00000

Binary. Bit position 13 is the MSB.

8-5

4-0

Symbol Tracking Lag Format same as lead gain mantissa. Bit position 8 is the MSB.

Gain Mantissa

(Acquisition)

Symbol Tracking Lag Format same as lead gain exponent. Bit position 4 is the MSB.

Gain Exponent

(Acquisition)

TABLE 32. SYMBOL TRACKING LOOP FILTER GAIN (TRK) CONTROL REGISTER

DESTINATION ADDRESS = 18

BIT

POSITION

FUNCTION

DESCRIPTION

31-24

23-18

17-14

Not Used

Reserved

No programming required.

Reserved. Set to 0 for proper operation.

Symbol Tracking Lead Gain Mantissa

(Track)

Format same as lead gain mantissa (see Table 31). Bit position 17 is the MSB.

13-9

8-5

Symbol Tracking Lead Gain Exponent

(Track)

Format same as lead gain exponent (see Table 31). Bit position 13 is the MSB.

Format same as lead gain mantissa (see Table 31). Bit position 8 is the MSB.

Format same as lead gain exponent (see Table 31). Bit position 4 is the MSB.

Symbol Tracking Lag Gain Mantissa

(Track)

4-0

Symbol Tracking Lag Gain Exponent

(Track)

TABLE 33. SYMBOL TRACKING LOOP FILTER LAG ACCUMULATOR INITIALIZATION CONTROL REGISTER

DESTINATION ADDRESS = 19

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

Symbol Tracking Loop Writing to this address initializes the lag accumulator with the contents of the four Microprocessor

Filter Lag Accumulator Interface Holding Registers at the start of the next loop filter computation cycle. The contents of the

Initialization

holding registers should not be changed until after the start of a new compute cycle since the current

contents of the holding registers are loaded at the compute cycle start. At a slow rate, it could take 1 low

rate symbol time to change. The Microprocessor Interface should be used to read an internal status

register which signals when the lag accumulator load is complete (see Table 13 in the Microprocessor

Interface Section). The contents of the holding registers are loaded into the 32 MSBs of the lag

accumulator and the 8 LSBs are zeroed.

It is a good practice to load the LAG accumulators at the very end of a configuration load sequence.

3-290

HSP50210

TABLE 34. LOCK DETECTOR CONFIGURATION CONTROL REGISTER

DESTINATION ADDRESS = 20

BIT

POSITION

FUNCTION

Reserved

False Lock

DESCRIPTION

Reserved. Set to 0 for proper operation.

31-28

27

This bit selects the input to the False Lock Accumulator.

Accumulator Operation 0 = Frequency Error input enabled to accumulator.

1 = False Lock Bit enabled to accumulator.

26-20

Dwell Counter

Pre-load

The Dwell Counter holds off the Lock Accumulator integration for the number of integration cycles

programmed here. The length of the integration cycle is set in the bit positions 19-10. The 7-bit value

programmed here should be set to 1 less than the desired hold off time in integration cycles. The pre-

load is zeroed during Track Mode. Only used during stepped acquisition mode.

19-10

9-0

Integration Counter

Pre-Load

(Acquisition)

The Integration Counter controls the number Phase Error samples accumulated by the Lock

Accumulator. The 10-bit number loaded here is set to two less than the number of Phase Error samples

desired in the Integration Period. Total Range 2-1025. Bit 19 is the MSB.

Integration Counter

Pre-Load (Track)

Function is identical to Acquisition Integration Counter Pre-Load. See above.

TABLE 35. LOCK ACCUMULATOR PRE-LOADS CONTROL REGISTER

DESTINATION ADDRESS = 21

BIT

POSITION

FUNCTION

DESCRIPTION

31-16

Lock Accumulator Pre- The lock threshold is set by an accumulator pre-load which is backed off from the accumulator full scale

Load

(Acquisition)

by the threshold amount. The Lock Accumulator is 18 bits and the accumulator bit weightings relative to

the magnitude of the Phase Error input and the pre-load is given below:

BIT WEIGHTING OF ACCUMULATOR PRE-LOAD

10

9

8

7

0

-1 -2 -3 -4 -5 -6 -7

2

2 2 2 ......2 . 2

2

BIT WEIGHTING OF

PHASE ERROR MAGNITUDE

BINARY POINT

11

The accumulator roll over is at the 2 bit position.

15-0

Lock Accumulator Pre- Function is identical to Acquisition Lock Accumulation Pre-Load. See above.

Load (Track)

TABLE 36. FALSE LOCK ACCUMULATOR PRE-LOAD CONTROL REGISTER

DESTINATION ADDRESS = 22

BIT

POSITION

FUNCTION

False Lock

DESCRIPTION

31-16

Depending on configuration, the input to the False Lock Accumulator is either the false lock indicator bit

or the magnitude of the frequency error detector output. Like the Lock Accumulator, the threshold is set

Accumulator

Pre-Load (Acquisition) by an accumulator pre-load that is backed off from accumulator full scale. The False Lock Accumulator

can accumulate sums up to 18 bits, and the bit weightings of the false lock indicator bit and the frequency

error input relative to accumulator full scale are shown below.

BIT WEIGHTING OF ACCUMULATOR PRE-LOAD

10

9

8

7

0

-1 -2 -3 -4 -5 -6 -7

2

2 2 2 ......2 . 2

2

BIT WEIGHTING OF

FALSE LOCK INDICATOR BIT

BIT WEIGHTING OF

FREQUENCY ERROR MAGNITUDE

BINARY POINT

11

The accumulator roll over is at the 2 bit position.

15-0

False Lock

Accumulator

Pre-Load (Track)

See above. The Lock Detector State Machine only uses the accumulator during the verify state during

which the Track parameters are used.

3-291

HSP50210

TABLE 37. ACQUISITION/TRACKING CONTROL REGISTER

DESTINATION ADDRESS = 23

BIT

POSITION

FUNCTION

Not Used

DESCRIPTION

No programming required.

31-16

15

Reserved

Set to 0 for proper operation.

14

False Lock Detect

Enable

This bit enables the false lock detection during the verify state of state machine controlled acquisition.

The overflow of the False Lock Accumulator before the Integration Counter forces the false lock state. If

disabled, the overflow of the False Lock Accumulator has no effect on state machine operation.

0 = Disable False Lock.

1 = Enable False Lock.

Note: The false Lock Detector is designed for false lock detection on square wave data. For shaped

waveforms false lock detection should be disabled or frequency error should be used.

13

Frequency Sweep

Mode

This bit selects whether stepped or continuous frequency sweep mode is used (see Lock Detector Sec-

tion).

0 = Stepped Frequency Sweep (provided for microprocessor controlled acquisition mode).

1 = Continuous Frequency Sweep.

12-9

8-5

Verify State Length

False Lock Sweep

These bits set the number of integration cycles over which carrier lock must be maintained before the

Lock State is declared. The verify state is used to make sure that lock detection was not the result of noise

or false lock. The 4-bit value programmed here sets the verify state from 0 to 15 Integration Periods.

These bits set the duration of forced frequency sweep before returning to the acquisition state. When

continuous frequency sweep mode is selected, the programmed number represents the number of Lock

Accumulator integration cycles to sweep before returning to the acquisition state. In stepped frequency

sweep mode, the number represents the number of loop filter compute cycles over which to enable the

sweep input to the lag accumulator.

4

Lock Detector Control This bit selects whether the acquisition/tracking process is controlled externally by a microprocessor or

internally by the state machine. If microprocessor control is chosen, the lock detect accumulator

integrates for the programmed period of time and ignores accumulator roll over, if any. The Lock Detector

Accumulator halts after each Integration Period and waits to be restarted by the microprocessor. In

addition, the microprocessor must select the acquisition/tracking parameters, as well as enable the

Frequency Sweep Block.

0 = Microprocessor Control.

1 = Internal State Machine Control.

3

2

Microprocessor

Acquisition/Track

Select

0 = Track Parameters Chosen.

1 = Acquisition Parameters Chosen.

Microprocessor Lock

This bit controls the state of the lock bit (STATUS6) in the status output STATUS6-0 (see Output Select

Section). In addition, this bit sets the internal state machine to the locked state when Lock Detector

Control is switched from microprocessor control to state machine control. See Table 46 for the STATUS

bit information.

1

0

Reserved

Set to zero for proper operation.

Microprocessor

Frequency Sweep

Enable

This bit is used to enable the output of the Frequency Sweep Block to the lag path of the Symbol Tracking

Loop Filter. This bit is only used under microprocessor control of the Lock Detector.

3-292

HSP50210

TABLE 38. HALT LOCK DETECTOR FOR READING CONTROL REGISTER

DESTINATION ADDRESS = 24

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

Stop Lock Detector for Writing this location halts the Lock Detector State Machine at the end of the current Lock Detector

Reading

Accumulator integration cycle. This function is provided so that the Lock Detector integrators can be

stopped for reading via the microprocessor interface (only useful when the Lock Detector is under

internal state machine control). Bit 7 of the internal status register can be monitored via the

Microprocessor Interface to determine when the Lock Detector has stopped and is ready for reading.

See Table 13 for information on the internal status bits. The Lock Detector will remain stopped until

restarted (see Restart Lock Detector Control Register: Table 39).

TABLE 39. RESTART LOCK DETECTOR CONTROL REGISTER

DESTINATION ADDRESS = 25

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

Restart Lock Detector Writing this location restarts the Lock Detector State Machine following a read of the Lock Detector. Note:

Stopping the Lock Detector for reading is not required in Microprocessor Control Mode since the

Lock Detector Accumulators stop at the end of each integration cycle. See also Table 44.

TABLE 40. SOFT DECISION SLICER CONFIGURATION CONTROL REGISTER

DESTINATION ADDRESS = 26

BIT

POSITION

FUNCTION

Not Used

DESCRIPTION

31-8

7

No programming required.

Slicer Output Format

0 = Soft decision outputs are in sign/magnitude format.

1 = Soft decision outputs are in two’s complement format.

6-0

Soft Decision

Threshold

The input to the slicer is compared against thresholds which are 1x, 2x and 3x the value programmed

here. The slicer output depends on the relationship of the I or Q magnitude to the 3 soft thresholds as

given in Table 7. The threshold is programmed as a fractional unsigned value with the following bit

weightings:

-1 -2 -3 -4 -5 -6 -7

0. 2

2

2 .

Note: Since the signal magnitude on either the I or Q path ranges between 0.0 and ~1.0, the

threshold value should not exceed 1.0/3 = 0.33. Bit position 6 is the MSB.

TABLE 41. SERIAL OUTPUT CONFIGURATION CONTROL REGISTER

DESTINATION ADDRESS = 27

BIT

POSITION

FUNCTION

Not Used

DESCRIPTION

No programming required.

31-16

15-13

12

Reserved

Set to zero for proper operation.

Serial Data Sync

Polarity

(SOF output)

0 = SOFSYNC pulses “High” one serial clock before data word on SOF.

1 = SOFSYNC pulses “Low” one serial clock before data word on SOF.

Set to 0 for use with the HSP50110.

11

Serial Data Sync

Polarity

(COF output)

0 = COFSYNC pulses “High” one serial clock before data word on COF.

1 = COFSYNC pulses “Low” one serial clock before data word on COF.

Set to 0 for use with the HSP50110.

3-293

HSP50210

TABLE 41. SERIAL OUTPUT CONFIGURATION CONTROL REGISTER (Continued)

DESTINATION ADDRESS = 27

BIT

POSITION

FUNCTION

DESCRIPTION

0 = Rising edge of serial clock at center of data bit.

10

Serial Clock Phase

Relative to Data

1 = Falling edge of serial clock at center of data bit. Set to 0 for use with the HSP50110.

9-8

Serial Clock Divider

These bits set the clock rate of SLOCLK.

00 -> SLOCLK = CLK/2.

01 -> SLOCLK = CLK/4.

10 -> SLOCLK = CLK/8.

11 -> SLOCLK = CLK/16.

7

Serial Clock Select for 0 = CLK is used as the serial clock.

COF Output

1 = SLOCLK is used as the serial clock.

Note: If the HSP50210 is used together with the HSP50110, CLK must be selected as the serial

clock for the SOF and COF outputs, and the same CLK must be used by both chips.

6-4

Serial Word Length for 000 = 8 Bits

COF Output

001 = 12 Bits

010 = 16 Bits

011 = 20 Bits

100 = 24 Bits

101 = 28 Bits

110 = 32 Bits

111 = 40 Bits

3

Serial Clock Select for 0 = CLK is used as the serial clock.

SOF Output

1 = SLOCLK is used as the serial clock.

Note: If the HSP50210 is used together with the HSP50110, CLK must be selected as the serial

clock for the SOF and COF outputs, and the same CLK must be used by both chips.

2-0

Serial Word Length for 000 = 8 Bits

SOF Output

001 = 12 Bits

010 = 16 Bits

011 = 20 Bits

100 = 24 Bits

101 = 28 Bits

110 = 32 Bits

111 = 40 Bits

3-294

HSP50210

:

TABLE 42. OUTPUT SELECTOR CONFIGURATION CONTROL REGISTER

DESTINATION ADDRESS = 28

BIT POSITION

FUNCTION

DESCRIPTION

31-8

7-4

Not Used

No programming required.

Reserved

Set to zero for proper operation.

3-0

Output Select

These bits select which input signals are routed to the 20 output pins AOUT9-0 and BOUT9-0. The signal

selections are listed below in Tables 42A and 42B.

Definition of Signal Bus Names:

Data Signal Busses:

ISOFT(2:0) This bus is the I channel soft decision slicer output data, expressed in the data format set

by CW26 bit 7, with one sign bit (ISOFT2) and two soft decision bits.

QSOFT(2:0) This bus is the Q channel soft decision slicer output data, expressed in the data format set

by CW26 bit 7, with one sign bit (QSOFT2) and two soft decision bits.

IEND(7:1)

This bus is the 7 MSB’s of I end symbol sample into the soft decision slicer, in 2’s comple-

ment format. (MSB = Iend7).

QEND(7:1) This bus is the 7 MSB’s of Q end symbol sample into the soft decision slicer, in 2’s comple-

ment format. (MSB = Qend7).

Status Signal Parameter Busses:

AGC(7:1) . . . . . This bus is the 7 MSB’s of the AGC Accumulator Register. (MSB = AGC7).

MAG (7:0) . . . . This bus is the 8-bit magnitude output of the Cartesian to Polar converter, in unsigned

binary format. (MSB = MAG7).

PHASE (7:0) . . This bus is the 8-bit phase output of the Cartesian to Polar converter, in unsigned binary

format. (MSB = PHASE7).

FE(7:1) . . . . . . This bus is the seven MSB’s of the Frequency Error Detector Output Register, in 2’s

complement format. (MSB = FE7).

GE (7:1) . . . . . This bus is the seven MSB’s of the Gain Error (AGC) Accumulator Register, in 2’s com-

plement format. (MSB = GE7).

TE (7:1) . . . . . This bus is the seven MSB’s of the Bit Phase Error Detector Output Register, in 2’s com-

plement format. (MSB = TE7).

CARPE (7:1) . . This bus is the seven MSB’s of the Carrier Phase Error Detector Output Register, in 2’s

complement format. (MSB = PE7).

LKACC(6:0) . . .This bus is the seven LSB’s of the Phase Error Accumulator Register in the Lock Detector,

in unsigned offset binary format. (MSB = LKACC6) If accumulation bits 14-17 = 1, then

bits 7-13 are output as LKACC(6.0). These outputs are zero otherwise.

LKCNT(6:0) . . This bus is the seven LSB’s of the Integration Counter in the Lock Detector, in one’s

complement format. (MSB = LKCNT6) If bits 7-9 of the accumulator are zero, then bits

0-6 are output as LKCNT(6-0). These outputs are zero otherwise.

NCOCOS(9:0) . This bus is the 10-bit two’s complement output of the DCL NCO, in 2’s complement for-

mat. (MSB = NCOCOS7).

Applications for the Various Output Signals:

ISOFT(2:0) and QSOFT(2:0)

These signals provide a simple interface to a FEC decoder. As the most likely to be used output bus, these

signals are included in all but one of the programmable multiplexer output configurations.

IEND(7:1) and QEND(7:1)

These signals are useful when input to a D/A converter and displayed on an oscilloscope in the X-Y plot.

This will yield the constellation signal display with which analog modem designers are familiar.

STATUS(6:0)

These signals can be used in fault detection for use in BIT/BITE applications and are useful during sys-

tem debug.

AGC(7:1)

This signal is useful in monitoring the AGC operation, signal detection and antenna tracking applications.

Other single bit signals are provided for direct use in external AGC.

MAG(7:0) and PHASE(7:0)

These signals are useful in signal detection applications, where presence of a signal is represented by a

particular signal magnitude or phase.

3-295

HSP50210

TABLE 42. OUTPUT SELECTOR CONFIGURATION CONTROL REGISTER (Continued)

DESTINATION ADDRESS = 28

BIT POSITION

FUNCTION

DESCRIPTION

FREQERR(7:1), GAINERR(7:1), BITPHERR(7:1), and CARPHERR(7:1)

These signals are useful in applications that need these signals output at the symbol rate and available

for hardwiring, rather than at the processor access rate. Configurations that use the DCL as a stand alone

demodulator and matched filter are examples of such applications.

LKACC(6:0) and LKCNT(6:0)

These signals are provided for applications which require a lock detection interface that is not processor

dependent. These signals are also useful in fault detection in BIT/BITE applications.

NCOCOS(9:0)

This signal is provided for use when the DCL is configured as a stand alone Loop Filter and NCO. This

signal can be useful in fault detection in BIT/BITE applications.

TABLE 42A. AOUT BIT DEFINITIONS

OUTPUT

SELECT

0000

0001

0010

0011

0100

0101

0110

0111

1000

AOUT 9

ISOFT2

RSRVD7

AOUT 8

ISOFT1

QSOFT2

ISOFT1

RSRVD6

AOUT 7

ISOFT0

MAG7

AOUT 6

QSOFT2

MAG6

AOUT 5

QSOFT1

MAG5

AOUT 4

QSOFT0

MAG4

AOUT 3

STATUS6 STATUS5 STATUS4 STATUS3

MAG3 MAG2 MAG1 MAG0

AOUT 2

AOUT 1

AOUT 0

ISOFT0

RSRVD5

QSOFT2

RSRVD4

QSOFT1

RSRVD3

QSOFT0

RSRVD2

STATUS6 STATUS5 STATUS4 STATUS3

LKACC6

Iend7

LKACC5

Iend6

LKACC4

Iend5

LKACC3

Iend4

RSRVD1

RSRVD0

STATUS5 STATUS6

TABLE 42B. BOUT BIT DEFINITION

OUTPUT

SELECT

BOUT 9

BOUT 8

BOUT 7

BOUT 6

BOUT 5

AGC6

BOUT 4

AGC5

BOUT 3

BOUT 2

BOUT 1

AGC2

BOUT 0

AGC1

0000

0001

0010

0011

0100

0101

0110

0111

1000

STATUS2 STATUS1 STATUS0 AGC7

AGC4

ACG3

STATUS6 STATUS0 PHASE7

PHASE6

PHASE5

FE6

PHASE4

FE5

PHASE3

FE4

PHASE2

FE3

PHASE1

FE2

PHASE0

FE1

STATUS2 STATUS1 STATUS0 FE7

STATUS2 STATUS1 STATUS0 GE7

STATUS2 STATUS1 STATUS0 TE7

STATUS2 STATUS1 STATUS0 CARPE7

GE6

GE5

GE4

GE3

GE2

GE1

TE6

TE5

TE4

TE3

TE2

TE1

CARPE6

LKCNT5

Qend6

CARPE5

LKCNT4

Qend5

CARPE4

LKCNT3

Qend4

CARPE3

LKCNT2

Qend3

CARPE2

LKCNT1

Qend2

CARPE1

LKCNT0

Qend1

LKACC2

Iend3

LKACC1

Iend2

LKACC0

Iend1

LKCNT6

Qend7

NCOCOS9 NCOCOS8 NCOCOS7 NCOCOS6 NCOCOS5 NCOCOS4 NCOCOS3 NCOCOS2 NCOCOS1 NCOCOS0

TABLE 43. UPDATE READ REGISTER CONFIGURATION CONTROL REGISTER

DESTINATION ADDRESS = 29

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

Load Output Holding

Register for

Microprocessor Read

Loading the Address Register with this destination address samples the contents of the Carrier Loop

Filter Lag Accumulator, Symbol Tracking Loop Filter Lag Accumulator, and the AGC Accumulator. The

sampled accumulator values are loaded into the output holding registers for reading via the

Microprocessor Interface. Allow 6 CLKs until the output holding register is stable for reading.

3-296

HSP50210

TABLE 44. INITIALIZE LOCK DETECTOR (µP CONTROL MODE) CONTROL REGISTER

DESTINATION ADDRESS = 30

BIT

POSITION

FUNCTION

Initialization of Lock

DESCRIPTION

N/A

Loading the address register with this destination address pre-loads all of the Lock Detector

Detector Accumulators Accumulators and resets the Integration Counters to restart the integration process. Note: A write to this

address only initializes the Lock Detector when it is in microprocessor control mode (see

Acquisition/Tracking Control Register; Table 37).

TABLE 45. TEST CONFIGURATION CONTROL REGISTER

DESTINATION ADDRESS = 31

BIT

POSITION

FUNCTION

Not Used

DESCRIPTION

31-16

15-6

5

No programming required.

Set to 0 for proper operation.

Reserved

Initialize NCO

This bit is used to zero the feed back in the NCO’s phase accumulator. This is useful in setting the output

of the NCO to a known value.

0 = Enable normal NCO operation.

1 = Zero phase accumulator feedback for test.

4

3

Zero Symbol Tracking This bit is used to zero the lag accumulator in the Symbol Tracking Loop Filter.

Loop Filter

Accumulator

0 = Enable normal loop filter operation.

1 = Zero Lag Accumulator.

Zero Carrier Loop Filter This bit is used to zero the lag accumulator in the Carrier Loop Filter.

Accumulator

0 = Enable normal loop filter operation.

1 = Zero Lag Accumulator.

2-0

Reserved

Set to 0 for proper operation.

TABLE 46. STATUS 6-0 SIGNAL DESCRIPTIONS

DESCRIPTION

BIT

POSITION

FUNCTION

6

Carrier Lock

0 = Lock Detector is not in locked state (Carrier Tracking Loop is not locked).

1 = Lock Detector has achieved the locked state (Carrier lock has been achieved).

5

Acquisition/Track

indicator

0 = Tracking Parameters currently being used by Tracking Loops.

1 = Acquisition Parameters currently being used by Tracking Loops.

4

3

Reserved

N/A.

Frequency Sweep

Direction

This bit indicates the direction of the frequency sweep selected by the Frequency Sweep input to the lag

path of the Carrier Tracking Loop Filter (Defined for upper sideband signals).

0 = Up (Sweep increasing in frequency).

1 = Down (Sweep decreasing in frequency).

2

1

0

High Power

This bit is one clock cycle long and indicates when the AGC is at its lower limit (see AGC Section and

Table 15).

0 = AGC above lower limit.

1 = AGC at lower limit.

Low Power

This bit is one clock cycle long and indicates when the AGC is at its upper limit (see AGC Section and

Table 15).

0 = AGC is at or below its upper limit.

1 = AGC is above its upper limit.

Data Ready Strobe

This bit pulses “High” for one CLK synchronous with a new signal output on OUTB6-0 (see Output

Selector Control Register: Table 45). For example if the lower 4 bits of the Output Selector Register are

set to 0010 (BINARY), This bit will pulse active on the same CLK that new FE7-1 data is output.

3-297

HSP50210

Appendix A

Noise Bandwidth Summary

For a given decimation rate, the double-sided noise

equivalent bandwidth is shown using various combinations

of the CIC ﬁlter and the compensation ﬁlters in the

and without the root raised cosine ﬁlter in the HSP50210.

The noise bandwidth is measured relative to the output

sample rate.

HSP50110. Each combination of ﬁlters is also shown with

TABLE A

INT/DUMP

INTE-

GRATE/

DUMP

INTEGRATE/

DUMP

W/COMP

3RD ORDER

CIC W/COMP

AND RRC

INT/DUMP

AND RRC

W/COMP

AND RRC

3RD

3RD ORDER 3RD ORDER CIC

DEC

2

ORDER CIC CIC W/COMP

AND RRC

0.420829

0.402135

0.401628

0.401510

0.401465

0.401443

0.401431

0.401424

0.401415

0.401462

0.401598

0.400708

0.400933

0.403557

-

1.0000

1.3775

0.492771

0.5348

0.6250

0.5525

0.5508

0.5504

0.5502

0.5501

0.5500

1.3937

1.0785

1.0714

1.0698

1.0691

1.0688

1.0687

1.0686

1.0685

1.0684

1.0683

0.531055

0.501525

0.500731

0.500547

0.500477

0.500443

0.500424

0.500410

0.500404

0.500408

0.500215

0.501272

0.499348

0.497418

0.501420

-

10

18

26

34

42

50

58

66

74

82

90

98

106

114

122-4096

NOTE:

6. Noise Bandwidth of RRC Filter is 0.492676.

3-298

HSP50210

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

Input, Output Voltage . . . . . . . . . . . . . . . . .GND -0.5V to V +0.5V

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 3

Thermal Resistance (Typical, Note 7)

θ

C/W

JA

24

CC

PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

o

Maximum Storage Temperature. . . . . . . . . . . . . . . . -65 C to 150 C

Maximum Junction Temperature PLCC . . . . . . . . . . . . . . . . . .150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

o

Operating Conditions

(PLCC - Lead Tips Only)

Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.75V to +5.25V

Temperature Range

o

Die Characteristics

Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

o

Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45,000

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

7. θ is measured with the component mounted on an evaluation PC board in free air.

JA

o

DC Electrical Speciﬁcations

PARAMETER

V

= 5.0V ±5%, T = 0 C to 70 C (Commercial), T = -40 C to 85 C (Industrial)

CC

A

SYMBOL

TEST CONDITIONS

MIN

MAX

UNITS

Power Supply Current

I

V

= Max, CLK = 52.6MHz

CC

-

225

mA

CCOP

(Notes 8, 9)

Standby Power Supply Current

Input Leakage Current

Output Leakage Current

Clock Input High

I

V

= Max, Outputs Not Loaded

-

-10

3.0

-

500

10

-

µA

V

CCSB

CC

I

= Max, Input = 0V or V

= Max, CLK

I

CC

I

O

CC

V

IHC

Clock Input Low

V

= Min, CLK

0.8

-

V

ILC

Logical One Input Voltage

Logical Zero Input Voltage

Logical One Output Voltage

Logical Zero Output Voltage

Input Capacitance

V

= Max

2.0

-

V

IH

V

= Min

0.8

-

V

IL

V

I

f

= -400µA, V

= Min

2.6

-

V

OH

OL

CC

V

= 2mA, V

CC

= Min

0.4

10

V

OL

C

= SCLK = 1MHz

-

pF

IN

CLK

All measurements referenced to GND.

Output Capacitance

C

-

o

OUT

T

= 25 C (Note 10)

A

NOTES:

8. Power supply current is proportional to frequency. Typical rating is 4mA/MHz.

9. Output load per test circuit and C = 40pF.

L

10. Not tested, but characterized at initial design and at major process/design changes.

o

AC Electrical Speciﬁcations

V

= 5.0V ±5%, T = 0 C to 70 C (Commercial), T = -40 C to 85 C (Industrial),

CC

(Note 11)

A

52MHz

PARAMETER

CLK Period

SYMBOL

MIN

19

7

MAX

COMMENTS

T

-

ns

CP

CLK High

CH

CLK Low

T

7

CL

SH

SL

SERCLK High

T

t

7

SERCLK Low

7

Setup Time IIN9-0,QIN9-0,SYNC,FZ_CT,FZ_ST to CLK

t

8

DS

DH

Hold Time IIN9-0,QIN9-0,SYNC,FZ_CT,FZ_ST FROM CLK

Setup Time ISER, QSER, SSYNC to SERCLK

1

t

8

DSS

3-299

HSP50210

o

AC Electrical Speciﬁcations

V

= 5.0V ±5%, T = 0 C to 70 C (Commercial), T = -40 C to 85 C (Industrial),

CC

A

(Note 11) (Continued)

52MHz

PARAMETER

SYMBOL

MIN

0

MAX

COMMENTS

Hold Time ISER, QSER, SSYNC FROM SERCLK

Setup Time A0-2, C0-7 to Rising Edge of WR

Hold Time A0-2, C0-7 from Rising Edge of WR

WR to CLK

t

-

ns

DSH

t

15

0

ns

WS

WH

WC

t

-

t

15

10

-

ns, (Note 13)

ns

SERCLK to CLK

t

-

SC

DO

CLK to AOUT9-0,BOUT9-0, COF, COFSYNC, SOF,

SOFSYNC,SMBLCLK, HI/LO,SLOCLK,LKINT,THRES

t

8

Read Address Low to Data Valid

CLK to Status Out on C0-7

WR High

t

-

26

15

-

ns

ADO

CDO

ns

t

16

-

ns

WRH

WRL

WR Low

t

-

ns

RD Low

t

-

RL

RD LOW to Data Valid

RD HIGH to Output Disable

Output Enable

t

15

10

8

ns

RDO

ROD

-

ns, (Note 12)

ns

t

-

OE

OD

RF

Output Disable Time

Output Rise, Fall Time

NOTES:

-

8

ns, (Note 12)

-

5

11. AC tests performed with C = 40 pF, I = 2mA, and I

OL

= -400mA. Input reference level for CLK is 2.0V, all other inputs 1.5V.

OH

L

Test V = 3.0V, V

= 4.0V, V = 0V.

IH

IHC

IL

12. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design

changes.

13. Set up time required to ensure action initiated by WR or SERCLK will be seen by a particular CLK.

AC Test Load Circuit

S1

DUT

^C†

L

±

IOH

1.5V

IOL

SWITCH S1 OPEN FOR I

AND I

CCOP

CCSB

EQUIVALENT CIRCUIT

† Test head capacitance.

3-300

HSP50210

Waveforms

t

WRH

WRL

WR

t

RF

t

RF

t

WS

WH

2.0V

0.8V

C0-7, A0-2

FIGURE 26. TIMING RELATIVE TO WR

FIGURE 27. OUTPUT RISE AND FALL TIMES

OEA,

OEB

t

CP

1.5V

t

CH

CL

t

OE

OD

CLK

OUTA9-0,

OUTB9-0

1.7V

1.3V

t

DS

DH

IIN9-0, QIN9-0,

SYNC,

FIGURE 29. OUTPUT ENABLE/DISABLE

FZ_CT, FZ_ST

AOUT9-0, BOUT9-0,

COF, COFSYNC,

t

SOF, SOFSYNC,

RL

t

DO

HI/LO, SMBLCLK,

RD

SLOCLK, LKINT, THRES

t

; t

SC WC

A2-0

SERCLK, WR

C0-7

C7-0

t

CDO

ADO

RDO

ROD

FIGURE 28. TIMING RELATIVE TO CLK

FIGURE 30. TIMING RELATIVE TO READ

t

SL

SH

SERCLK

t

DSH

DSS

ISER, QSER, SSYNC

FIGURE 31. SERCLK TIMING

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

3-301


型号：	HSP50210JC-52
厂家：	Intersil
描述：	Digital Costas Loop 数字科斯塔斯环电信集成电路
文件：	总49页 (文件大小：328K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HSP50210JC-52 [INTERSIL]

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