HSP50214_技术文档

HSP50214

Programmable Downconverter

February 2000

[ /Title

(HSP5

0214)

/Sub-

ject

(Pro-

gram-

mable

Down-

con-

verter)

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/Key-

words

(Inter-

sil

Semi-

con-

ductor,

Down-

con-

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Down

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Pro-

Features

Description

• Up to 52 MSPS Front-End Processing Rates (CLKIN)

and 35 MSPS Back-End Processing Rates (PROCCLK) digitized IF data into ﬁltered baseband data which can be

Clocks May Be Asynchronous

The HSP50214 Programmable Downconverter converts

processed by a standard DSP microprocessor. The

Programmable Downconverter (PDC) performs down

conversion, decimation, narrowband low pass ﬁltering, gain

scaling, re-sampling, and Cartesian to Polar coordinate

conversion.

• Processing Capable of >100dB SFDR8-

• Up to 255-Tap Programmable FIR

• Overall Decimation Factor Ranging from 4 to 16384

• Output Samples Rates to 8.2 MSP8-S with Output

Bandwidths to 625kHz Lowpass

The 14-bit sampled IF input is down converted to baseband

by digital mixers and a quadrature NCO, as shown in the

Block Diagram. A decimating (4 to 32) ﬁfth order Cascaded

Integrator-Comb (CIC) ﬁlter can be applied to the data

before it is processed by up to 5 decimate-by-2 halfband ﬁl-

ters. The halfband ﬁlters are followed by a 255-tap program-

mable FIR ﬁlter. The output data from the programmable FIR

ﬁlter is scaled by a digital AGC before being re-sampled in a

polyphase FIR ﬁlter. The output section can provide seven

types of data: Cartesian (I, Q), polar (R, θ), ﬁltered frequency

(dθ/dt), timing error (TE), and AGC level in either parallel or

serial format.

• 32-Bit Programmable NCO for Channel Selection and

Carrier Tracking

• Digital Re-Sampling Filter for Symbol Tracking Loops

and Incommensurate Sample-to-Output Clock Ratios

• Digital AGC with Programmable Limits and Sle8- Rate

to Optimize Output Signal Resolution; Fixed or Auto

Gain Adjust

• Serial, Parallel, and FIFO 16-Bit Output Modes

• Cartesian to Polar Converter and Frequency Discrimi-

nator for AFC Loops and Demodulation of AM, FM,

FSK, and DPSK

Ordering Information

• Input Level Detector for External I.F. AGC Support

PART

NUMBER

TEMP.

RANGE ( C)

o

PACKAGE

120 Ld MQFP

PKG. NO.

Q120.28x28

Applications

HSP50214VC

HSP50214VI

0 to 70

• Single Channel Digital Software Radio Receivers

• Base Station Rx’s: AMPS, NA TDMA, GSM, and CDMA

-40 to 85

• Compatible with HSP50210 Digital Costas Loop for

PSK Reception

• Evaluation Platform Available

gram-

mable

Down-

con-

verter,

DSP,

AMPS,

TDMA

,

North

Ameri-

can

Block Diagram

MICROPROCESSOR

READ/WRITE

CONTROL

C(7:0)

AGC LOOP FILTER

AGC

LEVEL DETECT

I SYMBOL

TH

5

ORDER

CIC

FILTER

POLYPHASE

FIR AND

HALFBAND

FILTERS

SEROUTA

SEROUTB

AOUT(15:0)

CARTESIAN

MAG.

TO

POLAR

IN(13:0)

PHASE

COORDINATE

CONVERTER

TH

5

ORDER

CIC

FILTER

BOUT(15:0)

POLYPHASE

FIR AND

GAIN

ADJ

(2:0)

HALFBAND

FILTERS

Q SYMBOL

CARRIER

NCO

COF

FREQ

SOF

CLKIN

DISCRIMINATOR

RE-SAMPLING

NCO

PROCCLK

REFCLK

TIMING ERROR

∆

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 4266.3

1

HSP50214

Pinout

120 LEAD MQFP

TOP VIEW

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

DATARDY

OEBH

BOUT15

BOUT14

1

2

3

4

5

6

7

8

IN10

IN9

IN8

GND

IN7

NC

IN6

IN5

IN4

IN3

IN2

GND

IN1

IN0

V

CC

NC

BOUT13

BOUT12

BOUT11

BOUT10

BOUT9

BOUT8

GND

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

GND

PROCCLK

V

CC

V

CLKIN

GND

NC

ENI

CC

MSYNCI

MSYNCO

GND

BOUT7

BOUT6

BOUT5

GND

73

72

71

70

69

68

67

66

65

64

63

62

61

GAINADJ2

GAINADJ1

GAINADJ0

COF

COFSYNC

GND

BOUT4

NC

BOUT3

BOUT2

BOUT1

BOUT0

OEBL

SOF

SOFSYNC

V

CC

SYNCIN1

SYNCIN2

2

HSP50214

Pin Descriptions

NAME

TYPE

DESCRIPTION

V

-

I

Positive Power Supply Voltage.

Ground.

CC

GND

CLKIN

Input Clock. This clock should be a multiple of the input sample rate. All input section processing oc-

curs on the rising edge of CLKIN.

IN(13:0)

ENI

I

Input Data. The format of the input data may be set to offset binary or 2’s complement. IN13 is the

MSB (see control word 0).

Input Enable. Active Low. This pin enables the input to the part in one of two modes, gated or inter-

polated (see control word 0). In gated mode, one sample is taken per CLKIN when ENI is asserted.

GAINADJ(2:0)

GAINADJ Input. Adds an offset to the gain via the shifter following the mixer. GAINADJ value is added

to the shift code from the microprocessor (µP) interface. The shift code is saturated to a maximum

code of F. The gain is offset by (6dB)(GAINADJ). (000 = 0dB gain adjust; 111 = 42dB gain adjust)

GAINADJ2 is the MSB. See “Using the Input Gain Adjust Control Signals” section.

PROCCLK

I

Processing Clock. PROCCLK is the clock for all processing functions following the CIC section. Pro-

cessing is performed on PROCCLK’s rising edge. All output timing is derived from this clock.

NOTE: This clock may be asynchronous to CLKIN.

AGCGNSEL

COF

I

AGC Gain Select. This pin selects between two AGC loop gains. This input is setup and held relative

to PROCCLK. Gain setting 1 is selected when AGCGNSEL = 1.

Carrier Offset Frequency Input. This serial input pin is used to load the carrier offset frequency into the

Carrier NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32 bits. The setup and hold

times are relative to CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1].

COFSYNC

SOF

I

Carrier Offset Frequency Sync. This signal is asserted one CLK before the most signiﬁcant bit (MSB)

of the offset frequency word (see Serial Interface Section). The setup and hold times are relative to

CLKIN. This input is compatible with the output of the HSP50210 Costas loop [1].

Resampler Offset Frequency Input. This serial input pin is used to load the offset frequency into the

Resampler NCO (see Serial Interface Section). The offset may be 8, 16, 24, or 32 bits. The setup and

hold times are relative to PROCCLK. This input is compatible with the output of the HSP50210 Costas

loop [1].

SOFSYNC

I

Resampler Offset Frequency Sync. This signal is asserted one CLK before the MSB of the offset fre-

quency word (see Serial Interface Section). The setup and hold times are relative to PROCCLK. This

input is compatible with the output of the HSP50210 Costas loop [1].

AOUT(15:0)

O

Parallel Output Bus A. Two parallel output sources are available on the HSP50214. The ﬁrst is called

the Direct Output Port, where the source is selected through control word 20 (see the Microprocessor

Write section) and comes directly from the Output MUX section (see Output Control Section). The

most signiﬁcant byte of AOUT always outputs the most signiﬁcant byte of the Parallel Direct Output

Port whose format is selected via µP interface. AOUT15 is the MSB. In this mode, the AOUT(15:0)

bus is updated as soon as data is available. DATARDY is asserted to indicate new data.

The second source for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output

Port acts like a FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude,

phase, and frequency information; a data type is selected using SEL(2:0). Up to 7 data sets are stored

in the Buffer RAM Output Port. The LSBytes of the AOUT and BOUT busses form the 16 bits for the

buffered output mode and can be used for buffered mode while the MSBytes are outputting data in

the direct output mode.

BOUT(15:0)

O

Parallel Output Bus B. Two parallel output sources are available on the HSP50214. The ﬁrst is called

the Direct Output Port, where the source is selected through control word 20 (see the Microprocessor

Write section) and comes directly from the Output MUX section (see Output Control Section). The

most signiﬁcant byte of BOUT always outputs the most signiﬁcant byte of the Parallel Direct Output

Port whose format is selected via µP interface. BOUT15 is the MSB. In this mode, the BOUT(15:0)

bus is updated as soon as data is available. DATARDY is asserted to indicate new data.

The second source for parallel data is called the Buffer RAM Output Port. The Buffer RAM Output

Port acts like a FIFO for blocks of information called data sets. Within a data set is I, Q, magnitude,

phase, and frequency information; a particular information is selected using SEL(2:0). Up to 7 data

sets is stored in the Buffer RAM Output Port. The least signiﬁcant byte of BOUT can be used to either

output the least signiﬁcant byte of the B Parallel Direct Output Port or the least signiﬁcant byte of the

Buffer RAM Output Port. See Output Section.

3

HSP50214

Pin Descriptions (Continued)

NAME

TYPE

DESCRIPTION

DATARDY

O

Output Strobe Signal. Active low. Indicates when new data from the Direct Output Port section is avail-

able. DATARDY is asserted for one PROCCLK cycle during the ﬁrst clock cycle that data is available

on the parallel out busses. See Output Section.

OEAH

OEAL

I

Output enable for the MSByte of the AOUT bus. Active Low.

Output enable for the LSByte of the AOUT bus. Active Low.

Output enable for the MSByte of the BOUT bus. Active Low.

Output enable for the LSByte of the BOUT bus. Active Low.

OEBH

OEBL

SEL(2:0)

Select Address is used to choose which information in a data set from the Buffer RAM Output Port is

sent to the least signiﬁcant bytes of AOUT and BOUT. SEL2 is the MSB.

INTRRP

SEROUTA

SEROUTB

O

Interrupt Output. Active low. This output is asserted for 8 PROCCLK cycles when the Buffer RAM Out-

put Port is ready for reading.

Serial Output Bus A Data. I, Q, magnitude, phase, frequency, timing error and AGC information can

be sequenced in programmable order. See Output Section and Microprocessor Write Section.

Serial Output Bus B Data. Contents may be related to SEROUTA. I, Q, magnitude, phase, frequency,

timing error and AGC information can be sequenced in programmable order. See Output Section and

Microprocessor Write Section.

SERCLK

SERSYNC

SEROE

O

I

Output Clock for Serial Data Out. Derived from PROCCLK as given by control word 20 in the Micro-

processor Write Section.

Serial Output Sync Signal. Serves as serial data strobes. See Output Section and Microprocessor

Write Section.

Serial Output Enable. When high, the SEROUTA, SEROUTB, SERCLK, and SERSYNC signals are

set to a high impedance.

C(7:0)

A(2:0)

WR

I/O

Processor Interface Data Bus. See Microprocessor Write Section. C7 is the MSB.

Processor Interface Address Bus. See Microprocessor Write Section. A2 is the MSB.

I

Processor Interface Write Strobe. C(7:0) is written to control words selected by A(2:0) in the Program-

mable Down Converter on the rising edge of this signal. See Microprocessor Write Section.

RD

I

Processor Interface Read Strobe. C(7:0) is read from output or status locations selected by A(2:0)

in the Programmable Down Converter on the falling edge of this signal. See Microprocessor Read

Section.

REFCLK

I

Reference Clock. Used as an input clock for the timing error detector. The timing error is computed

relative to REFCLK. REFCLK frequency must be less than or equal to PROCCLK/2.

MSYNCO

O

Multiple Chip Sync Output. Provided for synchronizing multiple parts when CLKIN and PROCCLK are

asynchronous. MSYNCO is the synchronization signal between the input section operating under

CLKIN and the back end processing operating under PROCCLK. This output sync signal from one

part is connected to the MSYNCI signal of all the HSP50214s.

MSYNCI

I

Multiple Chip Sync Input. The MSYNCI pin of all the parts should be tied to the MSYNCO of one part.

NOTE: MSYNCI must be connected to an MSYNCO signal for operation.

SYNCIN1

CIC Decimation/Carrier NCO Update Sync. Can be used to synchronize the CIC section, carrier NCO

update, or both. See the Multiple Chip Synchronization Section and Control Word 0 in the Micropro-

cessor Write Section. Active High.

SYNCIN2

I

FIR/Timing NCO Update/AGC Gain Update Sync. Can be used to synchronize the FIR, Timing NCO

update, AGC gain update, or any combination of the above. See the Multiple Chip Synchronization

Section and Control Words 7, 8, and 10 in the Microprocessor Write Section. Active High.

SYNCOUT

O

Strobe Output. This synchronization signal is generated by the µP interface for synchronizing multiple

parts. Can be generated by PROCLK or CLKIN (see Control word 0 and Control word 24 in the Mi-

croprocessor Write Section). Active High.

4

HSP50214

tion out of the Cartesian to Polar Coordinate converter are

Functional Description

routed to the frequency detector, which is followed by a 63-

tap, 22-bit coefﬁcient FIR ﬁlter structure for facilitating FM and

FSK detection. The 14-bit input resolution is the smallest bit

resolution found throughout the conversion and ﬁltering sec-

tions, providing excellent dynamic range in the DSP process-

ing. A unique input gain scaler adds an additional 42dB of

range to the input level variation, to compensate for changes

in the analog RF front end receive equipment. Synchroniza-

tion circuitry allows precise timing control of the base station

reconﬁguration for all receive channels simultaneously. Por-

tions of this table were corroborated with reference [2].

The HSP50214 Programmable Downconverter (PDC) is an

agile digital tuner designed to meet the requirements of a

wide variety of communications industry standards. The

PDC contains the processing functions needed to convert

sampled IF signals to baseband digital samples. These func-

tions include LO generation/mixing, decimation ﬁltering, pro-

grammable FIR shaping/bandlimiting ﬁltering, re-sampling,

automatic gain control (AGC), frequency discrimination and

detection as well as multi-chip synchronization. The

HSP50214 interfaces directly with a DSP microprocessor to

pass baseband and status data.

TABLE 1. CELLULAR PHONE BASE STATION APPLICATIONS

USING FDMA

A top level functional block diagram of the HSP50214 is

shown in Figure 1. The diagram shows the major blocks and

multiplexers used to reconﬁgure the data path for various

architectures. The HSP50214 can be broken into 13 sec-

tions: Synchronization, Input, Input Level Detector, Carrier

Mixer/Numerically Control Oscillator (NCO), CIC Decimating

Filter, Halfband Decimating Filter, 255-Tap Programmable

FIR Filter, Automatic Gain Control (AGC), Resampler/Half-

band Filter, Timing NCO, Cartesian to Polar Converter, Dis-

criminator, and Output sections. All of these sections are

conﬁgured through a microprocessor interface.

AMPS MCS-L1 NMT-400

STANDARD (IS-91) MCS-L2 NMT-900 C450

ETACS

NTACS

RX BAND 824-849 925-940 453-458 451-456 871-904

(MHz)

890-915

915-925

CHANNEL

BW (kHz)

30

832

FM

25.0

12.5

25

12.5

20.0

10.0

25.0

12.5

# TRAFFIC

CHANNELS

600

1200

200

1999

222

444

1240

800

VOICE

MODULA-

TION

FM

9.5

FSK

6.4

8

The HSP50214 has three clock inputs; two are required and

one is optional. The input level detector, carrier NCO, and CIC

decimating ﬁlter sections operate on the rising edge of the

input clock, CLKIN. The halfband ﬁlter, programmable FIR ﬁl-

ter, AGC, Resampler/Halfband ﬁlters, timing NCO, discrimina-

tor, and output sections operate on the rising edge of

PROCCLK. The third clock, REFCLK, is used to generate tim-

ing error information.

PEAK

DEVIATION

(kHz)

12

FSK

8

5

4

CONTROL

MODULA-

TION

FSK

4.5

0.3

FSK

3.5

1.2

FSK

2.5

5.3

PEAK

DEVIATION

(kHz)

NOTE: All of the clocks may be asynchronous.

CONTROL

CHANNEL

RATE

10

PDC Applications Overview

This section highlights the motivation behind the key program-

mable features from a communications system level perspec-

tive. These motivations will be deﬁned in terms of ability to

provide DSP processing capability for speciﬁc modulation for-

mats and communication applications. The versatility of the

Programmable Downconverter can be intimidating because of

the many Control Words required for chip conﬁguration. This

section provides system level insight to help allay reservations

about this versatile DSP product. It should help the designer

capitalize on the greatest feature of the PDC - VERSATILITY

THROUGH PROGRAMMABILITY. It is this feature, when fully

understood, that brings the greatest return on design invest-

ment by offering a single receiver design that can process the

many waveforms required in the communications marketplace.

(Kbps)

TDM Based Standards and Applications

Table 2 provides an overview of some common time division

multiplying (TDM) base station applications to which the

PDC can be applied. For time division multiple access

(TDMA) applications, such as North American TDMA

(IS136), where 30kHz is the received band of interest the

PCS basestation, the PDC offers 0.012Hz frequency resolu-

tion in downconversion in addition to α = 0.35 matched (pro-

grammable) ﬁltering capability. The π/4 DPSK modulation

can be processed using the PDC Cartesian to Polar coordi-

nate converter and dφ/dt detector circuitry or by processing

the I/Q samples in the DSP µP. The PDC provides the ability

to change the received signal gain and frequency, synchro-

nous with burst timing. The synchronous gain adjustment

allows the user to measure the power of the signal at the A/D

at the end of a burst, and synchronously reload that same

gain value at the arrival of the next user burst.

FDM Based Standards and Applications

Table 1 provides an overview of some common frequency

division multiplex (FDM) base station applications to which the

PDC can be applied. The PDC provides excellent selectivity

for frequency division multiple access (FDMA) signals. This

high selectivity is achieved with 0.012Hz resolution frequency

control of the NCO and the sharp ﬁlter responses capable

with a 255-tap, 22-bit coefﬁcient FIR ﬁlter. The 16-bit resolu-

For applications other than cellular phones (where the pre-

ambles are not changed), the PDC frequency discriminator

output can be used to obtain correlation on the preamble

pattern to aid in burst acquisition.

6

HSP50214

versions of these formats, ASK and FSK are also readily pro-

TABLE 2. CELLULAR BASESTATION APPLICATIONS USING

TDMA

cessed using the PDC. Just as in the AM modulated case, ASK

signals will use 15-bit magnitude output of the Cartesian to

Polar Coordinate converter. Multi-tone FSK can be processed

several ways. The frequency information out of the discrimina-

tor can be used to identify the received tone, or the ﬁlter can be

used to identify and power detect a speciﬁc tone of the received

signal. AMPS is an example of a FM application.

STANDARD

GSM

PCN

IS-54

TYPE

Cellular

935-960

Cellular

824-849

BASESTATION RX

BAND (MHz)

1805-1880

CHANNEL BW (kHz)

# TRAFFIC CHANNELS

VOICE MODULATION

200

8

200

16

30

3

PM and PSK

The PDC provides the downconversion, demodulation,

matched ﬁltering and coordinate conversion required for

demodulation of PM and PSK modulated waveforms. These

modulation formats will require external carrier and symbol

timing recovery loop ﬁlters to complete the receiver design.

The PDC was designed to interface with the HSP50210 Dig-

ital Costas Loop to implement the carrier phase and symbol

timing recovery loop ﬁlters.

GMSK

π/4

DPSK

CHANNEL RATE (Kbps)

270.8

48.6

CONTROL

GMSK

π/4

MODULATION

DPSK

CHANNEL RATE (Kbps)

270.8

48.6

Several applications are combinations of frequency and time

domain multiple access schemes. For example, GSM is a

TDMA signal that is frequency hopped. The individual chan-

nels contain Gaussian MSK modulated signals. The PDC

again offers the 0.012Hz tuning resolution for de-hopping the

received signal. The combination of halfband and 256-tap

programmable, 22-bit coefﬁcient FIR ﬁlters readily performs

the necessary matched ﬁltering for demodulation and opti-

mum detection of the GMSK signals.

Digital modulation formats that combine amplitude and

phase for symbol mapping, such as m-ary QAM can also be

downconverted, demodulated, and matched ﬁltered. The

received symbol information is provided with 16 bits of reso-

lution in either Cartesian or Polar coordinates to facilitate

remapping into bits and to recover the carrier phase. Exter-

nal Symbol mapping and Carrier Recovery Loop Filtering is

required for this waveform.

Re-Sampling and Interpolation Filters

CDMA Based Standards and Applications

Two key features of the re-sampling FIR ﬁlter are that the

resampler ﬁlter allows the output sample rate to be pro-

grammed with millihertz resolution and that the output sam-

ple rate can be phase locked to an independent separate

clock. The resampler frees the front end sampling clocks

from having to be synchronous or integrally related in rate to

the baseband output. The asynchronous relationship

between front end and back end clocks is critical in applica-

tions where ISDN interfaces drive the baseband interfaces,

but the channel sample rates are not related in any way. The

interpolation halfband ﬁlters can increase the rate of the out-

put when narrow frequency bands are being processed. The

increase in output rate allows maximum use of the program-

mable FIR while preserving time resolution in the baseband

data.

For Code Division Multiple Access (CDMA) type signals, the

PDC offers the ability to have a single wideband RF front

end, from which it can select a single spread channel of

interest. The synchronization circuitry provides for easy con-

trol of multiple PDC for applications where multiple received

signals are required, such as base-stations.

In IS-95 CDMA, the receive signal bandwidth is 1.2288MHz

wide with many spread spectrum channel in the band. Each

spread channel is a QPSK signal. The PDC supplies the

downconversion and ﬁltering required to receive a single

spread channel in the presence of strong adjacent interfer-

ence. Multiple PDC’s would be sourced from a single receive

RF chain, each processing a different receive frequency

channel. The despreader would usually follow the PDC. In

some very speciﬁc applications, with short, ﬁxed codes, the

ﬁltering and despreading may be possible with innovative

use of the programmable, 22-bit coefﬁcient FIR ﬁlter. The

PDC offers 0.012Hz resolution on tuning to the desired

receive channel and excellent rejection of the portions of the

band not being processed, via the halfband and 255-tap pro-

grammable, 22-bit coefﬁcient FIR ﬁlter.

14-Bit Input and Processing Resolution

The PDC maintains a minimum of 14 bits of processing reso-

lution through to the output. Which provides over 84dB of

dynamic range. The 18 bits of resolution on the internal ref-

erences provide a spurious ﬂoor that is better than 98dBc.

Furthermore, the PDC provides up to 42dB of gain scaling to

compensate for any change in gain in the RF front end as

well as up to 96dB of gain in the internal PDC AGC. This

gain maximizes the output resolution for small signals and

compensates for changes in the RF front end gain, to handle

Traditional Modulation Formats

AM, ASK, FM and FSK

The PDC has the capability to fully demodulate AM and FM changes in the incoming signal.

modulated waveforms. The PDC outputs 15 bits of amplitude or

16 bits of frequency for these modulation formats. The FM dis-

criminator has a 63-tap programmable, 22-bit coefﬁcient FIR ﬁl-

ter for additional signal conditioning of the FM signal. Digital

7

HSP50214

Summary

reset on SYNCIN2 using Control Word 7, bit 21. The

MSYNCO of one of the PDCs is then used to drive the MSI

of all the PDCs (including its own).

The greatest feature of the PDC is its ability to be reconﬁg-

ured to process many common standards in the communica-

tions industry. Thus, a single hardware element can receive For application conﬁgurations where CLKIN and PROCCLK

and process a wide variety of signals from PCS to traditional have the same source, SYNCIN1 and SYNCIN2 can be tied

cellular, from wireless local loop to SATCOM. The high reso- together. However, if different enabling is desired for the front

lution frequency tuning and narrowband ﬁltering are instru- end and backend processing of the PDC’s, these signals can

mental in almost all of the applications.

still be controlled independently.

In summary, SYNCIN1 is used to update phase offset,

update center frequency, reset CIC decimation counters and

reset the carrier NCO (clear the feedback in the NCO).

SYNCIN2 is used to reset the HB ﬁlter, FIR ﬁlter,

resampler/HB state machines and the output FIFO, load a

new gain into the AGC and load a new resampler NCO cen-

ter frequency and phase offset.

Multiple Chip Synchronization

Multiple PDCs are synchronized using a MASTER/SLAVE

conﬁguration. One part is responsible for synchronizing the

front end internal circuitry using CLKIN while another part is

responsible for synchronizing the backend internal circuitry

using PROCCLK.

The PDC is synchronized with other PDCs using ﬁve control

lines: SYNCOUT, SYNCIN1, SYNCIN2, MSYNCO, and

Input Section

MSYNCI. Figure 2 shows the interconnection of these ﬁve The block diagram of the input controller is provided in Fig-

signals for multiple chip synchronization where different ure 3. The input can support offset binary or two’s comple-

sources are used for CLKIN and PPOCCLK.

ment data and can be operated in gated or interpolated

mode (see Control Word 0 from the Microprocessor Write

Section). The gated mode takes one sample per clock when

the input enable (ENI) is asserted. The gated mode allows

the user to synchronize a low speed sampling clock to a high

speed CLKIN.

PDC A is the Master sync through MSO.

PDC B conﬁgures the CLKIN sync through SYNCIN1.

PDC A conﬁgures the PROCCLK sync through SYNCIN2.

A

B

The interpolated mode allows the user to input data at a low

sample rate and to zero-stuff the data prior to ﬁltering. This

zero stufﬁng effectively interpolates the input signal up to the

rate of the input clock (CLKIN). This interpolated mode

allows the part to be used at rates where the sampling fre-

quency is above the maximum input rate range of the half-

band ﬁlter section, and where the desired output bandwidth

is too wide to use a cascaded integrator comb (CIC) ﬁlter

without signiﬁcantly reducing the dynamic range. See Fig-

ures 4-7 for an interpolated input example, detailing the

associated spectral results.

HSP50214

(MASTER)MSO

MSO

MSI

(MASTER

SYNCIN1)

(MASTER

SYNCIN2)

SYNCOUT

SYNCIN2

SYNCIN1

SYNCOUT

SYNCIN2

SYNCIN1

ALL OTHER SYNCIN1

ALL OTHER SYNCIN2

ALL OTHER MSI

Interpolation Example:

The speciﬁcations for the interpolated input example are:

FIGURE 2. SYNCHRONIZATION CIRCUIT

Input Sample Rate = 5 MSPS

PROCCLK = 28MHz

Interpolate by 8, Decimate by 10

Desired 85dB dynamic range output bandwidth = 500kHz

SYNCOUT for PDC B should be set to be synchronous with

CLKIN (Control Word 0, bit 3 = 0. See the Microprocessor

Write Section). SYNCOUT for PDC B is tied to the SYNCIN1

of all the PDCs. The SYNCIN1 can be programmed so that

the carrier NCO and/or the 5th order CIC ﬁlter of all PDCs can Input Level Detector

be synchronously loaded/updated using SYNCIN1. See Con-

trol Word 0, bits 19 and 20 in the Microprocessor Write Sec-

tion for details.

The Input Level Detector Section measures the average

magnitude error at the PDC input for the microprocessor by

comparing the input level against a programmable thresh-

old and then integrating the result. It is intended to provide

a gain error for use in an AGC loop with either the RF/IF or

A/D converter stages (see Figure 8). The AGC loop

includes Input Level Detector, the microprocessor and an

external gain control ampliﬁer (or attenuator). The input

samples are rectiﬁed and added to a threshold pro-

grammed via the microprocessor interface, as shown in

Figure 9. The bit weighting of the data path through the

SYNCOUT for one of the other PDC’s besides PDC B,

should be set for PROCCLK (bit 3 = 1 in Control Word 0).

This output signal is tied to the SYNCIN2 of all PDCs. The

SYNCIN2 can be programmed so that the AGC updates its

accumulator with the contents in the master registers (Con-

trol Word 8, bit 29 in the Microprocessor Write Section).

SYNCIN2 is also used to load or reset the timing NCO using

bit 5, Control Word 11. The halfband and FIR ﬁlters can be

8

HSP50214

input threshold detector is shown in Figure 10. The thresh- cessor interface through Control Word 1. Only the upper 16

old is a signed number, so it should be set to the inverse of bits are programmable. The 2 LSBs are always zero. Con-

the desired input level. The threshold can be set to zero if trol Word 1, bits 29-14 are programmed to:

the average input level is desired instead of the error. The

(EQ. 1)

ICPrel = (N) ⁄ 4 + 1

sum of the threshold and the absolute value of the input is

accumulated in a 32-bit accumulator. The accumulator can

handle up to 2 samples without overﬂow. The integration

time is controlled by an 18-bit counter. The integration

counter preload (ICPrel) is programmed via the micropro-

where N is the desired integration period, deﬁned as the

number of input samples to be integrated. N must be a multi-

18

ple of 4: [0, 4, 8, 12, 16 .... , 2 ].

INPUT LEVEL DETECTOR †

STATUS (0) †

INPUT_THRESH †

LEVEL

DETECT

INTG_MODE †

INTG_INTEVAL †

IN(13:0)

BYPASS †

INPUT

FORMAT†

NCO††

4

LIMIT

EN

3

GAINADJ(2:0)

DELAY 3

∑

4

ENI

DELAY 3

INTERP †

CONTROL WORD 0

CONTROL WORD 1

OFFSET_BIN †

CONTROL

LOGIC

INPUT_THRESH†

INTG_MODE†

INTG_INTEVAL†

† Controlled via microprocessor interface.

†† See NCO section for more details.

CLKIN

FIGURE 3. BLOCK DIAGRAM OF THE INPUT SECTION

↑ 8 (0 STUFF) = 40MHz

4MHz

BYPASS

PROCCLK = 28MHz

CIC FILTER

R = ↓10

500kHz = 85dB

BANDWIDTH

(NOT ACHIEVED

WITH CIC FILTER

PATH)

5MHz

500kHz = 85dB

BANDWIDTH

HB/FIR FILTER

CIC

FILTER

5MHz

MAX. f = 4MHz

S

(EXCEEDED IN

BYPASS PATH)

MIN. R = 4

Without Interpolation, the CIC bypass path exceeds the HB/FIR ﬁlter

input sample rate and the CIC ﬁlter path will not yield the desired 85dB

dynamic range band width of 500kHz.

FIGURE 5. BLOCK DIAGRAM OF THE INTERPOLATION

APPROACH

FIGURE 4. STATEMENT OF THE PROBLEM

9

HSP50214

f

2f

10MHz

3f

15MHz

4f

20MHz

5f

25MHz

6f

30MHz

7f

35MHz

8f

40MHz

9f

45MHz

10f

S

50MHz

S

5MHz

THE INPUT DATA SPECTRUM SAMPLED AT RATE R = f

S

f’ /8

S

5MHz

f’s/4

10MHz

3f’ /8

S

15MHz

f’ /2

S

20MHz

5f’ /8

S

25MHz

3f’ /4

S

30MHz

7f’ /8

S

35MHz

f’

S

40MHz

FIGURE 6. INTERPOLATION SPECTRUM: INTERPOLATE BY 8 THE INPUT DATA WITH ZERO STUFFING; SAMPLE AT RATE R = f’

S

4MHz 8MHz 12MHz 16MHz 20MHz 24MHz 28MHz 32MHz 36MHz 40MHz

DECIMATE BY 10 AND CIC FILTER; SAMPLE AT RATE R = f’ /10

S

85dB DYNAMIC RANGE BANDWIDTH

CIC FILTER ALIAS PROFILE

CIC FILTER

FREQUENCY

RESPONSE

O.5MHz

1MHz

2MHz

3MHz

4MHz

FIGURE 7. ALIAS PROFILE AND THE 85dB DYNAMIC RANGE BANDWIDTH

µPROC

INPUT LEVEL

DETECTOR (24-BIT

ERROR VALUE)

DAC

THRESH

IF

INPUT

A/D

PDC

GCA

FIGURE 8. PROCESSOR BASED EXTERNAL IF AGC

ACCUMULATOR

32

ADDR(2:0)

INPUT

GATING

LOGIC

24

TO

R

E

G

M

U

X

+

|X|

IN(13:0)

µPROC

E

8

G

CLKIN

R

INPUT_THRESHOLD †

E

G

INTEGRATION_INTERVAL†

“0”

16

START †

INTEGRATION_MODE †

COUNTER

CLKIN

CONTINUOUS

SINGLE

† Controlled via microprocessor interface.

FIGURE 9.

10

HSP50214

The integration period counter can be set up to run Typically, the average input error is read from the Input Level

continuously or to count down and stop. Continuous Detector port for use in AGC applications. By setting the

integration counter operation lets the counter run, with threshold to 0, however, the average value of the input signal

sampling occurring every time the counter reaches zero. can be read directly. The calculation is:

Because the processor samples the detector read port

(EQ. 2)

dBFS

= (20)log[(1.111)(level) ⁄ ((N)(16))]

RMS

asynchronous to the CLKIN, data can be missed unless the

status bit is monitored by the processor to ensure that a

sample is taken for every integration count down sequence.

where “level” is the 24-bit value read from the 3 level detec-

tor registers and “N” is the number of samples to be inte-

grated. Note that to get the average value of a sinusoid,

multiply the RMS value by 1.111. For a full scale input sinu-

soid, this yields an RMS value of approximately 3dBFS.

In the count down and stop mode, the microprocessor read

commands can be synchronized to system events, such as

the start of a burst for a TDMA application. The integration

counter can be started at any time by writing to Control Word

2. At the end of the integration period (counter = 0000), the

upper 23 bits of the accumulator are transferred to a holding

register for reading by the microprocessor. Note that it is not

the restarting of the counter (by writing to Control Word 2)

that latches the current value, but the end of the integration

count. When the accumulator results are latched, a bit is set

in the status register to notify the processor. Reading the

most signiﬁcant byte of the 23 bits clears the status bit. See

the Microprocessor Read Section. Figure 11 illustrates a

typical AGC detection process.

NOTE: 1.111 scales the sinusoid average (2/π) to 1/√2

.

A) INPUT SIGNAL

B) RECTIFIED SIGNAL

C) THRESHOLD

D) ACCUMULATOR INPUTS

E) DETECTOR OUTPUT

F) CLOSED LOOP STEADY STATE

(CONSTANT INPUT)

18

17

16

15

14

13

12

11

10

9

2

FIGURE 11. SIGNAL PROCESSING WITHIN LEVEL DETECTOR

Carrier Synthesizer/Mixer

The carrier synthesizer/mixer section of the HSP50214 is

shown in Figure 12. The NCO has a 32-bit phase accumula-

tor, a 10-bit phase offset adder, and a sine/cosine ROM.

The frequency of the NCO is the sum of a center frequency

control word, loaded via the microprocessor interface (Con-

trol Word 3, bits 0 to 31), and an offset frequency, loaded

serially via the COF and COFSYNC pins. The offset fre-

quency can be zeroed in Control Word 0, bit 1. Both fre-

8

7

6

5

4

3

2

1

f

0

S

2

0

2

-2

-1

-2

-1

-2

-1

-2

-1

-2

-1

-2

-3

-4

-5

-6

-7

-8

-9

-1

-2

-3

-4

-6dB

-12dB

-18dB

-24dB

-30dB

-36dB

-42dB

-48dB

-54dB

-60dB

-66dB

-72dB

-78dB

-84dB

-90dB

2

quency control terms are 32 bits and the addition is modulo

32

2

. The output frequency of the NCO is computed as:

-3

-4

-5

32

(EQ. 3)

-6

F

= f * N ⁄ (2 ) ,

IN

C

-7

-8

or in terms of the programmed value:

-9

-10

-11

-12

-13

-10

-11

-12

-13

-10

-11

-12

-13

-10

-11

-12

-13

-10

-11

-12

-13

2

32

(EQ. 3A)

N = INT[F × 2 ⁄ F

]

,

C

IN HEX

where N is the 32-bit sum of the center and offset frequency

terms, f is the input sampling frequency, and INT is the

integer of the computation. See the Microprocessor Write

Section on instructions for writing Control Word 3.

IN

FIGURE 10. INPUT THRESHOLD DETECTOR BIT WEIGHTING

11

HSP50214

o

For example, if N is 3267 (decimal), and f is 52MHz, then would produce a phase offset of 11.25 and a value of -512

IN

o

F

is 39.55Hz. If received data is modulated at a carrier fre- would produce an offset of 180 . The phase offset is loaded via

C

quency of 10MHz, then the synthesizer/mixer should be pro- the microprocessor interface. See the Microprocessor Write

grammed for N = 313B13B1 (hex) or CEC4EC4F(hex). Section on instructions for writing Control Word 4.

Because the input enable, ENI, controls the operation of the The most signiﬁcant 18 bits from the phase adder are used

phase accumulator, the NCO output frequency is computed as the address a sin/cos look-up table. This look-up table

relative to the input sample rate, f , not to f

. The fre- maps phase into sinusoidal amplitude. The sine and cosine

IN CLKIN

quency control, N, is interpreted as two’s complement values have 18 bits of amplitude resolution. The spurious

because the output of the NCO is quadrature. Negative fre- components in the sine/cosine generation are at least

quency L.O.s select the upper sideband; positive frequency -96dBc. The sine and cosine samples are routed to the

L.O.s select the lower sideband. The range of the NCO is - mixer section whSere they are multiplied with the input sam-

f /2 to +f /2. The frequency resolution of the NCO is ples to translate the signal of interest to baseband.

IN IN

32

f /(2 ) or approximately 0.012Hz when CLKIN is 52 MSPS

IN

The mixer multiplies the 14-bit input by the 18-bit quadrature

sinusoids. The mixer equations are:

and ENI is tied low.

TO MIXERS

COS

18 18

SIN

(EQ. 5)

I

= I × cos(ω )

IN c

OUT

(EQ. 5A)

REG

Q

= I × sin(ω )

IN c

OUT

CARRIER

PHASE

STROBE†

The mixer output is rounded symmetrically to 15 bits.

SIN/COS

ROM

To allow the frequency and phase of multiple parts to be

updated synchronously, two sets of registers are used for

latching the center frequency and phase offset words. The

offset phase and center frequency control words are ﬁrst

loaded into holding registers. The contents of the holding

registers are transferred to active registers in one of two

ways. The ﬁrst technique involves writing to a speciﬁc Con-

trol Word Address. A processor write to Control Word 5,

transfers the center frequency value to the active register

while a processor write to Control Word 6 transfers the

phase offset value to the active register.

18

R

E

G

R

E

G

CARRIER

PHASE

10

+

OFFSET†

CLEAR

PHASE

0

ACCUMULATOR

ACCUM †

R

E

G

ENI

REG

MUX

+

COF

ENABLE†

MUX

32

The second technique, designed for synchronizing updates

to multiple parts, uses the SYNCIN1 pin to update the active

registers. When Control Word 1, bit 20 is set to 1, the

SYNCIN1 pin causes both the center frequency and phase

offset holding registers to be transferred to active registers.

Additionally, when Control Word 0, bit 0 is set to 1, the feed-

back in the phase accumulator is zeroed when the transfer

from the holding to active register occurs. This feature pro-

vides synchronization of the phase accumulator starting

phase of multiple parts. It can also be used to reset the

phase of the NCO synchronous with a speciﬁc event.

0

CF

COF

CARRIER

FREQUENCY

STROBE †

REG

SYNC

REG

COFSYNC

COF

CARRIER

LOAD ON

UPDATE†

SHIFT REG

CARRIER

FREQUENCY†

SYNC

CIRCUITRY

SYNCIN1

† Controlled via microprocessor interface.

FIGURE 12. BLOCK DIAGRAM OF NCO SECTION

The carrier offset frequency is loaded using the COF and

COFSYNC pins. Figure 13 details the timing relationship

between COF, COFSYNC and CLKIN. The offset frequency

word can be zeroed if it is not needed. Similarly, the

Sample Offset Frequency register controlling the resampler

NCO is loaded via the SOF and SOFSYNC pins. The

procedure for loading data through the two pin NCO

interfaces is identical except that the timing of SOF and

SOFSYNC is relative to PROCCLK.

The phase of the Carrier NCO can be shifted by adding a

10-bit phase offset to the MSB’s (modulo 360 ) of the output

o

of the phase accumulator. This phase offset control has a

o

resolution of 0.35 and can be interpreted as two’s comple-

o

ment from -180 to 180 (-π to π) or as binary from 0 to

o

360 (0 to 2π). The phase offset is given by:

10

9

φ

= 2π × (PO ⁄ 2 );(–(2 – 1) < PO < (2 – 1))

(EQ. 4)

OFF

or, in terms of the parameter to be programmed:

10

PO = INT[(2

φ

) ⁄ 2π ]

;(–π < φ

< π)

(EQ. 4A)

OFF

HEX

OFF

where PO is the 10-bit two’s complement value loaded into the

Phase Offset register (Control Word 4, bits 9-0). For example, a

value of 32 (decimal) loaded into the Phase Offset register

12

HSP50214

CIC Decimation Filter

CLKIN

The mixer output may be ﬁltered with the CIC ﬁlter or it may be

routed directly to the halfband ﬁlters. The CIC ﬁlter is used to

reduce the sample rate of a wideband signal to a rate that the

halfbands and programmable ﬁlters can process, given the

maximum computation speed of PROCCLK. (See Halfband

and FIR Filter Sections for techniques to calculate this value.)

COFSYNC/

SOFSYNC

COF/

SOF

MSB

LSB MSB

OTE: Data must be loaded MSB first.

Prior to the CIC ﬁlter, the output of the mixer goes through a

barrel shifter. The shifter is used to adjust the gain in 6dB

steps to compensate for the variation in ﬁlter gain with deci-

mation. (See Equation 6). Fine gain adjustments must be

done in the AGC section. The shifter is controlled by the sum

of a 4-bit CIC Shift Gain word from the microprocessor and a

3-bit gain word from the GAINADJ(2:0) pins. The three bit

value is pipelined to match the delay of the input samples.

The sum of the 3 and 4-bit shift gain words saturates at a

value of 15. Table 3 details the permissible values for the

GAINADJ(2:0) barrel shifter control, while the Figure 15

shows the permissible CIC Shift Gain values.

IGURE 13. SERIAL INPUT TIMING FOR COF AND SOF INPUTS

Each serial word has a programmable word width of either 8,

16, 24, or 32 bits (See Control Word 0, bits 4 and 5, for the

Carrier NCO programming and Control Word 11, bits 3 and

4, for Timing NCO programming). On the rising edge of the

clock, data on COF or SOF is clocked into an input shift reg-

ister. The beginning of a serial word is designated by assert-

ing either COFSYNC or SOFSYNC “high” one CLK period

prior to the ﬁrst data bit.

The assertion of the COFSYNC (or SOFSYNC) starts a count

down from the programmed word width. On following CLKs,

data is shifted into the register until the speciﬁed number of

bits have been input. At this point the contents of the register

are transferred from the shift register to the respective 32-bit

holding register. The shift register can accept new data on the

following CLK. If the serial input word is deﬁned to be less

than 32 bits, it will be transferred to the MSBs of the 32-bit

holding register and the LSBs of the holding register will be

zeroed. See Figure 14 for details.

The CIC ﬁlter structure for the HSP50214 is ﬁfth order; that

is it has ﬁve integrator/comb pairs. A ﬁfth order CIC has

84dB of alias attenuation for output frequencies below 1/8

the CIC output sample rate.

15

8-BIT INPUT

14

10-BIT INPUT

13

12-BIT INPUT

12

14-BIT INPUT

11

32†

30

28

10

ALLOWABLE CIC SHIFT

GAINS ARE BELOW THE

CURVES

9

8

7

6

5

4

3

2

1

0

26

ASSERTION OF

COFSYNC, SOFSYNC

24†

22

20

18

16†

14

12

10

8†

6

DATA TRANSFERRED

TO HOLDING REGISTER

(8)

(24) (32)

4

8

12 16 20 24 28 32 36 40 44 48 52 56 60 64

DECIMATION (R)

(16)

4

2

0

FIGURE 15. CIC SHIFT GAIN VALUES

2

6

10 14 18 22 26 30 34 38 42 46 50 54

CLK TIMES

T ††

D

The decimation rate of the CIC ﬁlter is programmed in Control

Word 0, bits 12 - 7. The CIC Shift Gain is programmed in Con-

trol Word 0, bits 16-13. The CIC Bypass is set in Control Word

0, bit 6.

T ††

D

T ††

D

T ††

D

†Serial word width can be: 8, 16, 24, 32 bits wide.

TABLE 3. GAIN ADJUST CONTROL AND CIC DECIMATION

†T is determined by the COFSYNC, COFSYNC rate.

D

∆GAIN VALUE

MAX. CIC

(dB)

GAIN ADJ(2:0)

DECIMATION

FIGURE 14. HOLDING REGISTERS LOAD SEQUENCE FOR

COF AND SOF SERIAL OFFSET FREQUENCY

DATA

0

000

001

010

011

100

101

110

111

32

27

24

21

18

16

12

10

6

12

18

24

30

36

42

NOTE: Serial Data must be loaded MSB first, and COFSYNC or

SOFSYNC should not be asserted for more than one CLK

cycle.

NOTE: COF loading and timing is relative to CLKIN while SOF

loading and timing is relative to PROCCLK.

NOTE: T can be 0, and the fastest rate is with 8-bit word width.

D

13

HSP50214

CIC Gain Calculations

would not drop by 12dB. This ﬁxed gain adjust eliminates the

need for the software to continually normalize.

The gain through the CIC ﬁlter increases with increased dec-

imation. The programmable barrel shifter that precedes the One must, exercise care when using this function as it can

ﬁrst integrator in the CIC is used to offset this variation. Gain cause overﬂow in the CIC ﬁlter. Each gain adjust in the

variations due to decimation should be offset using the 4-bit shifter from the gain adjust control signals is the equivalent

CIC Shift Gain word. This allows the input signal level to be of an extra bit of input. The maximum decimation in the CIC

adjusted in 6dB steps to control the CIC output level.

is reduced accordingly. With a decimation of 32, all 40 bits of

the CIC are needed, so no input offset gain is allowed. As

the decimation is reduced, the allowable offset gain

increases. Table 3 shows the decimation range versus

desired offset gain range. Table 3 assumes that the CIC Shift

Gain has been programmed per Equation 7 or 8A.

The gain at each stage of the CIC is:

N

(EQ. 6)

k = R ,

where R is the decimation factor and N is the number of stages.

The input to the CIC from the mixer is 15 bits, and the bit widths

of the accumulators for the ﬁve stages in the HSP50214 are 40,

36, 32, 32, and 32, as shown in Figure 16. This limits the maxi-

mum decimation in the CIC to 32 for a full scale input.

The CIC ﬁlter decimation counter can be loaded synchronous

with other PDC chips, using the SYNCIN1 signal and the CIC

External Sync Enable bit. The CIC external Sync Enable is set

via Control Word 0, bit 19.

5

25

If R is 32, the gain through all ﬁve integrator stages is 32 = 2

.

20

(The gain through the last four CIC stages it is 2 , through the

15

last 3 it is 2 , etc.) The sum of the input bits and the growth

bits cannot exceed the accumulator size. This means that for a

decimation of 32 and 15 input bits, the ﬁrst accumulator must

be 15 + 25 = 40 bits.

0

2

0

2

0

2

0

2

0

2

0

2

-1

-2

-3

Thus the value of the CIC Shift Gain word can be calculated:

(EQ. 7)

-4

-5

-6

-7

-8

NOTE: The number of input bits is IIN. (If the number of bits into

the CIC filter used the value 40 replaces 39).

-9

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

-24

-25

-26

-27

-28

-29

-30

-31

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

-24

-25

-26

-27

-28

-29

-30

-31

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

-24

-25

-26

-27

-28

-29

-30

-31

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

-24

-25

-26

-27

-28

-29

-30

-31

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

-24

-25

-26

-27

-28

-29

-30

-31

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

-22

-23

0

2

For 14 bits, Equation 7 becomes:

-1

5

-2

SG = FLOOR[25 – log (R) ]for 4 < R < 32

2

(EQ. 8A)

(EQ. 8B)

-3

= 15

for R = 4

-4

-5

For 12 bits, Equation 7 becomes:

-6

-7

5

SG = FLOOR[27 – log (R) ]for 5 < R < 40

2

-8

= 15

for 4 ≤ R ≤ 5

-9

-10

-11

-12

-13

-14

For 10 bits, Equation 7 becomes:

5

SG = FLOOR[29 – log (R) ]for 6 < R < 52

2

(EQ. 8C)

(EQ. 8D)

= 15

for 4 ≤ R ≤ 6

0

2

-1

For 8 bits, Equation 7 becomes:

-2

5

SG = FLOOR[31 – log (R) ]for 9 < R < 64

-3

2

-4

= 15

for 4 ≤ R ≤ 9

-5

-6

Figure 15 is plot of Equations 8A through 8D. The 4-bit CIC

Shift Gain word has a range from 0 to 15. The 6-bit Decima-

tion Rate Register, (R-1), has a range from 0 to 63, limited by

the input resolution as cited above.

-7

-32

-33

-34

-35

-36

-37

-38

-39

-32

-33

-34

-35

2

-8

-9

-10

-11

-12

-13

-14

Using the Input Gain Adjust Control Signals

The input gain offset control GAINADJ(2:0)) is provided to offset

the signal gain through the part, i.e. to keep the CIC ﬁlter output

level constant as the analog front end attenuation is changed.

The gain adjust offset is 6dB per code, so the gain adjust range is

0 to 42dB. For example, if 12dB of attenuation is switched in at

the receiver RF front end, a code of 2 would increase the gain at

the input to the CIC ﬁlter up 12dB so that the CIC ﬁlter output

FIGURE 16. CIC FILTER BIT WEIGHTING

NOTE: If 14 input bits are not needed, the gain adjust can be in-

creased by one for each bit that the input is shifted down

at the input. For example, if only 12 bits are needed, an

offset range of 24dB is possible for a decimation of 24.

14

HSP50214

Halfband Decimating Filters

HALFBAND

FILTER INPUT

The Programmable Down Converter has ﬁve halfband ﬁlter

stages, as shown in Figure 17. Each stage decimates by 2

and ﬁlters out half of the available bandwidth. The ﬁrst half-

band, or HB1, has 7 taps. The remaining halfbands; HB2,

HB3, HB4, and HB5; have 11, 15, 19, and 23 taps respec-

tively. The coefﬁcients for these halfbands are given in Table

4. Figure 18 shows the frequency response of each of the

f

= f

S

IN

F

= f

IN

N

†

HALFBAND FILTER 1

1

0

CONTROL WORD 7, BIT 15

halfband ﬁlters with respect to normalized frequency, F .

N

F

= f OR f /2

S S

HB1

F

= F

HB1

N

Frequency normalization is with respect to the input sam-

pling frequency of each ﬁlter section. Each stage is activated

by their respective bit location (15-20) in Control Word 7. Any

combination of halfband ﬁlters may be used, or all may be

bypassed. Figure 19 details the halfband alias proﬁles with

†

HALFBAND FILTER 2

0

1

CONTROL WORD 7, BIT 16

F

= F

OR F

HB1

/2

HB1

HB2

F

= F

HB2

N

respect to normalized frequency F .

N

†

HALFBAND FILTER 3

Since each halfband ﬁlter section decimates by 2, the total

decimation through the halfband ﬁlter is given by:

0

1

CONTROL WORD 7, BIT 17

N

DEC = 2

(EQ. 9)

F

= F

OR F

/2

HB2

HB

HB3

HB2

F

= F

HB3

N

†

HALFBAND FILTER 4

where N = Number of Halfband Filters Selected (1 - 5).

0

1

CONTROL WORD 7, BIT 18

F

= F

OR F

/2

HB4

HB3

†

F

= F

HB4

N

HALFBAND FILTER 5

1

CONTROL WORD 7, BIT 19

0

F

= F

OR F

HB4

/2

HB4

5

HALFBAND

FILTER OUTPUT

† Each halfband section decimates by 2

FIGURE 17. BLOCK DIAGRAM OF HALFBAND FILTER

SECTION

0

ALIAS

-6dB BANDWIDTH

-20

PROFILES

-20

-40

HALFBAND FILTER 5

HALFBAND FILTER 4

HALFBAND FILTER 3

HALFBAND FILTER 2

HALFBAND FILTER 1

-60

-80

HALFBAND FILTER 5

-80

HALFBAND FILTER 4

HALFBAND FILTER 3

HALFBAND FILTER 2

HALFBAND FILTER 1

-100

-120

-100

-120

0.125

0.25

0.375

0.5

0.125

0.25

0.375

0.5

NORMALIZED FREQUENCY (F )

N

FIGURE 19. HALFBAND FILTER ALIAS CONSIDERATIONS

FIGURE 18. HALFBAND FILTER FREQUENCY RESPONSE

15

HSP50214

TABLE 4. HALFBAND FILTER COEFFICIENTS

COEFFICIENTS

C0

HALFBAND #1

- 0.031303406

0.000000000

0.281280518

0.499954224

0.281280518

0.000000000

- 0.031303406

HALFBAND #2

0.005929947

0.000000000

-0.049036026

0.000000000

0.29309082

HALFBAND #3

-0.00130558

-0.000000000

-0.012379646

-0.000000000

-0.06055069

-0.000000000

-0.299453735

-0.499954224

-0.299453735

-0.000000000

-0.06055069

-0.000000000

-0.012379646

-0.000000000

-0.00130558

HALFBAND #4

-0.000378609

-0.000000000

-0.003810883

-0.000000000

-0.019245148

-0.000000000

-0.069904327

-0.000000000

-0.304092407

-0.500000000

-0.304092407

0.000000000

-0.069904327

-0.000000000

-0.019245148

-0.000000000

-0.003810883

-0.000000000

-0.000378609

HALFBAND #5

-0.000347137

-0.000000000

-0.00251317

-0.000000000

-0.010158539

-0.000000000

-0.03055191

-0.000000000

-0.081981659

-0.000000000

-0.309417725

-0.500000000

-0.309417725

-0.000000000

-0.081981659

-0.000000000

-0.03055191

-0.000000000

-0.010158539

-0.000000000

-0.00251317

-0.000000000

-0.000347137

C1

C2

C3

C4

C5

0.499969482

0.29309082

C6

C7

0.000000000

-0.049036026

0.000000000

0.005929947

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

NOTE: While Halfband filters are typically selected starting with the last stage in the filter chain to give the maximum alias free

bandwidth, a higher throughput rate may be obtained using other filter combinations. See Application Note 9720, “Calculat-

ing Maximum Processing Rates of the PDC”.

Depending on the number of halfbands used, PROCCLK where:

must operate a some minimum rate above the input sample

rate, F , to the halfband. This relationship depends on the

S

number of multiplies for each of the halfband ﬁlter stages.

The ﬁlter calculations take 3, 4, 5, 6, and 7 multiplies per

input for HB1, HB2, HB3, HB4, and HB5 respectively. If we

HB1 = 1 if this section is selected and 0 if it is bypassed;

HB2 = 1 if this section is selected and 0 if it is bypassed;

HB3 = 1 if this section is selected and 0 if it is bypassed;

HB4 = 1 if this section is selected and 0 if it is bypassed;

HB5 = 1 if this section is selected and 0 if it is bypassed;

T = number of Halfband Filters Selected. The range for T is

from 0 to 5.

keep the assumption that f is the input sampling frequency,

S

then Equation 10 shows the minimum ratio needed.

HB5

f

/f ≥ ([(7)(HB5)(2

)+

PROCCLK S

Examples of PROCCLK Rate Calculations

(HB4 + HB5)

(6)(HB4)(2

(5)(HB3)(2

(4)(HB2)(2

(3)(HB1)(2

)+

(HB3+HB4+HB5)

Suppose we enable HB1, HB3, and HB5. Using Figure 16,

HB1= 1, HB3 = 1, and HB5 = 1. Since stage 2 and stage 4

are not used, HB2 and HB4 = 0. PROCCLK must operate

)+

(HB2+HB3+ HB4+HB5)

)+

(HB1+HB2+HB3+HB4+HB5)

faster than (7x2+5x4+3x8)/8 = 7.25 times faster than f .

S

T

)]/2

If all ﬁve halfbands are used, then PROCCLK must operate at

(7x2+6x4+5x8+4x16+3x32)/32 = 7.4375 times faster than f .

(EQ. 10)

S

16

HSP50214

using Control Word 17 bit 9, then coefﬁcients are loaded

255-Tap Programmable FIR Filter

starting with the center coefﬁcient in Control Word 128 and

proceed to last coefﬁcient in Control Word 128+n. The ﬁlter

symmetry type can be set to even or odd symmetric, and the

number of ﬁlter coefﬁcients can be even or odd, as illustrated

in Figure 20. Note that complex ﬁlters can also be realized

but are only allowed to be asymmetric. Only the coefﬁcients

that are used need to be loaded.

The Programmable FIR ﬁlter can be used to implement real

ﬁlters with even or odd symmetry, using up to 255 ﬁlter taps,

or complex ﬁlters with up to 64 taps. The FIR ﬁlter takes

advantage of symmetry in coefﬁcients by summing data

samples that share a common coefﬁcient, prior to multiplica-

tion. In this manner, two ﬁlter taps are calculated per multiply

accumulate cycle. Asymmetric ﬁlters cannot share common

coefﬁcients, so only one tap per multiply accumulate cycle is

calculated. The ﬁlter can be effectively bypassed by setting

the coefﬁcient C = 1 and all other coefﬁcients, C = 0.

0

N

C0

CN-1

COEFFICIENT

NUMBER

Additionally, the Programmable FIR ﬁlter provides for deci-

mation rates, R, from 1 to 16. The processing rate of the Fil-

ter Compute Engine is PROCCLK. As a result, the frequency

of PROCCLK must exceed a minimum value to insure that a

ﬁlter calculation is complete before the result is required for

output. In conﬁgurations which do not use decimation, one

input sample period is available for ﬁlter calculation before

an output is required. For conﬁgurations which employ deci-

mation, up to 16 input sample periods may be available for

ﬁlter calculation.

C0

CN-1

COEFFICIENT

NUMBER

EVEN SYMMETRIC

EVEN TAP FILTER

ODD SYMMETRIC

EVEN TAP FILTER

CN-1

C0

COEFFICIENT

NUMBER

COEFFICIENT

NUMBER

EVEN SYMMETRIC

ODD TAP FILTER

ODD SYMMETRIC

ODD TAP FILTER

For real ﬁlter conﬁgurations, use Equation 11 to calculate the

number of taps available at a given input ﬁlter sample rate.

(EQ. 11A)

TA PS = (floor[PROCCLK ⁄ (F

⁄ R) – R])(1 +

C0

CN-1

SAMP

SYM) – [(SYM)(ODD#)]

COEFFICIENT

NUMBER

COEFFICIENT

NUMBER

for real ﬁlters, and

ASYMMETRIC

ODD TAP FILTER

ASYMMETRIC

EVEN TAP FILTER

(EQ. 11B)

TA PS = floor[(PROCCLK ⁄ (F

⁄ R) – (R] ⁄ 2)]

SAMP

REAL FILTERS

for complex ﬁlters, where ﬂoor is deﬁned as the integer por-

tion of a number; PROCCLK is the compute clock; FSAMP =

the FIR input sample rate; R = Decimation Rate; SYM = 1 for

symmetrical ﬁlter, 0 for asymmetrical ﬁlter; ODD# = 1 for an

odd number of ﬁlter taps, 0 = an even number of taps.

C

Q

C

Q(N-1)

COEFFICIENT

NUMBER

C

Q(0)

C

Use Equation 12 to calculate the maximum input rate.

I(N-1)

F

= (PROCCLK) (R) ⁄ [R + [floor[(Ta ps) +

(SYM)(ODD#)] ⁄ (1 + SYM)]]

(EQ. 12A)

C

SAMP

I(0)

C

I

COMPLEX FILTERS

for real ﬁlters, and

(EQ. 12B)

F

= [(PROCCLK)(R)] ⁄ [R + floor[(Ta ps)(2)]]

SAMP

Deﬁnitions:

Even Symmetric: h(n) = h(N-n-1) for n = 0 to N-1

Odd Symmetric: h(n) = -h(N-n-1) for n = 0 to N-1

Asymmetric: a ﬁlter with no coefﬁcient symmetry

Even Tap ﬁlter: a ﬁlter where N is an even number

for complex ﬁlters, where ﬂoor[x], PROCCLK, FSAMP, R =

Decimation Rate, SYM, and ODD# are deﬁned as in Equa-

tion 11.

Use Equation 13 to calculate the maximum output sample

rate for both real and complex ﬁlters.

Odd Tap ﬁlter:

Real Filter:

a ﬁlter where N is an odd number

a ﬁlter implemented with real coefﬁcients

Complex Filters: a ﬁlter with quadrature coefﬁcients

F

= (F

) ⁄ R

SAMP

(EQ. 13)

FIROUT

FIGURE 20. DEMONSTRATION OF DIFFERENT TYPES OF

DIGITAL FIR FILTERS CONFIGURED IN THE

PROGRAMMABLE DOWNCONVERTER

The coefﬁcients are 22 bits and are loaded using writes to

Control Words 128 through 255 (see Microprocessor Write

Section). For real ﬁlters, the same coefﬁcients are used by I

and Q paths. If the ﬁlter is conﬁgured as a symmetric ﬁlter

17

HSP50214

6

Automatic Gain Control (AGC)

The AGC section provides gain to small signals, after the

large signals and out-of-band noise have been ﬁltered out, to

ensure that small signals have sufﬁcient bit resolution in the

Re-Sampling/Interpolating Halfband ﬁlters and the Output

Formatter. The AGC can also be used to manually set the

gain. The AGC optimizes the bit resolution for a variety of

input amplitude signal levels. The AGC loop automatically

adds gain to bring small signals from the lower bits of the 26-

bit programmable FIR ﬁlter output into the 16-bit range of the

5

4

3

2

1

0

G (dB)

G (LINEAR)

output section. Without gain control, a signal at -72dBFS =

-12

20log (2 ) at the input would have only 4 bits of resolu-

10

tion at the output (12 bits less than the full scale 16 bits). The

potential increase in the bit resolution due to processing gain

of the ﬁlters can be lost without the use of the AGC.

0

16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

AGC CONTROL MANTISSA VALUES (TIMES 256)

FIGURE 21. AGC MULTIPLIER LINEAR AND dB TRANSFER

FUNCTION

Figure 23 shows the block diagram for the AGC Section. The

FIR ﬁlter data output is routed to the Re-Sampling and Half-

band ﬁlters after passing through the AGC multipliers and

shift registers. The outputs of the Interpolating Halfband ﬁl-

ters are routed to the Cartesian to Polar coordinate con-

verter. The magnitude output of the coordinate converter is

routed through the AGC error detector, the AGC error scaler

and into the AGC loop ﬁlter. This ﬁltered error term is used to

drive the AGC multiplier and shifters, completing the AGC

control loop.

100

N = 15

N = 14

N = 13

90

80

70

60

50

40

30

20

10

0

N = 12

N = 11

N = 10

The AGC Multiplier/Shifter portion of the AGC is identiﬁed in

Figure 23. The gain control from the AGC loop ﬁlter is sam-

pled when new data enters the Multiplier/Shifter. The limit

detector detects overﬂow in the shifter or the multiplier and

saturates the output of I and Q data paths independently.

N = 9

N = 8

N = 7

N = 6

The shifter has a gain from 0 to 90.31dB in 6.021dB steps,

N = 5

N = 4

N = 3

N

where 90.31dB = 20log (2 ), when N = 15. The mantissa

10

provides an additional 6dB of gain in 0.0338dB steps where

-8

8

6.004dB = 20log [1+(X)2 ], where X = 2 -1. Thus, the

10

AGC multiplier/shifter transfer function is expressed as:

N = 2

N = 1

N = 0

N

–8

AGC Mult/Shift Gain = 2 [1 + (X)2 ],

(EQ. 14)

where N, the shifter exponent, has a range of 0>N>15 and

8

0

64

128

192

X, the mantissa, has a range of 0>X>(2 -1).

AGC CONTROL WORD (MANTISSA x 256)

Equation 14 can be expressed in dB,

FIGURE 22. AGC GAIN CONTROL TRANSFER FUNCTION

N

–8

(AGC Mult/Shift Gain)dB = 20log (2 [1 + (X)2 ])

(EQ. 14A)

10

The Cartesian to Polar Coordinate converter accepts I and Q

data and generates magnitude and phase data. The magni-

tude output is determined by the equation:

The full AGC range of the Multiplier/Shifter is from 0 to

-8 15

8

96.314dB (20log [1+(2 -1)2 ] + 20log [2 ] = 96.314).

10 10

Figure 21 illustrates the transfer function of the AGC multi-

plier versus mantissa control for N = 0. Figure 22 illustrates

the complete AGC Multiplier/Shifter Transfer function for all

values of exponent and mantissa control.

˙

2

(EQ. 15)

r

= 1.64676 I + Q .

where the magnitude limits are determined by the maximum

I and Q signal levels into the Cartesian to Polar converter.

Taking fractional 2’s complement representation, magnitude

ranges from 0 to 2.329, where the maximum output is

˙

2

r = 1.64676 (1.0) + (1.0) = 1.64676 × 1.414 = 2.329.

The AGC loop feedback path consists of an error detector,

error scaling, and an AGC loop ﬁlter. The error detector sub-

tracts the magnitude output of the coordinate converter from

18

HSP50214

the programmable AGC THRESHOLD value. The bit weight-

TABLE 6A. AGC LIMIT EXPONENT vs GAIN

ing of the AGC THRESHOLD value (Control Word 8, bits 16-

28) is shown in Table 5. Note that the MSB is always zero.

The range of the AGC THRESHOLD value is 0 to 7.9995.

The AGC Error Detector output has the identical range.

GAIN(dB)

EXPONENT

MANTISSA

96.330

90.309

84.288

78.268

72.247

66.227

60.206

54.185

48.165

42.144

36.124

30.103

24.082

18.062

12.041

6.021

15

14

13

12

11

10

9

511

0

TABLE 5. AGC THRESHOLD (CONTROL WORD 8) BIT

WEIGHTING

0

28 27 26 25 24 23 22 21 20 19 18 17 16

0

2

1

0

-1

-2

-3

-4

-5

-6

-7

-8

-9 -10

0

2

2 .

2

0

The loop gain is set in the AGC Error Scaling circuitry, using

the two programmable mantissas and exponents. The man-

tissa, M, is a 4-bit value which weights the loop ﬁlter input

from 0.0 to 0.9375. The exponent, E, deﬁnes a shift factor

0

8

0

7

0

-15

that provides additional weighting from 2 to 2

Together

6

0

the mantissa and exponent deﬁne the loop gain as given by,

5

0

–(15 – E

)

–4

LG

AGC Loop Gain = M

2

(EQ. 16)

4

0

LG

3

0

where M

is a 4-bit binary value ranging from 0 to 15, and

LG

is a 4-bit binary value ranging from 0 to 15. Table 7 and

2

0

E

LG

1

0

8 detail the binary values and the resulting scaling effects of

the AGC Scaling mantissa and exponent. The composite

(shifter and multiplier) AGC scaling Gain range is from

0.000

0

TABLE 6B. AGC LIMIT MANTISSA vs GAIN

0

0.0000 to 2.329(0.9375)2 = 0.0000 to 2.18344. The scaled

GAIN(dB)

EXPONENT

MANTISSA

gain error can range (depending on threshold) from 0 to

2.18344, which maps to a “gain change per sample” range

of 0 to 3.275dB/sample.

6.000

5.750

5.500

5.250

5.000

4.750

4.500

4.250

4.000

3.750

3.500

3.250

3.000

2.750

2.500

2.250

2.000

1.750

1.500

1.250

1.000

0.750

0.500

0.250

0.020

0

509

480

452

425

398

372

347

323

299

276

254

232

211

190

170

151

132

114

96

The AGC Gain mantissa and exponent values are pro-

grammed into Control Word 8, bits 0-15. The PDC provides

for the storing of two values of AGC Scaling Gain (both expo-

nent and mantissa). This allows for quick adjustment of the

loop gain by simply asserting the external control line

AGCGNSEL. When AGCGNSEL = 0, then AGC GAIN 0 is

selected, and when AGCGNSEL = 1, AGC Loop Gain 1 is

selected. Possible applications include acquisition/tracking,

no burst present/burst present, strong signal/weak signal,

track/hold, or fast/slow AGC values.

The AGC loop ﬁlter consists of an accumulator with a built in

limiting function. The maximum and minimum AGC gain lim-

its are provided to keep the gain within a speciﬁed range and

are programed by 12-bit control words using the following

the equation:

–9

e

(EQ. 17)

AGC Gain Limit = (1 + m

2

)2

AGC

(AGC Gain Limit)dB = (6.02)(eeee) + 20log(1.0 + 0.eeeeeeee)

(EQ. 17A)

79

where m is an 8-bit mantissa value between 0 and 511, and e

is the 4-bit exponent ranging from 0 to 15. Control Word 9, bits

16-27 are used for programming the upper limit, while bits 0-

11 are used to program the lower threshold. The ranges and

format for these limit values are shown in Tables 6A - C. The

bit weightings for the AGC Loop Feedback elements is

detailed in Table 9.

62

46

30

14

1

TABLE 6C. AGC LIMIT DATA FORMAT

CONTROL WORD 9 BIT:

FORMAT

27

e

26

e

25

e

24

e

23

m

22

m

21

m

20

m

19

m

18

m

17

m

16

m

19

HSP50214

AGC

ERROR

DETECTOR

AGC ERROR SCALING

(RANGE = 0 TO 2.18344)

AGC LOOP FILTER

16

13

MSB = 0

SERIAL

OUT

+

13

EXP

MANTISSA

4

∆

MSB = 0

µP

LIMIT

DET

AGCGNSEL

UPPER LIMIT †

LOWER LIMIT †

13

MANTISSA =

01.XXXXXXX(XXXXXXX)††

9

MAGNITUDE

4

NNNN

EXP=2

(RANGE = 0 TO 2.3)

LIMIT

DET

(RANGE = 0 TO 1)

18

26

18

IFIR

IAGC

RE-SAMPLING

FIR FILTERS

AND

CARTESIAN

TO

LIMIT

DET

POLAR

INTERPOLATING

HALFBAND

FILTERS

COORDINATE

CONVERTER

(G = 1.64676)

18

26

QFIR

QAGC

AGC MULTIPLIER/SHIFTER

† Controlled via microprocessor interface.

† † Indicates additional resolution of the A version.

FIGURE 23. AGC BLOCK DIAGRAM

Using AGC loop gain, the AGC range, and expected error maximum AGC gain error by the loop gain. The expected

detector output, the gain adjustments per output sample for range for the AGC rate is ~ 0.00004 to 1.23dB/symbol time

the loop ﬁlter section of the Digital AGC can be given by:

for a threshold of 1/2 scale. See the notes at the bottom of

Table 9 for calculation of the AGC Response times. The

maximum AGC Response is given by:

AGC Slew Rate = 1.5dB(THRESH – (MAG*1.64676)) ×

–(15 – E

)

–4

LG

(EQ. 18)

(M )(2 ) 2

LG

AGC Response

= Input(Cart/Polar Gain)(Error Det Gain)(AGC

Max

Loop Gain)(AGC Output Weighting)

(EQ. 19)

The loop gain determines the growth rate of the sum in the

loop accumulator which, in turn, determines how quickly the

AGC gain traces the transfer function given in Figures 21

and 22. Since the log of the gain response is roughly linear,

the loop response can be approximated by multiplying the

Since the AGC error is scaled to adjust the gain, the loop

settles asymptotically to its ﬁnal value. The loop settles to

the mean of the signal.

20

HSP50214

TABLE 7. AGC LOOP GAIN BINARY MANTISSA TO GAIN

SCALE FACTOR MAPPING

Resampler/Halfband Filter

The Resampler is an NCO controlled polyphase ﬁlter that

allows the output sample rate to have a non-integer relation-

ship to the input sample rate. The ﬁlter engine can be viewed

conceptually as a ﬁxed interpolation ﬁlter, followed by an

NCO controlled decimator.

BINARY

CODE

BINARY

CODE

SCALE

(MMMM)

FACTOR

(MMMM)

FACTOR

0000

0001

0010

0011

0100

0101

0110

0111

0.0000

0.0625

0.1250

0.1875

0.2500

0.3125

0.3750

0.4375

1000

1001

1010

1011

1100

1101

1110

1111

0.5000

0.5625

0.6250

0.6875

0.7500

0.8125

0.8750

0.9375

The prototype polyphase ﬁlter has 192 taps designed at 32

times the input sample rate. Each of the 32 phases has 6 ﬁl-

ter taps (6)(32) = 192. The stopband attenuation of the pro-

totype ﬁlter is greater than 60dB, as shown in Figure 24. The

signal to total image power ratio is approximately 55dB, due

to the aliasing of the interpolation images. The ﬁlter is capa-

ble of decimation rates from 1 to 4. If the output is at least 2x

the baud rate, the 32 interpolation phases yield an effective

sample rate of 64x the baud rate or approximately 1.5%,

(1/64), maximum timing error.

Following the Resampler are two interpolation halfband ﬁl-

ters. The halfband ﬁlters allow the user to up-sample by 2 or

4 to recover time resolution lost by decimating. Interpolating

by 2 or 4 gives 1/4 or 1/8 baud time resolution (assuming 2x

baud at the Resampler output). The halfband ﬁlters use the

same coefﬁcients as HB3 and HB5 from the Halfband Filters

Section. If one halfband is used, the 23-tap ﬁlter is chosen. If

two are used, the 23-tap ﬁlter runs ﬁrst followed by the

15-tap ﬁlter operating at twice the ﬁrst halfband’s rate. The

23-tap ﬁlter requires 7 multiplies, and the 15-tap ﬁlter

requires 5 multiplies to complete a ﬁlter calculation.

TABLE 8. AGC LOOP GAIN BINARY EXPONENT TO GAIN

SCALE FACTOR MAPPING

BINARY

CODE

(EEEE)

BINARY

CODE

(EEEE)

SCALE

FACTOR

SCALE

FACTOR

15

2

7

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

2

14

2

6

2

Using the interpolation halfband ﬁlters allows for reduction in

the FIR ﬁlter sample rate. This optimizes the use of the pro-

grammable FIR ﬁlter by allowing the FIR output sample rate

to be closer to the Nyquist rate of the desired bandwidth.

Optimizing the FIR ﬁlter performance provides better use of

the programmable FIR taps. Table 10 details the maximum

clocking rates for the possible re-sampling and interpolation

halfband ﬁlter conﬁgurations of this section of the PDC. Con-

trol Word 16, bits 2-0 identify the ﬁlter conﬁguration. Control

Word 16, bit 3 is used to bypass the polyphase Resampler

ﬁlter.

13

2

5

2

12

2

4

2

11

2

3

2

10-

2

9

1

2

8

0

2

For proper data output from the interpolation ﬁlters, the data

ready signal must account for the re-sampling and interpola-

tion processes. Figure 25 illustrates the insertion of addi-

tional data ready pulses to provide sufﬁcient pulses for the

new output sample rate. The Resampler Output Pulse Delay

parameter is set in Control Word 16, bits 4-11. These bits set

the delay between the output samples when interpolation is

utilized. Program this distance between pulses using

For example, if M

= 0101 and E

= 1100, the AGC

LG

-7

Loop Gain = 0.3125*2 . The loop gain mantissas and

exponents are set in the AGC Loop Parameter control reg-

ister (Control Word 8, bits 0-15). Two AGC loop gains are

provided in the Programmable Down Converter, for quick

adjustment of the AGC loop. The AGC Gain select is a con-

trol input to the device, selecting Gain 0 when AGCGNSEL

= 0, and selecting Gain 1 when AGCGNSEL = 1.

(EQ. 20)

N = [(f

/f

) – 1]

PROCCLK OUT

A value of at least 5 is required to have sufﬁcient time to

update the output buffer register. (Writing 5 samples

requires 5 clock cycles) A value of at least 16 is required for

proper serial output from the part. (Conversion from 16-bit

parallel to serial) The value is programmed in numbers of

PROCCLK’s.

21

HSP50214

.

TABLE 9. BIT WEIGHTING FOR AGC LOOP FEEDBACK PATH

AGC LOOP

FILTER

AGC

OUTPUT

AND AGC

AGC

ACCUM

BIT

GAIN

ERROR

BIT

GAIN

ERROR

AGC LOOP

GAIN

AGC GAIN

FILTER GAIN MULTIPLIER SHIFT

SHIFT

= 4

SHIFT

= 8

SHIFT LIMITS BIT RESOLUTION

POSITION INPUT WEIGHT (MANTISSA)

(OUTPUT)

= 0

2

= 15

WEIGHT

(dB)

31

30

29

28

2

1

2

1

2

1

0

E

3

48

24

2

E

1

12

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

12

11

10

9

= 2

= 1

2

1

2

1

E

0

6

M

X

-1

3

= 0

.

0

.

0

.

0

.

-2

1.5

= 1

= 2

= 3

= 4

= 5

= 6

= 7

= 8

= 9

= 10

x

1

-3

0.75

8

x

2

-4

0.375

7

3

-5

0.1875

0.09375

0.04688

0.02344

0.01172

0.00586

0.00293

0.00146

0.000732

0.000366

0.000183

0.0000916

0.0000458

0.0000229

0.0000114

0.00000572

0.00000286

6

4

-6

5

-7

4

6

-8

3

7

0

.

7

-9

2

8

1

8

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

-21

1

9

2

9

0

10

11

12

13

14

3

10

11

12

13

14

G

0

.

4

1

5

2

6

3

7

0

.

4

8

1

5

9

8

2

6

10

11

12

13

14

G

7

3

7

6

4

8

5

9

4

6

10

11

12

13

14

3

7

2

8

1

9

0

10

AGC Response

= Input(Cart/PolarGain)(Error Det Gain)(AGC Loop Gain

)(AGC Output Weighting).

Max

Min

Max

-0

= (1)(1.64676)(2 )(1)(0.75dB) ~ 1.23dB/symbol time.

-15

= (1)(1.64676)(2 )(1)(0.75dB) ~ 0.00004dB/symbol time.

Thus, the expected range for the AGC rate is ~ 0.00004 to 1.23dB/symbol time.

22

HSP50214

TABLE 10. POLYPHASE AND INTERPOLATING HALFBAND

FILTER MAXIMUM CLOCKING RATES

0

RESAM-

PLER

INPUT

RATE

(MHz)

-20

-40

INTER-

POLATION

RATE

OUTPUT

RATE

(MHz)

CLOCK

CYCLES

MODE

Bypass

-60

-80

0

6

35.00

-

28.00

Polyphase Filter

35/6

NCO ≤ 5.83

= 5.83

-100

-120

Polyphase and

1 Halfband Filter

13

23

7

35/13

= 2.69

2

4

2

4

NCO ≤ 5.38

NCO ≤ 6.09

10.00

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

Polyphase and

2 Halfband Filters

35/23

= 1.52

FREQUENCY (RELATIVE TO f

)

IN

1 Halfband Filter

35/7

= 5.00

FIGURE 24A. POLYPHASE RESAMPLER FILTER BROADBAND

FREQUENCY RESPONSE

2 Halfband Filters

17

35/17

8.24

= 2.059

10

0

POLYPHASE

HALFBAND

FILTER #1

HALFBAND

FILTER #2

-10

-20

-30

-40

-50

-60

-70

RESAMPLER

FILTER

RESAMPLER

NCO

PULSE

DELAY

PULSE DELAY

COUNTER

-80

0

PROCCLK

PROCCLK/N

FREQUENCY (RELATIVE TO f

)

IN

# EXTRA

PULSES

FIGURE 24B. POLYPHASE RESAMPLER FILTER PASS BAND

FREQUENCY RESPONSE

THIS BLOCK GENERATES EXTRA

DATA READY PULSES FOR THE

NEW OUTPUTS FROM THE

0

1

0

1

0

1

0

1

0

1

0

1

0

0 BYPASS

0

1

INTERPOLATION PROCESS.

2

1

3 (NV)

3

0

1

3

NV = INVALAID MODE

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

FIGURE 25. GENERATING DATA READY PULSES FOR OUTPUT

DATA

In burst systems (such as TDMA), time resolution is needed

for quickly identifying the optimum sample point. The timing

is adjusted by shifting the decimation in the DSP µP to the

closest sample. Use of timing error rate in this way may yield

a faster acquisition than a phase-locked loop coherent bit

synchronization. Finding the optimum sample point mini-

mizes intersymbol interference.

Fine time resolution is needed in CDMA systems to resolve

different multipath rays. In CDMA systems, the demands on

the programmable FIR can only be relieved by the Resam-

pler/interpolation halfband ﬁlters. Assume the chip rate for a

baseband CDMA system is 1.2288MHz and PROCCLK is lim-

ited to 35MHz. Using the symmetric ﬁlter pre-sum approach,

PROCCLK limits the programmable FIR to 70MIPS (millions

FREQUENCY (RELATIVE TO f

)

IN

FIGURE 24C. POLYPHASE RESAMPLER FILTER EXPANDED

RESOLUTION PASSBAND FREQUENCY

RESPONSE

23

HSP50214

of instructions per second) effective due to symmetry. If the trol (Control Word 11, bit 1), a Timing NCO Phase

CDMA ﬁlter (loaded into the programmable FIR section) Accumulator Load On Update control (Control Word 11, bit

requires an impulse response with a span of 12 chips, the ﬁl- 0), the Timing NCO Center Frequency (Control Word 12), a

ter at 2x the chip-rate would need 24 taps. The 24 taps would Timing Phase Offset (Control Word 13, bits 0-7), a Timing

translate into 59MIPS = (1.2288MHz)(2)(24). To get the same Frequency Strobe (Control Word 14) and a Timing Phase

ﬁltering at 8x the chip rate would require 944MIPS = Strobe (Control Word 15). Refer to the Carrier Synthesizer

(1.2288MHz)(8)(96). Direct 8x ﬁltering can not be accom- Mixer section for a detailed discussion of the serial interface

plished with the programmable ﬁlter alone because 944MIPS for the Timing NCO offset frequency word.

are much greater that the 60MIPs effective limit set by PROC-

A timing error detector is provided for measuring the phase

CLK. It is necessary to decimate down to 2x the chip rate to

difference between the timing NCO and a external clock input,

get a realistic number of ﬁlter taps. Both interpolation halfband

REFCLK. Timing Error is generated by comparing the values

ﬁlters are used to obtain an 8x CDMA output. The MIPS for

of two programmable counters. One counter is clocked with

the ﬁrst halfband equals (2.4576MHz)(Number of Multiplies

the Timing NCO carry out and the other is clocked by the

for ﬁrst halfband), and the second equal (4.9152MHz)(Num-

REFCLK. The 12-bit NCO Divide parameter is set in Control

ber of Multiplies for second halfband). Combined halfband ﬁl-

Word 18, bits 16-27. The NCO Divide parameter is the pre-

ters is equal to (1.2228MHz)(4)(48) = 236MIPS. Thus the

load to the counter that is clocked by the Timing NCO carry

MIPS are 18 and 25 for the ﬁrst and second halfbands respec-

out. The 12-bit Reference Divide parameter is set in Control

tively, and 42 for both.

Word 18, bits 0-11, and is the preload for the counter that is

clocked by the Reference clock. Figure 27 details the block

diagram of the timing error generation circuit. The 16 bits of

Timing NCO

timing error are available both as a PDC serial output and as a

The Timing NCO is very similar to the carrier NCO phase

processor read parameter. See the Processor Read Section

accumulator section. It provides the NCO driven sample pulse

for more details on accessing this value.

and associated phase information to the re-sampling ﬁlter pro-

cess described in the Resampler Filter section. The Timing

NCO does not include the SIN/COS section found in the Car-

rier NCO. The top level block diagram is shown in Figure 26.

TIMING

NCO

ACC

NCO DIVIDE†

(NCO DIVIDE)/2†

EN EXT TIMING NCO SYNC †

FILTER PHASE

SELECT

SYNC

SYNCIN2

-

12

TE(15:0)

TIMING PHASE STROBE †

5

PROGRAMMABLE

DIVIDER

CARRY OUT = RUN

FILTER STROBE

+

TIMING NCO

4

8

+

PHASE OFFSET †

REFERENCE

CLEAR

PHASE

DIVIDE†

PHASE

ACCUMULATOR

0

ACC †

EN

PROGRAMMABLE

DIVIDER

REG

+

MUX

REFCLK

TIMING NCO

PH ACC

LOAD ON

UPDATE†

† Controlled via microprocessor interface.

FIGURE 27. TIMING ERROR GENERATION

ENABLE SOF†

MUX

32

SCF

0

SOF

SYNC

REG

Figure 27A illustrates an application where the Timing Error

Generator is used to lock the receiver samples with a trans-

mit data rate. In this example, the receive samples are at

four times the transmit data rate. An external loop ﬁlter is

required, whose frequency error output is fed into the Timing

NCO. This allows the loop to track out the long term drift

between the receive sample rate and the transmit data clock.

REG

TIMING FREQ

STROBE †

SYNC

SHIFT REG

SOFSYNC

SOF

TIMING NCO CENTER

FREQUENCY†

NUMBER OF SOF BITS †

† Controlled via microprocessor interface.

FIGURE 26. TIMING NCO BLOCK DIAGRAM

The programmable parameters for the Timing NCO include

an Enable External Timing NCO Sync (Control Word 11, bit

5), the serial word width, Number of Offset Frequency Bits

(Control Word 11 bits 3-4), an Enable Offset Frequency con-

trol (Control Word 11, bit 2), a Clear NCO Accumulator con-

24

HSP50214

TABLE 11. MAG/PHASE BIT WEIGHTING

o

BIT

MAGNITUDE

PHASE ( )

LOOP

FILTER

2

15 (MSB)

2

Always 0

180

90

µP

1

14

2

0

13

2

45

TIMING

NCO

ACC.

-1

2

12

22.5

CLKIN/R

T

-2

2

11

11.25

(NCO DIVIDE)/2†

-3

2

10

5.625

NCO DIVIDE = 4N†

-4

2

-

9

2.8125

12

TE(15:0)

-5

2

PROGRAMMABLE

DIVIDER

8

1.40625

+

-6

2

4

7

0.703125

0.3515625

0.17578125

0.087890625

0.043945312

0.021972656

0.010986328

0.005483164

-7

2

6

REFERENCE

-8

2

DIVIDE = N†

5

EN

-9

2

4

T

DATA CLK

(REFCLK)

X

PROGRAMMABLE

DIVIDER

-10

2

3

-11

2

TO T BLOCK

X

(MODULATOR)

2

1

-12

2

R

= TOTAL DECIMATION (CIC, HB FILTERS AND FIR)

T

-13

2

0 (LSB)

† Controlled via microprocessor interface.

FIGURE 27A. TIMING ERROR APPLICATION

π/2

4000

+π/2

3fff

Cartesian to Polar Converter

3fff

4000

Q

The Cartesian to Polar converter computes the magnitude

and phase of the I/Q vector inputs. The I and Q inputs are

16 bits. The converter phase output is 18 bits (truncated)

with the 16 MSB’s routed to the output formatter and all 18

bits routed to the frequency discriminator. The 16-bit output

phase can be interpreted either as two’s complement (-0.5 to

approximately 0.5) or unsigned (0.0 to approximately 1.0),

as shown in Figure 28. The phase conversion gain is 1/2π.

The phase resolution is 16 bits. The 16-bit magnitude is

unsigned binary format with a range from 0 to 2.32. The

magnitude conversion gain is 1.64676. The magnitude reso-

lution is 16 bits. The MSB is always zero.

7fff

π

8000

7fff

±π

0000

0

ffff

0000

0

ffff

I

8000

c000

3π/2

c000

-π/2

bfff

FIGURE 28. PHASE BIT MAPPING OF COORDINATE

CONVERTER OUTPUT

The magnitude and phase computation requires 17 clocks

for full precision. At the end of the 17 clocks, the magnitude

and phase are latched into a register to be held for the next

stage, either the Output Formatter or frequency discrimina-

tor. If a new input sample arrives before the end of the 17

cycles, the results of the computations up until that time, are

latched. This latching means that an increase in speed

causes only a decrease in resolution. Table 12 details the

exact resolution that can be obtained with a ﬁxed number of

clock cycles up to the required 17. The input magnitude and

phase errors induced by normal SNR values will almost

always be worse than the Cartesian to Polar conversion.

Table 11 details the phase and magnitude weighting for the

16 bits output from the PDC.

25

HSP50214

TABLE 12. MAG/PHASE ACCURACY vs CLOCK CYCLES

PHASE INPUT

MAGNITUDE

ERROR

PHASE

ERROR

(DEG.)†

PHASE

ERROR

(% f )

S

PHASE MULTIPLIER †

CLOCKS

(% f )

S

6

0.065

0.016

3.5

1.8

2

DISCRIMINATOR DELAY †

DISCRIMINATOR EN †

DELAY

(1-8)

7

1

-

8

0.004

0.9

0.5

+

9

<0.004

0.45

0.25

0.12

0.062

0.03

0.016

0.008

0.004

0.002

0.001

10

11

12

13

14

15

16

17

0.22

FIR COEFFICIENTS †

DISC. FIR DECIMATION †

FIR SYMMETRY TYPE †

FIR SYMMETRY †

63-TAP

FIR

0.11

FILTER

0.056

0.028

0.014

0.007

0.0035

0.00175

FIR TAPS †

FREQ(15:0)

† Controlled via microprocessor interface.

FIGURE 29. FREQUENCY DISCRIMINATOR BLOCK DIAGRAM

The discriminator input is 18 bits, and the output is rounded

asymmetrically to 16 bits. The phase into the discriminator

o

† Assumes ±180 = f .

S

0

1

2

3

can be multiplied by 2 , 2 , 2 , or 2 (modulo 2π) to remove

PSK data modulation. All programmable parameters for the

Frequency Discriminator are set in Control Word 17. Bits 15

and 16 are the phase multiplier which represents the shift

applied to the input phase. For CW, the multiply should equal

Frequency Discriminator

The discriminator block delays phase from the Cartesian to

Polar section and subtracts it from the latest sample. This

delay and subtract can be modeled as a programmable

delay comb ﬁlter. The output of the ﬁlter is dθ/dt, or fre-

quency. The transfer function of the discriminator is set by

0

2 , (00). For BPSK, QPSK, and 8PSK, the multiply should

1

2

3

equal 2 , (01); 2 , (10); or 2 , (11); respectively. Bit 14 is

used to enable or disable the discriminator. Bits 11-13 set

the decimation in the programmable FIR ﬁlter. Bit 10 sets the

ﬁlter symmetry type as either odd or even, bit 9 sets whether

the ﬁlter is asymmetric or symmetric, and bits 3-8 set the

number of FIR ﬁlter taps. Bits 0-2 set the number of delays in

the frequency discriminator.

–D

H(z)= 1 – Z

(EQ. 21)

where D is the programmable discriminator delay expressed

in number of sample clock delays. The discriminator output

frequency is then ﬁltered with a programmable FIR ﬁlter. The

block diagram of the Frequency Discriminator is shown in

Figure 29.

Output Section

The output section routes the 7 types of processed signals to

output pins in three basic modes. These basic modes are:

Parallel Direct Output, Serial Direct Output, and the Buffer

RAM Output. The Serial and Parallel Direct Output modes

were designed to output data strobes and “real time” continu-

ous streams of data. The Buffer RAM Output mode outputs

data upon receipt of an asynchronous request from an exter-

nal DSP processor or other baseband processing engine. The

The range of delay in the discriminator is from 1 to 8 sam-

ples. Modulo 2π subtraction eliminates rollover problems in

the subtraction at 2π. The alias free discriminator frequency

range is given by:

Range

= CW ± F

⁄ (D + 1) ;

SAMPOUT

(EQ. 22)

FREQDISC

where D is the discriminator delay deﬁned in Equation 21 use of the interrupt signal from the Programmable Down Con-

(1 < D < 8), FSAMP is the Discriminator FIR ﬁlter output verter in conjunction with the request strobes from the control-

OUT

sample rate and CW is the desired center frequency. When ler ensures that data is transferred only when both the

0

the phase multiplier is set to a value other than 2 , the dis- controller and the Programmable Down Converter are ready.

criminator range is reduced proportionally. The phase multi- The Buffer RAM output can be operated in a First In First Out

0

3

1

plier can be 1, 2, 4 or 8 (2 to 2 ). Thus, a multiply of 2

(FIFO) or SNAPSHOT mode with the data output either via

2

reduces the range by 2, a multiply of 2 reduces the range the 8-bit processor interface or a 16-bit processor interface.

by 4, and a multiply of 2 reduces the range by 8.

3

The FIR ﬁlter can be conﬁgured with up to 63 symmetric taps

and up to 32 asymmetric taps. In the symmetric mode, the

FIR can be conﬁgured for even or odd symmetry, as well as

with an even or odd number of ﬁlter taps. Decimation is pro-

vided to allow more processing time for longer (i.e., more

taps) ﬁlter structures.

26

HSP50214

Parallel Direct Output Port Mode

AOUT DIRECT PAR

OUTPUT MODE

DATA SOURCE †

The Parallel Direct Output Port Mode outputs two 16-bit

words, AOUT and BOUT, of “real time” data. Figure 30

details the parallel output circuitry. Selection of the data

source for the AOUT and BOUT parallel outputs is done via

Control Word 20, bits 22-23, and 20-21, respectively. The

AOUT port can output I, Magnitude, or Frequency data. The

BOUT port can output Q, Phase or Magnitude data. The

upper bytes of AOUT and BOUT are always in the parallel

direct mode. The 16-bit parallel direct mode is selected by

setting Control Word 20, bit 25, to zero. The DATARDY out-

put is asserted during the ﬁrst clock cycle of new data on the

AOUT bus.

DATARDY

16

I

A(15:8)

A(7:0)

AOUT(15:8)

16

MAG

AOUT(7:0)

16

RAM(15:8)

FREQ

BOUT DIRECT PAR

OUTPUT MODE

DATA SOURCE †

16

Q

B(15:8)

B(7:0)

BOUT(15:8)

BOUT(7:0)

16

PHAS

16

RAM (7:0)

MAG

RAM (15:0)

DATA SOURCE FOR LSB †

† Controlled via microprocessor interface.

FIGURE 30A. PARALLEL OUTPUT BLOCK DIAGRAM

PROCCLK

I CHOSEN FOR AOUT

I

Q

DATARDY

R CHOSEN FOR AOUT

R

Q

DATARDY

(NOTE 1)

17 PROCCLK PERIODS

DATARDY

(NOTE 2)

FREQ CHOSEN FOR AOUT

T (NOTE 4)

FREQ

Q

DATARDY

(NOTE 3)

NOTES:

1. Computation preempted by new data.

2. Computation completes.

3. If decimation is selected, the DATARDY signal will occur at 1/Deci times the I/Q output sample rate.

4. T is equal to the number of PROCCLK cycles needed to compute the discriminator FIR plus the delay from I/Q to R/φ plus 6. The delay

will change depending on whether the Θ computation is preempted or not.

FIGURE 30B. TIMING FOR PARALLEL OUTPUT

NOTE: I and Q are sample aligned in time. |r| and φ are sample aligned in time, but one sample delayed from I or Q. The frequency

sample is delayed in time from I or Q by 1 sample time + 63 tap FIR impulse response. If the FIR is set to decimate and fre-

quencies selected for AOUT, the DATARDY signal will be at the documented rate.

27

HSP50214

TABLE 13. LINKING CONTROL WORDS FOR SERIAL OUTPUT

Serial Direct Output Port Mode

DATA TYPE

IDENTIFIER

The Serial Direct Output Port Mode offers the ability to construct

two serial output data streams, SEROUTA AND SEROUTB, from

16-bit I, Q, magnitude, phase, frequency, timing error, and AGC

level data words. The total number of data words (1 to 8) for serial

output, and the sequential order of these data word components

of the serial output are programmable. Each data word may be

used once in either the SEROUTA or SEROUTB data streams.

Figure 31 illustrates the conceptual implementation of the Serial

Direct Output Port Mode.

DATA TYPE

000

001

010

011

100

101

110

111

I Data

Q Data

Magnitude (MAG) Data

Phase (PHAS) Data

Frequency (FREQ) Data

Timing Error (TIMERR) Data

AGC Gain

In the Serial Direct Mode, the output data is loaded into serial shift

registers and routed to two serial output pins, SEROUTA and

SEROUTB. The serial output shift clock, SERCLK, is PROCCLK

divided by 1, 2, 4, 8, or 16. The divide down ratio is programmed

using Control Word 20, bits 14-16. The data is shifted out on the

rising edge of the internal SERCLK. The external clock polarity of

SERCLK is programmable via Control Word 20, bit 18. A sync sig-

nal is provided for detection of the start or end of each word in the

serial sequence. Control Word 20, Bit 17, sets the SERSYNC sig-

nal location as either preceding the MSB (typical for interfacing

with microprocessors) or following the LSB (typical for interfacing

to D/A converters). Control Word 20, bit 19, sets the SERSYNC

polarity as active low or high. The LSB of each data word can be

configured as either the true LSB data, or set at a fixed logic “1” or

“0” for use as a tag bit. Control Word 20 bits 0-13 set the LSB of

each of the 7 types of data words that can be configured in the

serial output stream. Control Word 19, bits 21-24 set the number

of serial data words that will be linked to form the serial outputs.

Up to 7 data words can be linked to form the serial output.

SEROUTA and SEROUTB will have an identical number of words

in the serial output streams.

Zeros

Two examples will illustrate the process of configuring a serial

output using the Serial Output mode.

Serial Output Conﬁguration Example 1:

It is desired to output the I data word, followed by the Q data

word, followed by the Phase data word on the SEROUTA output.

Similarly, it is desired to output the Magnitude data word followed

by the Frequency data word, followed by the Timing Error data

word, followed by the AGC Level data word on the SEROUTB out-

put. Table 14 illustrates how Control Word 19 should be pro-

grammed.

TABLE 14. EXAMPLE 1 SERIAL OUTPUT CONTROL SETTINGS

CONTROL

WORD 19

BIT POSITION

BIT

VALUE

FUNCTION

RESULT

(I)

The 16-bit I, Q, magnitude, phase, frequency, timing error, AGC

level, and “zeros” data words for are loaded into their respective

shift registers. The Magnitude and AGC Level data word are

unsigned binary format with a leading zero, while the remaining

signals are 2’s complement format.

30-28

27-25

24-21

SEROUTA Data Source

SEROUTB Data Source

000

010

100

(|r|)

Number of Serial Word

Links in a Chain

(4)

Any of the eight data sources can be selected as the first serial

word for SEROUTA or SEROUTB. Control Word 19, bits 25-30

set the data type for the first serial word for SEROUTA and

SEROUTB. The three bit data type identifier is shown both in

Table 13 and in Figure 30, to the right of the controls for the cross

matrix switch. Serial output data word sequences are formed by

linking data words by programming the data source for each shift

requester’s shift input signal. This programming links the shift reg-

isters together in one or two serial chains. Thus the Control Word

19 term “Link follows X data”, where X is one of the seven data

types. Once the data source data word is selected (by program-

ming a three bit word representing one of the data types into Con-

trol Word 19, bits 25-27 (SEROUTA), and 28-30 (SEROUTB)), the

process for identifying the next word is to select a three bit data

type identifier which represents the data type to follow the source

data type. Program these bits into the Control Word 19 field repre-

senting the “Link following X data”, where X = the source data

type, defines the second word in the sequence. Likewise, the third

data word is linked by selecting the Control Word 19 bits that

identify the “Link following X data”, where X = the data type of the

second word in the serial chain. The process continues until all

the desired data words have been linked.

20-18

17-15

14-12

11-9

8-6

Link following I data

Link following Q data

Link following |r| data

Link following φ data

Link following f data

Link following AGC data

001

011

100

111

101

XXX

110

(Q)

(φ)

(f)

(Zeros)

(Timing)

(N/A)

(AGC)

5-3

2-0

Link following Timing

Error data

NOTE: Because all but the first data word in the serial output

is identified by the data type that it follows, SEROUTB

can only be fully independent of the sequence in SE-

ROUTA if it does not use any of the same data word

types. This implies a partition as described in Example

1. Once a data word that is used in SEROUTA is called

out in SEROUTB, the remaining sequence in SEROUTB

will be identical to that portion of SEROUTA sequence

that follows the duplicate data type. This follows from

using the “Link follows ‘data type’ data” for word link-

age.

NOTE: Each type of data word should be used only once in

each data stream. If the “Link following I data” is pro-

grammed with the data type identifier for I, then the

part will repeat the I data word until all of the data word

locations are filled. In Example 1, if bits 20-18 were er-

roneously programmed to 000 (I data) then the SEROU-

TA would be four sequential repeats of the I data word.

NOTE: I and Q are sample aligned in time. |r| and f are sample

aligned in time, but one sample delayed from I or Q.

The frequency sample is delayed in time from I or Q by

1 sample time + 63 tap FIR impulse response. If the FIR

is set to decimate, the FIR output will be repeated every

sample time until a new value appears at the filter out-

put. (i.e., the frequency samples are clocked out at the

I, Q sample rate regardless of decimation.)

28

HSP50214

The serial data stream looks like:

SEROUTA:

start

CONTROL WORD 19 FIELD

SEROUTB:

CONTROL WORD 19 FIELD

start

I data word >

Q data word >

φ data word >

Zero data word >

end >

SEROUTA source data = 000

Link following I data = 001

Link following Q data = 011

Link following φ data = 111

|r| data word >

f data word >

TE data word>

AGC data word >

end >

SEROUTB source data = 010

Link following |r| data = 100

Link following f data = 101

Link following TE data = 110

I DATA SERIAL OUTPUT TAG BIT †

Q DATA SERIAL OUTPUT TAG BIT †

MAGNITUDE DATA SERIAL OUTPUT TAG BIT †

PHASE DATA SERIAL OUTPUT TAG BIT †

FREQUENCY DATA SERIAL OUTPUT TAG BIT †

TIMING ERROR DATA SERIAL OUTPUT TAG BIT †

AGC DATA SERIAL OUTPUT TAG BIT †

XXX

000

001

010

011

100

101

110

111

SOURCE

I

DATA SOURCE FOR SEROUTA †

LINK FOLLOWING I DATA †

Q

MAG

LINK FOLLOWING Q DATA †

PHASE

FREQUENCY

TIMING ERROR

AGC

LINK FOLLOWING MAG DATA †

LINK FOLLOWING PHASE DATA †

LINK FOLLOWING FREQ DATA †

LINK FOLLOWING TIMING DATA †

LINK FOLLOWING AGC DATA †

ZERO

FOLLOWS I

SHIFT REG

I (15:0)

SHIFT REG

FOLLOWS Q

SHIFT REG

Q (15:0)

|r| (15:0)

φ (15:0)

FOLLOWS |r|

SHIFT REG

CROSS

MATRIX

SWITCH

FOLLOWS φ

CROSS

MATRIX

SWITCH

SHIFT REG

FOLLOWS f

f (15:0)

SHIFT REG

FOLLOWS TE

SHIFT REG

TE

(15:0)

SHIFT REG

FOLLOWS AGC

SHIFT REG

AGC

(15:0)

SHIFT REG

SEROUTA

SOURCE

ZERO

6

5

4

3

2

1

0

SHIFT REG

SERIAL OUTPUT SHIFT REGISTER

MUX

DATA SOURCE FOR SEROUTB †

SEROUTA

SEROUTB

SOURCE

5

4

3

2

1

0

PROGRAMMABLE

DIVIDER

SERIAL OUTPUT SHIFT REGISTER

PROCCLK

SEROUTB

^{NUM OF SER WORD LINKS IN A CHAIN}†

‡

SERIAL OUT CLOCK DIVIDER †

SERIAL OUTPUT SYNC POSITION †

SERIAL OUTPUT CLOCK POLARITY †

SERIAL OUTPUT SYNC POLARITY †

SERCLK

SERSYNC

‡

† Controlled via microprocessor interface

‡ Polarity is programmable

FIGURE 31. SERIAL OUTPUT FORMATTER BLOCK DIAGRAM

29

HSP50214

Serial Output Conﬁguration Example 2:

SEROUTB:

CONTROL WORD 19 FIELD

It is desired to output only three data words on each serial out-

put. The I data word, followed by the Q data word, followed by

the Magnitude data word is to be output on SEROUTA. The Q

data word followed by the Magnitude data word, followed by

the one other data word to be output on SEROUTB. The

choices for the remaining data word in the SEROUTB signal

are: phase, frequency, AGC level and timing error. Table 15

illustrates how Control Word 19 should be programmed.

start

Q data word >

|r|data word >

TBD data word>

end >

SEROUTB source data = 001

Link following Q data = 010

Link following |r| data = TBD

As shown by this example, once Q was linked to |r| in the

SEROUTA chain, the SEROUTB chain must have |r| follow-

ing Q, if Q is selected. Figure 32 illustrates the construction

of the serial output streams. If the serial data stream was

changed to be a length of four data words, then, by default,

the SEROUTA would be whatever is selected for SEROUTB

data word 3. SEROUTB would need to identify the fourth

data word. Thus, SEROUTA and SEROUTB are not fully

independent because they share the Q data word (and by

default, the MAGNITUDE follows Q data link and whatever is

selected for data word 3 to follow MAGNITUDE data in

SEROUTB).

TABLE 15. EXAMPLE 2 SERIAL OUTPUT CONTROL SETTINGS

CONTROL

WORD 19

BIT

BIT POSITION

FUNCTION

VALUE

RESULT

(I)

30-28

27-25

24-21

SEROUTA Data Source

SEROUTB Data Source

000

001

011

(Q)

Number of Serial Word

Links in a Chain

(3)

20-18

17-15

14-12

11-9

8-6

Link following I data

Link following Q data

Link following |r| data

Link following φ data

Link following f data

Link following AGC data

001

010

(Q)

(|r|)

The other signals provided with the SEROUTA and

SEROUTB are the SERSYNC and the SERCLK. The

SERSYNC signal can be programmed in either early or late

sync mode. The sync signal is pulsed active low or active

high for each information word link of the chain of data cre-

ated using control word 19. Figure 33 shows the four possi-

ble conﬁgurations of SERSYNC as programmed using

Control word 20.

TBD

XXX

TBD

(N/A)

5-3

2-0

Link following Timing

Error data

The serial data stream looks like:

As previously discussed, Control Word 20, bits 17 and 19,

set the functionality of the LSB of each data word. These bits

may be programmed to be either a logic “0”, logic “1” or as

normal data. The ﬁxed states are designed to allow the

microprocessor to synchronize to the serial data stream.

SEROUTA:

CONTROL WORD 19 FIELD

start

I data word >

Q data word >

|r|data word >

end >

SEROUTA source data = 000

Link following I data = 001

Link following Q data = 010

CONTROL WORD 19 BITS 24-21 = 011

(3 DATA WORDS IN EACH SERIAL OUTPUT)

DATA WORD 3

MAGNITUDE

DATA WORD 2

Q

DATA WORD 1

I

SEROUTA

SEROUTB

DATA WORD 3

TBD

DATA WORD 2

MAGNITUDE

DATA WORD 1

Q

THE REMAINING CHOICES FOR THE THIRD LINK ON SEROUTB ARE:

PHASE, FREQUENCY, AGC LEVEL, AND TIMING ERROR

NOTE: Once magnitude is identiﬁed to follow Q,

it must be that way on both serial outputs.

FIGURE 32. EXAMPLE 2 SERIAL OUTPUT DATA STREAM

30

HSP50214

“NORMAL”

0

1

2

LATE

SERSYNC

MODE

SERSYNC FOLLOWS LSB

“INVERTED”

“NORMAL”

1

2

3

EARLY

SERSYNC

MODE

SERSYNC PRECEDES MSB

MSB WORD1

“INVERTED”

LSB WORD0

MSB WORD2

MSB WORD3

0

2

1

0

15

14

• • •

2

1

15

14

• • •

2

1

15

14

• • •

2

DATA SHIFT MSB FIRST

LSB WORD2

LSB WORD1

FIGURE 33. VALID SERSYNC CONFIGURATION OPTIONS

Buffer RAM Output Port

The Buffer RAM parallel output mode utilizes a RAM to store The FIFO mode allows the processor to service the interface

output data for future retrieval by either the 8-bit microproces- only when enough samples are present in the RAM. This

sor that is conﬁguring the PDC or by a 16-bit baseband pro- mode is provided so that the µProcessor does not have to

cessing engine (which could also be a microprocessor). Data service the PDC every output sample. An interrupt,

is output from the RAM only on request and can be obtained INTRRPT, is asserted when the desired number of samples

from either the 8-bit µP interface or from a 16-bit interface that are available. The PDC can be programmed to assert the

uses the two LSBytes of AOUT and BOUT. The RAM holds up interrupt when up to 7 samples are available. Control Word

to eight 80-bit sample sets. Each sample set includes 16 bits 21 bit 15 is used to set the Buffer RAM controller to the FIFO

of each I, Q, magnitude, phase, and frequency data. The mode, while Control Word 21, bits 12-14 set the number of

RAM samples are mapped as shown in Table 16. The Buffer RAM samples to be stored (0 to 7) before the interrupt

RAM controller supports both FIFO and Snapshot modes.

(INTRRPT) is asserted. Control Word 20 bit 24 determines

whether the RAM output interface is the 8-bit microprocessor

interface or the 16-bit processor interface. In the 16-bit inter-

face the MSByte is sent to AOUT(7:0) while the LSByte is

sent to BOUT(7:0).

TABLE 16. RAM DATA STORAGE MAP

RAM

SAMPLE

SET

I

Q

DATA

(001)

|r|

DATA

(010)

Φ

DATA

(011)

F

DATA

(000)

DATA

(100)

The INTRRP output signal goes low for 8 PROCCLK cycles

when the number of samples in the Buffer RAM (depth)

reaches the programmed depth. The depth of the RAM is

calculated using Equation 23. A DSP microprocessor or the

data processing engine can use the INTRRP signal to know

that the RAM is ready to be read.

0

1

2

3

4

5

6

7

I (15:0) Q (15:0) |r| (15:0) φ (15:0) f (15:0)

0 0 0 0 0

I (15:0) Q (15:0) |r| (15:0) φ (15:0) f (15:0)

1

I (15:0) Q (15:0) |r| (15:0) φ (15:0) f (15:0)

2

I (15:0) Q (15:0) |r| (15:0) φ (15:0) f (15:0)

3

D

= [(ADDR

– ADDR

) – 1]

READ MOD8

(EQ. 23)

I (15:0) Q (15:0) |r| (15:0) φ (15:0) f (15:0)

RAM

WRITE

4

I (15:0) Q (15:0) |r| (15:0) φ (15:0) f (15:0)

5

I (15:0) Q (15:0) |r| (15:0) φ (15:0) f (15:0)

FIFO Operation via 16-Bit µProcessor

Interface

6

I (15:0) Q (15:0) |r| (15:0) φ (15:0) f (15:0)

7

Figure 34 shows the conceptual conﬁguration of the 16-bit

µProcessor interface. This interface looks like a 16-bit µPro-

cessor read-only microprocessor interface. The SEL(2:0)

lines are the address bus and the OEAL and OEBL lines are

the read lines. The address is decoded as shown in

Table 17.

NOTE: I and Q are sample aligned in time. |r| and φ are sample

aligned in time, but one sample delayed from I or Q. The

frequency sample is delayed in time from I or Q by 1

sample time + 63 tap FIR impulse response. If the FIR is

set to decimate, the FIR output will be repeated every

sample time until a new value appears at the filter output.

(i.e., the frequency samples are clocked out at the I, Q

sample rate regardless of decimation.)

Use of the 16-bit interface for Buffer RAM output requires

Control Word 20, bit 25, to be set to a logic “0” and Control

Word 20, bit 24, to be set to a logic “1”. Once the Control

31

HSP50214

TABLE 18. STATUS BIT DEFINITIONS

AOUT BIT

Word 20 has been set to route data to AOUT(7:0) and

BOUT(7:0), then the microprocessor must place a value on

the PDC input pins SEL(2:0), to choose which data type will

be output on AOUT(7:0) and BOUT(7:0). Table 17 deﬁnes

the data types in terms of SEL(2:0). With the control lines

set, the selected data is read MSByte on AOUT(7:0) and

LSByte on BOUT(7:0) when OEAL and OEBL (are low).

New data only read when OEBL goes low, so use µP for 8-

bit modes. Programming SEL(2:0) = 110 outputs a 16-bit

status signal on AOUT and BOUT. The FIFO status includes

FULL, EMPTY, FIFO Depth, and READYB. These status sig-

nals are deﬁned in Table 18.

LOCATION

INFORMATION

(7:5)

FIFO depth - When in FIFO mode, these bits

are the current depth of the FIFO.

4

3

2

EMPTY - When in FIFO mode, the FIFO is

empty, and the read pointer cannot be ad-

vanced. Active High.

FULL - When in FIFO mode, the FIFO is full,

and new samples will not be written.

Active High.

I

0

1

2

3

4

16

READYB - When in FIFO mode, the output buff-

er has reached the programmed threshold. In

the snapshot mode, the programmed number

of samples have been taken. Active Low.

I

Q

|r|

Q

|r|

φ

ƒ

DUAL

PORT

RAM

OUTPUT

DATA

φ

ƒ

STATUS 6

1-0

GND

OEBL

“SET OF WORDS”

ADDRESS

SEQUENCER

WRITE

SEQUENCER

SEL(2:0)

NOTE: In the Status output, BOUT(7:0) are all GND.

INCR

WR

INCR

RD

Figure 35 shows the interface between a 16-bit microproces-

sor (or other baseband processing engine) and the Buffer

RAM output section of the Programmable Down Converter,

conﬁgured for data output via the parallel outputs AOUT and

BOUT. In the 16-bit microprocessor interface conﬁguration,

the Buffer RAM pointer is incremented when the µProcessor

reads address SEL(2:0) = 7 and OEBL = 0.

NEW

DATA

PROCCLK

FIGURE 34. 16-BIT MICROPROCESSOR INTERFACE

BUFFER RAM MODE BLOCK DIAGRAM

After reset, the FIFO must be incremented to read the ﬁrst

sample set. This is because the RAM read and write pointers

cannot point to the same address. Thus, the FIFO pointer

must move to the next address before reading the next set of

data (I, Q, |r|, φ, and f) samples. 4 PROCCLK cycles are

required after an increment before reading can resume. The

FIFO write pointer is reset to zero (the ﬁrst data sample) when

Control Word 22 is written to via the 8-bit microprocessor

interface. See the Microprocessor Read Section for more

detail on how to obtain the Buffer RAM output with this tech-

nique. Figure 36 shows the timing diagram required for paral-

lel output operations. In this diagram, only the I, Q and

Frequency data are taken from each sample before incre-

menting to the next sample. Figure 36 assumes that the

pointer has already been incremented into a sample.

TABLE 17. BUFFER RAM OUTPUT SELECT DEFINITIONS

SEL(2:0)

000

OUTPUT DATA TYPE

I Data

001

Q Data

010

Magnitude

Phase

011

100

Frequency

Unused

101

NOTE: For the very first sample read, the pointer must be incre-

mented first and 4 PROCCLKs must pass before this

sample can be read.

110

Memory Status

111

Reading this address increments to the next

sample set

Figure 36 shows INTRRP going low before the FIFO is read.

The FIFO can be read before the number of samples

reaches the INTRRP pointer. The number of samples in the

FIFO must be monitored by the user via a status read.

32

HSP50214

READ

INTRRP

OEAL

INT

PDC

6

3

7

2

RD

5

4

0

1

D(15:8)

FIFO

DEPTH

AOUT(7:0)

OEBL

16-BIT

µP

WRITE

D(7:0)

A(2:0)

BOUT(7:0)

SEL(2:0)

A: FIFO DEPTH IS (WRITE - READ)

WRITE

FIGURE 35. INTERFACE BETWEEN A 16-BIT MICROPROCES-

SOR AND PDC IN FIFO BUFFER RAM MODE

6

3

7

2

READ

5

4

0

1

8 CLKS

INTRRP

> 4 CLKS

OEAL,

OEBL

B: FIFO FULL IS WHEN (WRITE - READ) = 7

READ

SEL(0:2)

0

1

4

7

0

I

1

AOUT(7:0),

BOUT(7:0)

I

Q

FR

Q

6

3

7

2

WRITE

1

2

3

4

5

6

7

8

1 2 3 4

5

4

0

1

PROCCLK

FIGURE 36. TIMING DIAGRAM FOR PDC IN FIFO MODE WITH

OUTPUTS I, Q, AND FREQUENCY SENT TO

AOUT(7:0) AND BOUT(7:0)

C: FIFO EMPTY IS WHEN (WRITE - READ) = 1

READ

Suppose the depth of the Buffer RAM Output section is pro-

grammed for an INTRRP pointer depth of 4. If the output is at 4

times the baud rate, the processing routine for the microprocessor

may only need to read the buffer when the Buffer RAM had 4

samples since processing is usually on a baud by baud basis.

6

7

5

4

0

1

Figure 37 illustrates the conceptual view of the FIFO as a circular

buffer, with the Write address one step ahead of the read

address.

WRITE

3

2

Figure 37A deals with clockwise read and write address incre-

menting. The FIFO depth is the difference between the Write and

Read pointers, modulo 8. Figure 37B illustrates a FIFO status of

Full, while Figure 37C illustrates a FIFO empty status condition.

Figure 37D illustrates a programmed FIFO depth of 3 and the

INTRRP signal indicating that the buffer has sufficient data to be

read.Following some simple rules for operating the FIFO will elim-

inate most operational errors:

READY

D: FIFO READY IS WHEN (WRITE - READ) > DEPTH

FIGURE 37. FIFO REGISTER OPERATION

Rule #4: You cannot write over what you have not read.

Rule #5: RESET places the Write address pointer = 000 and

Read address pointer = 111.

Rule #1: The Read and Write Pointers cannot point at the same

address (the circuitry will not allow this).

Rule #2: The FIFO is full when the Write Address = Read

Address -1 (no more data will be written until some samples are

read or the FIFO is reset).

Rule #6: The best addressing scheme is to read the FIFO until it

is empty. This avoids erroneous INTRRP assertions and provides

for simple FIFO depth monitoring. The interrupt is generated

when the depth increments past the threshold.

Rule #3: The FIFO is empty when the Read Address = (Write

Address -1) (the circuitry will not allow the read pointer to be

incremented).

33

HSP50214

Recall that INTRRP stays low for 8 PROCCLK cycles. The

FIFO Operation via 8-Bit µProcessor

Interface

FIFO can be read before the INTRRP signal goes low; the

number of samples in the FIFO must be monitored by the user.

Figure 38 illustrates the timing for RAM load sequence.

The Buffer RAM Output may also be accessed via the 8-bit

microprocessor interface C(7:0). Figure 39 shows the con-

ceptual conﬁguration of the 8-bit µprocessor interface. Con-

trol Word 20 bit 24 must be set to 0 in order to obtain Buffer

RAM data to this output. The Microprocessor Read section

describes how to read the data from each sample out of the

C(7:0) interface.

The read pointer of the FIFO is incremented when Control

Word 23 is written to. The data can not be read from the

next sample until 4 PROCCLKs after the Buffer RAM

pointer has been incremented. Control Word 22 is used to

reset the Read and Write pointers of the Buffer RAM output

to the ﬁrst sample to 000 and 007 for write and read

respectively.

PROCCLK

I/Q

R/φ

DELAY TO DATARDY DEPENDS ON LENGTH OF FIR IF FREQ CHOSEN

DATARDY

(I/Q SELECTED)

DATARDY

(R/φ SELECTED)

INTRPT

WRITES TO

SNAPSHOT

RAM

φ

ƒ

I

Q

R

FIGURE 38. RAM LOAD SEQUENCE

I

0

16

I

Q

|r|

R2 R1 R0 A2 A1 A0 SELECTION

Q

1

2

3

4

DUAL

PORT

RAM

0

1

X

0

1

0

1

X

0

1

0

1

0

1

X

0

X

0

X

1

0

1

0

1

0

X

0

1

0

1

X

1

0

1

0

1

0

1

0

1

0

1

X

0

1

0

1

0

1

X

1

RAM I LSB

|r|

0

φ

RAM I MSB

RAM Q LSB

RAM Q MSB

RAM |r| LSB

RAM |r| MSB

RAM φ LSB

φ

ƒ

LSByte

0

ƒ

R1 R0 A1

0

1

“SET OF WORDS”

ADDRESS

WRITE

SEQUENCER

STATUS

1

SEQUENCER

R2

1

INCR

WR

INCR

RD

RAM φ MSB

RAM ƒ LSB

MSByte

A0

OUTPUT

DATA

RAM ƒ MSB

NOT USED

NEW

DATA

INPUT INTEG LSB

INPUT INTEG NMSB

INPUT INTEG MSB

AGC LSB

CONTROL

WORD 23

0

1

INT(15:0)

WRITE

A(2:0)

INT(22:16)

R2, R1, R0

A2, A1, A0

ADDRESS “5”

A2 A1 A0

2

3

AGC

AGC MSB

0: I;Q

1: |r|; φ

2: ƒ

TIMING

TIMING LSB

TIMING MSB

NOT USED

R0 A1

4: INPUT AGC

5: AGC; TIMING

STATUS

RD

FIGURE 39. 8-BIT MICROPROCESSOR INTERFACE BUFFER RAM MODE BLOCK DIAGRAM

34

HSP50214

Snap Shot Operation

INTRRP

The snapshot mode takes sets of adjacent samples at pro-

grammed intervals. It is provided for tracking algorithms that

do not require processing of every sample, but do require

sets of adjacent samples. For example, bit sync algorithms

have narrow loop bandwidths that may not need to be

updated every sample. Computing the bit phase may require

4 adjacent samples at 2 times the baud rate. The snapshot

mode allows the processor to implement the tracking algo-

rithms for high speed data without having to handle every

data sample.

TIME

RD

WR

RD

WR

A COMPLETE SET OF 3 DATA SAMPLES IS IN MEMORY AT INTRRP

A: NORMAL READ/WRITE SEQUENCE

The interval from the start of one snapshot to the start of a

second snapshot is programmed into bits 11-4 (where bit 11

is the MSB) of Control Word 21. The actual interval is the

value programmed plus 1. If bits 11-4 = 11111111, then the

interval is set to 256. If sample sets are to be taken every 4

samples, then bits 11-4 = 00000011.

INTRRP

Figure 40 shows the relationship between the snapshot

samples and the snapshot interval.

TIME

RD

WR

RD

WR

ADJACENT

SAMPLES

THE THIRD INTERRUPT HAS ONLY 1 NEW DATA ENTRY

(INSTEAD OF 3) AT INTRRP

B: FALSE TRIGGERED INTERRUPT READ/WRITE SEQUENCE

FIGURE 41. AVOIDING FALSE INTRRP ASSERTIONS

64

65

0

1

2

3

4

62

63

# SAMPLES = 4

INTERVAL = 64

Microprocessor Write Section

FIGURE 40. SNAP SHOT SAMPLING

The microprocessor write section uses an indirect

addressing scheme where a 32-bit data word is ﬁrst loaded

in a four 8-bit byte master registers using four writes via

C(7:0). The desired destination register address is then writ-

ten to another address using C(7:0). Writing this address

triggers a circuit that generates a pulse, synchronous to

clock, that loads the destination register. The sync circuits

and data words are synchronized to different clocks, CLKIN

or PROCCLK, depending on the destination registers.

The PDC begins to ﬁll the buffer each time an interval num-

ber of samples have passed. The number of sample sets the

PDC writes into the buffer is programmed into bits 3-0 of

Control Word 21. The number of samples stored is the pro-

grammed value and may be from 1 to 8 sample sets. A sam-

ple set consists of I, Q, |r|, φ and ƒ.

In snap shot operations, the buffer is read the same as for

FIFO operations. Figures 34 and 36 describe the block and

timing diagrams required to output data on AOUT(7:0) and

BOUT(7:0). Table 17 summarizes the selectable output sig-

nals. The method for reading data through the microproces-

sor section in snap shot mode is identical to the method

described in the FIFO mode subsection and the Micropro-

cessor Read Section.

A(2:0) determines the destination for the data on bus,

C(7:0). Table 19 shows the address map for microproces-

sor interface. Figure 42 shows the control register loading

sequence. The data in C(7:0) and address map in A(2:0) is

loaded into the PDC on the rising edge of WR and is

latched into the master register on the rising edge of WR

and A(2:0) = 100. Four clocks must pass before loading the

next control word to guarantee that the data has been

transferred.

Avoiding Timing Pitfalls When Using the Buffer RAM

Output Port

Some registers can be loaded (i.e., transferred from the

master register to a conﬁguration register or from a holding

register to an active register) by initiating a sync. For exam-

ple, to load the AGC Gain, the value of the AGC gain is ﬁrst

loaded into the holding registers, then a transfer is initiated

by SYNCIN2 if Control Word 8, bit 29 = 1. This allows the

AGC gain to be loaded by detecting a system event, such as

a start of a new burst. Bit 20 of Control Word 0 has the same

effect on the Carrier NCO center frequency for assertion of

SYNCIN1, except it transfers from a dedicated holding regis-

ter - not the master register.

In snapshot mode, the whole buffer is written whenever the

interval counter has timed-out. After time-out, old data can

be written over. Thus, the data contained within the buffer

must be retrieved before time-out to avoid data loss.

It may be desirable to disable the INTRRPT into the control-

ling microprocessor during read cycles to avoid the generat-

ing extra interrupts. Figure 41 details how the WRITE

address can trigger extra interrupts Care must be taken to

either read sufﬁcient data out of memory or RESET the

addressing to ensure that a complete set of data is the

cause of the interrupt.

35

HSP50214

Microprocessor Read Section

TABLE 19. DEFINITION OF ADDRESS MAP

REGISTER DESCRIPTION

A2-0

The microprocessor read uses both read and write proce-

dures to obtain data from the PDC. A write must be done to

location 5 to select the source of data to be read. The read

source is determined by the value placed on the lower three

bits of C(7:0). The output from a particular read code is

selected using a read address placed on A(2:0). The output

is sent to C(7:0) on the falling edge of RD.

0

Holding Register 0. Transfers to bits 7-0 of the 32-bit des-

tination register. Bit 0 is the LSB of the 32-bit register.

1

2

3

4

Holding Register 1. Transfers to bits 15-8 of a 32-bit desti-

nation register.

Holding Register 2. Transfers to bits 23-16 of a 32-bit des-

tination register.

If the Read Address is equal to 111, the Read Code is

ignored, and the status bits shown in Table 22 in the Output

Section is sent to C(7:0). This state was provided so that the

user could obtain the status bits quickly.

Holding Register 3. Transfers to bits 31-24 of a 32-bit des-

tination register. Bit 31 is the MSB of the 32-bit register.

This is the destination address register. On the fourth CLK

following a write to this register, the contents of the holding

registers are transferred to the destination register. All 8

bits written to this register are decoded into the destination

register address. The conﬁguration destination address

map is given in the tables in the Control Word section.

Refer to the timing diagram in Figure 43. Suppose the input

level detector has a hex value of (321AF5)H, then Table 21

details the steps to be taken.

PROCLK

5

Selects data source for reading. See Microprocessor Read

Section.

WR

RD

Suppose a (0018D038)H needs to be loaded into control word

0, then Table 20 details the steps to be taken.

A2-0

C7-0

5

READ ADDRESS

OUTPUT DATA C(7:0)

TABLE 20. EXAMPLE PROCESSOR WRITE SEQUENCE

STEP

A(2:0)

C(7:0)

COMMENT

READ CODE C(2:0)

LOAD ADDRESS

OF TARGET

CONTROL REGISTER

ASSERT RD

TO ENABLE DATA

OUTPUT ON C0-7

1

000

0011 1000 Loads 38 into master register

(7:0) on rising edge of WR

THREE-STATE

INPUT BUS

2

3

4

5

6

001

010

011

100

1101 0000 Loads D0 into master register

(15:8) on rising edge of WR

FIGURE 43. READING THE CONTROL REGISTERS USING A

LATCH CODE EQUAL TO A 5, A READ ADDRESS

AND A READ CODE

0001 1000 Loads 18 into master register

(23:16) on rising edge of WR

0000 0000 Loads 00 into master register

(31:24) on rising edge of WR

TABLE 21. PROCESSOR READ SEQUENCE (INPUT LEVEL

SETECTOR)

0000 0000 Load “0018D038” into Conﬁgu-

ration Control Register 0

STEP

A(2:0)

C(7:0)

COMMENT

Wait 4 CLKS

1

101

100

Write Read Code, 100 to

Address 5, WR pulled high to

generate rising edge.

1

4

2

3

CLK =

(PROCCLK,

CLKIN)

2

3

4

000

001

010

1111 1000 Drop RD low, Read AGC

(F4)H LSB

WR

0001 1010 Pull RD high, then drop low,

(1A)H Read AGC NLSB

A2-0

0

1

2

3

4

0

2

0011 0010 Pull RD high, then drop low,

(32)H Read AGC MSB

C7-0

LSB

MSB ADD

LOAD

CONFIGURATION

DATA

LOAD ADDRESS OF

TARGET CONTROL

REGISTER AND

WAIT 4 CLKs

LOAD NEXT

CONFIG-

URATION

REGISTER

FIGURE 42. LOADING THE CONTROL REGISTERS WITH

32-BIT CONTROL WORDS

36

HSP50214

Applications

TABLE 22. DEFINITION OF ADDRESS MAP

STATUS

READ

Composite Filter Response Example

CODE C2-0

TYPE

READ ADDRESS A(2:0)

For this example consider a total receive band roughly

25MHz wide containing 124 200kHz wide FDM channels as

shown in Figure 44. The design goal for the PDC is to tune to

and ﬁlter out a single 200kHz FDM channel from the FDM

band, passing only baseband samples onto the baseband

processor at a multiple of the 270.8 KBPS bit rate.

0

Buffer

000- I LSB

RAM I and 001- I MSB

Q

010- Q LSB

011- Q MSB

See Output Section.

1

2

Buffer

RAM

Output

000- MAG LSB (7-0)

001- MAG MSB (15-8)

010- PHASE LSB (7-0)

124 CHANNELS

(|r| and φ) 011- PHASE MSB (15-8)

See Output Section.

•

• •

Buffered

000- FREQ LSB

Frequency 001- FREQ MSB

See Output Section.

FREQUENCY

3

4

Not Used

200kHz

CHANNEL

Input Level Input AGC

Detector

000- input AGC LSB (0-7)

001- input AGC NLSB (8-15)

010- input AGC MSB (16-23)

5

AGC Data AGC (must write to location 10 to sample)

andTiming 000- AGC LSB (lower 8 bits of linear

Error

control word 3 used by multiplier)

mmmmmmmm LSB

001- AGC MSB (4 shift control bits and

first three bits of linear) control word

oeeeemmm MSB. This yields 11 bits of

the linear control mantissa.

010- Timing error LSB, Not stabilized.

011- Timing error MSB, Not stabilized.

FREQUENCY

FIGURE 44. RECEIVE SIGNAL FREQUENCY SPECTRUM

RF/IF Considerations

6

7

Not Used

The input frequency to the PDC is dependent on the A/D

converter selected, the RF/IF frequency, the bandwidth of

interest and the sample rate of the converter. If the A/D con-

verter has sufﬁcient bandwidth, then undersampling tech-

niques can be used to downconvert IF/RF frequencies as

part of the digitizing process, using the PDC to process a

lower frequency alias of the input signal.

Don’t Care Status

111- Status (6:0) consisting of

(6:4)-FIFO depth when output is in FIFO

Buffer RAM Output Mode

(3)-EMPTY signalling the FIFO is empty

and the read pointer cannot be ad-

vanced (Active High)

For example, a 70MHz IF can be sampled at 40MHz and the

resulting 10MHz signal alias can be processed by the PDC

to perform the desired downconversion/tuning and ﬁltering. If

the IF signal is less than 1/2 the sample frequency then stan-

dard oversampling techniques can be used to process the

signal. Of the two techniques, only undersampling allows

part of the down conversion function to be brought into the

digital domain just through sampling, assuming that a sam-

pling frequency can be found that keeps the alias signals low

and that the A/D converter has the bandwidth to accept the

unconverted analog signal.

(2)-FULL signalling the FIFO is full and

new samples will not be written (Active

High)

(1)-READYB Output buffer has reached

the programmed threshold in FIFO

mode or the programmed number of

samples have been taken in snapshot

mode. (Active Low)

(0)-INTEGRATIONhasbeencompleted

in the input level detector and is ready to

be read. (Active High)

37

HSP50214

References

PDC Conﬁguration

For this example, the PDC is conﬁgured as follows:

For Intersil documents available on the web, see

http://www.Intersil.com/

CLKIN: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39MHz

Mode: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gated

Input Format: . . . . . . . . . . . . . As required by digital source

Carrier NCO Fc: . . . . . . . . . As determined by channel freq.

Carrier NCO Phase Offset: . . . . . . . . . . . . . . . . . . . . . . . . . 0

Carrier NCO Offset Frequency: . . . . . . . . . . . . . . . Disabled

CIC Filter: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabled

Decimation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PROCCLK: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28MHz

Half Band Filters: . . . . . . . . . . . . . . . . . HB3 and 5 Enabled

FIR Filter:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .gsmtemp ﬁle

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fs = 541.667kHz

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Decimation = 1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Passband: 90kHz

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transition Band: 25kHz

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Passband Atten: 3dB

. . . . . . . . . . . . . . . . . . . . . . . . . Stop Band Atten: 111.25713

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIR Order: 90

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIR Symmetry: Even

Re-Sampling Filter: . . . . . . . . . . . . . . . . . . . . . HB1 Enabled

The basis for this conﬁguration is:

Intersil AnswerFAX (321) 724-7800.

[1] HSP50210 Data Sheet, Intersil Corporation, AnswerFAX

Doc. No. 3652.

[2] Cellular Radio and Personal Communications: A Book of

Selected Readings, Theodore S. Rappaport, 1995 by

IEEE, Inc.

[3] AN9720 Application Note, Intersil Corporation, “Calcu-

lating Maximum Processing Rates of the PDC

(HSP50214)”, AnswerFAX Doc. No. 99720.

Sampling Rate: Select a high rate PROCCLK

Output Rate: 1.083MHz (4x Bit Rate; 8x Baud Rate)

CIC Filtering: Primarily Rate Reduction (39/18 = 2.166MHz).

HB Filtering: Flat passband with rate reduction by 4 - low

enough (541.66kHz) for sufﬁcient FIR Taps to be used.

FIR Filtering: Primary shaping ﬁlter/set ﬁnal out of band

suppression.

Polyphase/HalfBand Filtering: Interpolate by two to output

8x baud rate or 4x bit rate.

The CIC and halfband ﬁlter responses are shown in Figure

45A and B. The composite ﬁlter response, constrained pri-

marily by halfband ﬁlter 5 and the FIR ﬁlter are shown in Fig-

ure 46A-C.

For a more detailed discussion of design approaches and

trades when designing with the PDC, refer to AN9720[3],

“Calculating the Maximum Processing Rates of the PDC”.

38

HSP50214

10

-10

10

-10

-30

-50

-70

-90

-110

-130

-110

-130

f

= CIC INPUT RATE

f

= CIC INPUT RATE

S

FREQUENCY

f

FREQUENCY

f

S

R

FIGURE 45A. CIC FILTER RESPONSE

FIGURE 45B. HB3 FILTER RESPONSE

10

-10

10

-10

f

= CIC INPUT RATE

S

-30

-50

-70

-90

-110

-130

-110

-130

f

= CIC INPUT RATE

FREQUENCY

S

f

R

f

R

S

FREQUENCY

S

FIGURE 46A. HB5 FILTER RESPONSE

FIGURE 46B. 255 FIR TAP FILTER RESPONSE

10

-10

f

= CIC INPUT RATE

S

-30

-50

-70

-90

-110

-130

f

FREQUENCY

S

R

FIGURE 46C. COMPOSITE FILTER RESPONSE

FIGURE 46. PDC FILTER FREQUENCY SPECTRUMS EXAMPLE (NORMALIZED TO SAME SCALE)

39

HSP50214

Conﬁguration Control Word Deﬁnitions

Note that in the Conﬁguration Control Register tables some of to the master register. Figure 39 details the timing for proper

the available 32 bits in a control word are not used. Unused operation of the Microprocessor Write Section. Bits identiﬁed

bits do not need to be written to the master register. If the des- as “Reserved” should be programmed to a zero.

tination only has 16 bits, then only 2 bytes need to be written

CONTROL WORD 0: CHIP CONFIGURATION, INPUT SECTION, CIC GAIN (SYNCHRONOUS TO CLKIN)

BIT

POSITION

FUNCTION

Reserved

Carrier NCO External 0- The SYNCIN1 pin has no effect on the Carrier NCO.

DESCRIPTION

31-21

Reserved.

20

Sync Enable

1- When the SYNCIN1 pin is asserted, the carrier center frequency and phase are updated from

the holding registers to the active register. Also, if bit 0 of this word is active, the carrier phase

accumulator feedback will be zeroed to set the Carrier NCO to a known phase, allowing the

NCOs of multiple parts to be initialized and updated synchronously.

19

CIC External Sync

Enable

0- The SYNCIN1 pin has no effect on the CIC ﬁlter.

1- When the SYNCIN1 pin is asserted, the decimation counter is loaded, allowing the decimation

counters in multiple chips to be synchronized.

18

17

Input Format

Input Mode

0- Two’s Complement Input Format.

1- Offset Binary Input Format.

0- Input operates in Gated Mode.

1- Input operates in Interpolated Mode.

16-13

CIC Shift Gain

These bits control the barrel shifter at the input to the CIC ﬁlter. These bits are added to the

GAINADJ(2:0) pins to determine the total shift. The sum is saturated at 15. See the CIC Decima-

tion Filter Section for values to be programmed in this ﬁeld based on CIC ﬁlter Decimation. Bit 16

is the MSB.

SG = Floor [39 - (number of input bits) - 5log (R)] for 4 < R < 31.

2

SG = 15 for R = 4.

SG = 0 for R = 32.

12-7

CIC Counter Preload These bits control the decimation in the CIC ﬁlter. Program this ﬁeld to R-1, where R is the de-

sired decimation rate in the ﬁlter. The decimation rate range is 4-32. See CIC Filter Section for

effective decimation range relative to the CIC Shift Gain value. Bit 12 is the MSB.

While this ﬁeld allows values from 0 - 63, the valid values are in the range from 4- 32.

6

CIC Bypassed

Active high, this bit routes the output of the input shifter to the output of the CIC with no ﬁltering.

When the CIC ﬁlter is bypassed, CLKIN must be at least twice the input sample rate (ENI should

be toggled to achieve this). When the CIC ﬁlter is bypassed, the bottom 24 bits of the barrel shifter

output are routed to the halfband ﬁlters.

5-4

3

Number of Offset

Frequency Bits

00 - 8 bits.

01 - 16.

10 - 24.

11 - 32.

Syncout CLK Select

Clear Phase Accum

This bit selects whether the SYNCOUT signal is generated from CLKIN of from PROCCLK

0- CLKIN.

1- PROCLK.

2

1

0

0- Enable accumulator in Carrier NCO.

1- Zero feedback in accumulator.

Carrier NCO Offset

Frequency Enable

When set to 1, this bit enables the offset frequency word to be added to the center frequency

control word. The offset is loaded serially via the COF and COFSYNC pins.

Carrier NCO Load

Phase Accum On

Update

When this bit is set to 1, the µP update to the Carrier NCO frequency or an external carrier NCO

load using SYNCIN1 will zero the feedback of the phase accumulator as well as update the phase

or frequency. This function can be used to set the NCO to a known phase synchronized to an

external event.

40

HSP50214

CONTROL WORD 1: INPUT LEVEL DETECTOR (SYNCHRONOUS TO CLKIN)

BIT

POSITION

FUNCTION

DESCRIPTION

31

30

Reserved

Reserved.

Integration Mode

0- Integration of magnitude error stops when the interval counter times out.

1- Integration runs continuously. When the interval counter times out, the integrator reloads, and

the results of the integration is sent to a register for the processor to read.

29-14

13-0

Integration Interval

Input Threshold

These are the top 16 bits of the 18-bit integration counter, ICPrel. ICPrel = (N)/4+1; where N is

the desired integration period in CLKIN cycles, deﬁned as the number of input samples to be

integrated. N must be a multiple of 4: [0, 4, 8, 12, 16 .... , 2 ]. Bit 29 is the MSB. If the input is

interpolated, then the zeros must be accounted for, as they will be added to the threshold! If the

gated input mode is used, the same input sample will be accumulated multiple times.

18

Input magnitude threshold. Bits 12-0 correspond to input bits 12-0. The magnitude of the input

is added to this threshold, where the threshold is a signed number. Bit 13 is the MSB.

CONTROL WORD 2: INPUT LEVEL DETECTOR START STROBE (SYNCHRONIZED TO CLKIN)

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

Start Input Level

Detector AGC

Integrator

Writing to this location starts/restarts the input AGC error integrator. The integrator will either

restart or stop when the integration interval counter times out depending on bit 30 of control reg-

ister 1 (see Microprocessor Write Section).

CONTROL WORD 3: CARRIER NCO CENTER FREQUENCY (SYNCHRONIZED TO CLKIN)

BIT

POSITION

FUNCTION

DESCRIPTION

These bits control the frequency of the Carrier NCO. The frequency range of the NCO is ± F /2

31-0

Carrier Center

Frequency

S

32

where F is the input sample rate. The bits are computed by the equation N = (F

/ F )*2

.

S

NCO

S

Bit 31 is the MSB. This location is a holding register. After loading, a transfer to the active reg-

ister is done by writing to Control Word 5 or by generating a SYNCIN1 with Control Word 0 bit

20 set to 1.

CONTROL WORD 4: CARRIER PHASE OFFSET (SYNCHRONIZED TO CLKIN)

BIT

POSITION

FUNCTION

DESCRIPTION

31-10

9-0

Reserved

These bits, PO, are used to offset the phase of the carrier NCO. The bits are computed by the

Carrier Phase Offset

10

equation PO= INT[(2

φ

)/ 2π]

; (-π <φ < π) for 10-bit 2’s complement representation or

off

HEX off

from 0 to 2π for 10-bit offset binary representation. Bit 9 is the MSB. This location is a holding

register. After loading, a transfer to the active register is done by writing to Control Word 6 or by

generating a SYNCIN1 with Control Word 0 bit 20 set to 1.

CONTROL WORD 5: CARRIER FREQUENCY STROBE (SYNCHRONIZED TO CLKIN)

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

Carrier Frequency

Strobe

Writing to this address updates the carrier frequency control word from the holding register.

CONTROL WORD 6: CARRIER PHASE STROBE (SYNCHRONIZED TO CLKIN)

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

Carrier Phase

Strobe

Writing to this address updates the carrier phase offset control word with the value written to

the phase offset (PO) register.

41

HSP50214

CONTROL WORD 7: HB, FIR CONFIGURATION (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

Reserved

DESCRIPTION

31-22

21

Reserved.

Enable External

Filter Sync

0- The SYNCIN2 pin has no effect on the halfband and FIR filters.

1- When the SYNCIN2 pin is asserted, the filter control circuitry in the halfband filters, the FIR,

the resampler, and the discriminator are reset. SYNCIN2 can be used to synchronize the com-

putations of the filters in multiple parts for the alignment. See Synchronization Section.

20

19

Halfband (HB)

Bypass

1- Bypass Halfband Filters.

0- Enable HB Filters (at least one HB must be enabled).

HB5 Enable

0- Disables HB number 5 (the last in the cascade).

1- Enables HB filter number 5.

18

17

HB4 Enable

Setting this bit enables HB filter number 4.

HB3 Enable

Setting this bit enables HB filter number 3.

16

HB2 Enable

Setting this bit enables HB filter number 2.

15

HB1 Enable

Setting this bit enables HB filter number 1.

14-11

10

FIR Decimation

FIR Real/Complex

Load decimation from 1-16, where 0000 = 16. Bit 14 is the MSB.

0- Complex Filter.

1- Dual Real Filters.

9

8

FIR Sym Type

FIR Symmetry

FIR Taps

0- Odd Symmetry.

1- Even Symmetry.

0- Symmetric Filters.

1- Asymmetric Filters.

7-0

Number of taps in the FIR filter. Range is 1 to 255, where 0000000 is invalid.

CONTROL WORD 8: AGC CONFIGURATION 1 (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

DESCRIPTION

31-30

29

Reserved

Reserved.

Sync AGC Updates

to SYNCIN2

When this bit is 1, the SYNCIN2 pin loads the contents of the master registers into the AGC

accumulator.

28-16

15-12

Threshold

The magnitude measurement out of the cartesian to polar converter is subtracted from this val-

ue to get the gain error. A gain of 1.647 in the cartesian to polar conversion that must be taken

into account when computing this threshold. These bits are weighted -2 down to 2 . Bit 28 is

the MSB.

2

-10

Loop Gain 1

Mantissa

Selected when AGCGNSEL = 1. These bits, MMMM, together with the exponent bits, EEEE

(11-8), set the loop gain for the AGC loop. The gain adjustment per output sample is:

-(15 - EEEE)

1.5dB(Threshold -[Magnitude * 1.6]) 0.MMMM * 2

where magnitude ranges from 0

to 1.414 and the threshold is programmed in bits 28-16. The decimal value for the mantissa is

calculated as DEC(MMMM)/16. Bit 15 is the MSB.

11-8

Loop Gain 1

Exponent

Selected when AGCGNSEL = 1. These bits are EEEE. See description of bits 15-12. Bit 11 is

the MSB.

42

HSP50214

CONTROL WORD 8: AGC CONFIGURATION 1 (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

DESCRIPTION

7-4

3-0

Loop Gain 0 Mantissa Selected when AGCGNSEL = 0. These bits are MMMM. See description for bits 15-12. Same

equations are used for Loop 0. Bit 7 is the MSB.

Loop Gain 0

Exponent

Selected when AGCGNSEL = 0. These bits are EEEE. See description for bits 15-12. Same

equations are used for Loop 0. Bit 3 is the MSB.

CONTROL WORD 9: AGC CONFIGURATION 2 (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

DESCRIPTION

31-28

27-16

Reserved

Upper Limit

Maximum gain/minimum signal. The upper four bits are used for exponent; the remaining bits

form the mantissa in the fractional offset binary: [eeeemmmmmmmm]. See the AGC Section for

details. Bit 27 is the MSB. The gain is in dB. G = (6.02)(eeee) + 20log (1.0 + 0.mmmmmmmm)

10

GAIN dB/20

eeee = Floor [log (10

2

)].

GAIN dB/20 eeee

mmmmmmmm = Floor [512(10

/2

- 1)].

15-12

11-0

Reserved

Reserved.

Lower Limit

Minimum gain/maximum signal. The upper four bits are used for exponent; the remaining bits

form the mantissa in the fractional offset binary: [eeeemmmmmmmm]. See the AGC Section for

details. Bit 11 is the MSB. The gain is in dB. G = (6.02)(eeee) + 20log (1.0 + 0.mmmmmmmm).

10

GAIN dB/20

eeee = Floor [log (10

2

)].

GAIN dB/20 eeee

mmmmmmmm = Floor [512(10

/2

- 1)].

CONTROL WORD 10: AGC SAMPLE GAIN CONTROL STROBE (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

Sample AGC Gain

Level

Writing to this location samples the output of the AGC loop filter to stabilize the value for µP

reading.

CONTROL WORD 11: TIMING NCO CONFIGURATION (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

Reserved

DESCRIPTION

31-6

5

Reserved.

Enable External

0- SYNCIN2 has no effect on the timing NCO.

Timing NCO Sync

1- When SYNCIN2 is asserted, the timing NCO center frequency and phase are updated with

the value loaded in their holding registers. If bit 0 of this word is set to 1, the phase accumulator

feedback is also zeroed.

4-3

2

Number of Offset

Frequency Bits

00 - 8 bits.

01 - 16.

10 - 24.

11 - 32.

Enable Offset

Frequency

0- Zero Offset Frequency to Adder.

1- Enable Offset Frequency.

43

HSP50214

CONTROL WORD 11: TIMING NCO CONFIGURATION (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

Clear Phase

DESCRIPTION

1

0

0- Enable Accumulator.

1- Zero Feedback in Accumulator.

Accumulator

Timing NCO Phase

Accumulator Load

On Update

When this bit is set to 1, the µP update to the timing NCO frequency or an external timing NCO

load using SYNCIN2 will zero the feedback of the phase accumulator as well as update the

phase and frequency. This function can be used to set the NCO to a known phase synchronized

to an external event.

CONTROL WORD 12: TIMING NCO CENTER FREQUENCY (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

DESCRIPTION

31-0

Timing NCO Center

Frequency

These bits control the frequency of the timing NCO. The frequency range of the NCO is from 0

to F

where F is the input sample rate to the re-sampling ﬁlter. The bits are com-

RESAMP

32

puted by the equation: N =(f

/F

)*2 . Bit 31 is the MSB. This location is a holding

OUT RESAMP

register. After loading, a transfer to the active register is done by writing to Control Word 14 or

by generating a SYNCIN2 with Control Word 11 bit 5 set to 1.

CONTROL WORD 13: TIMING PHASE OFFSET (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

DESCRIPTION

31-8

7-0

Reserved

Reserved.

Timing NCO Phase

Offset

These bits are used to offset the phase of the carrier NCO. The range is 0 to 1 times the resa-

mpler input period interpreted either as ± T/2 (2’s complement) or 0 to T (offset binary). Bit 7 is

the MSB. This location is a holding register. After loading, a transfer to the active register is done

by writing to Control Word 15 or by generating a SYNCIN2 with Control Word 11 bit 5 set to 1.

CONTROL WORD 14: TIMING FREQUENCY STROBE (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

Timing Frequency

Strobe

Writing to this address updates the active timing NCO frequency register in the timing NCO (see

Timing NCO Section).

CONTROL WORD 15: TIMING PHASE STROBE (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

Timing Phase Strobe Writing to this address updates the active timing NCO phase offset register in the timing NCO

(see Timing NCO Section).

44

HSP50214

CONTROL WORD 16: RE-SAMPLING FILTER CONTROL (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

Reserved

DESCRIPTION

31-12

11-4

Reserved.

Resampler Output

Pulse Delay

NOTE: These bits program the delay between output samples when interpolating. The extra out-

puts can be delayed from 2 to 255 clocks from the ﬁrst output. A delay of 2 equals 255

clocks of delay. A delay of 0 or 1 is an invalid mode. When interpolating by 2, one extra

output is generated; when interpolating by 4, 3 extra outputs are generated. Program by

the equation (PROCCLK/f

) - 1. Bit 11 is the MSB.

OUT

NOTE: If less than 5 is programmed, there will not be sufficient time to fully update the out-

put buffer. If less than 16 is programmed, the serial output may be preempted. This

means that it won’t finish and if the sync is programmed to follow the data, there

may never be a sync.

3

Resampler Bypass

0- Re-Sampling Filter Enabled. A valid combination of bits 2-0 must also be selected.

1- Re-Sampling Filter is Bypassed.

2-0

Filter Mode Select;

2- HB2 Enabled

1- HB1 Enabled

0- Resampler

Enabled

000- Not Valid.

001- Resampler Enabled.

010- Halfband 1 Enabled.

011- Resampler and Halfband Filter 1 Enabled.

100- Not Valid.

101- Not Valid.

110- Both Halfband Filters Enabled.

111- Resampler and Both Halfband Filters Enabled.

CONTROL WORD 17: DISCRIMINATOR FILTER CONTROL, DISCRIMINATOR DELAY (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

DESCRIPTION

31-17

Reserved

Reserved.

16-15

Phase Multiplier

These bits program allow the phase output of the cartesian to polar converter to be multiplied by

1, 2, 4, or 8 (modulo 2π) to remove phase modulation before the frequency is measured.

00- No Shift on Phase Input to frequency discriminator.

01- Shift Phase Input to frequency discriminator up 1 (one bit), discarding the MSB and zero ﬁlling

the LSB.

10- Shift Phase Input to frequency discriminator up 2 (two) bits, discarding the MSB and zero ﬁll-

ing the LSB.

11- Shift Phase Input to frequency discriminator up 3 (three) bits, discarding the MSB and zero

ﬁlling the LSB.

14

Discriminator Enable

0- Disable Discriminator.

1- Enable Discriminator.

13-11

Discriminator FIR

Decimation

The decimation can be programmed from 1 to 8, where 000 = decimate by 8; 001 = decimate by

1; 010 = decimate by 2; 011 = decimate by 3; 100 = decimate by 4; 101 = decimate by 5; 110 =

decimate by 6; and 111 - decimate by 7.

10

9

FIR Symmetry Type

FIR Symmetry

0- Odd Symmetry.

1- Even Symmetry.

0- Symmetric.

1- Asymmetric.

8-3

2-0

Number of FIR Taps

Discriminator Delay

Number of FIR taps from 1 to 63, where 00000 is not valid (00001 = 1 tap, 00010 = 2 taps, etc.

up to 11111 = 63 taps). Bit 8 is the MSB.

Sets the number of delays from 1 to 8 in the discriminator. Set delay ddd to delay minus 1,

where 000 represents 1 delay; 001 represents 2 delays, 010 represents 3 delays, 011 repre-

sents 4 delays, 100 represents 5 delays, 101 represents 6 delays, 110 represents 7 delays, and

111 represents 8 delays. If ddd the decimal representation bits 2-0, then the discriminator a

-(ddd + 1)

transfer function H(Z) = 1-Z

.

45

HSP50214

CONTROL WORD 18: TIMING ERROR PRELOADS (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

Reserved

DESCRIPTION

31-28

27-16

Reserved.

NCO Divide

The Resampler NCO output is divided down by the value loaded into this register plus 1. Load

with a value that is one less than the desired period. Bit 27 is the MSB.

11-0

Reference Divide

The reference clock is divided down by the value loaded into this register plus 1. Load with a

value that is one less than the desired period. Bit 27 is the MSB. A minimum preload of “I” is

required.

CONTROL WORD 19: SERIAL OUTPUT ORDER (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

Reserved

DESCRIPTION

31

Reserved.

30-28

Data Source for

SEROUTA

Serial Output A source. The serial data source is selected using Table 12 (see Output Section).

Serial Output B source. The serial data source is selected using Table 12 (see Output Section).

27-25

24-21

Data Source for

SEROUTB

Number of Serial

Word Links in a

Chain

This parameter determines the number of SERSYNC pulses generated. It can be set from 1 to

7. If this parameter matches the number of serial words that are linked together to form a serial

output chain, then there will be a sync pulse for every word in the serial output. In applications

where a processor is receiving the serial data, it may be desirable to have a single SERSYNC

pulse for the whole serial output chain, instead of a SERSYNC for each word in the data chain.

The processor then parses out the various data words. As an example, if the I and Q are

chained together and a single SERSYNC pulse is generated for this serial output chain, no am-

biguity exists in the processor about which two data samples (one from I and one from Q) are

related.

20-18

17-15

14-12

11-9

8-6

Link Following I Data The serial data word, or link, following the I data word is selected using Table 12

(see Output Section).

Link Following Q

Data

The serial data word, or link, following the Q data word is selected using Table 12

(see Output Section).

Link Following

Magnitude Data

The serial data word, or link, following the MAG data word is selected using Table 12

(see Output Section).

Link Following

Phase Data

The serial data word, or link, following the PHAS data word is selected using Table 12

(see Output Section).

Link Following

Frequency Data

The serial data word, or link, following the FREQ data word is selected using Table 12

(see Output Section).

5-3

Link Following AGC

Level Data

The serial data word, or link, following the AGC data word is selected using Table 12

(see Output Section).

2-0

Link Following Timing

Error Data

The serial data word, or link, following the TIMERR data word is selected using Table 12

(see Output Section).

46

HSP50214

CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION

(SYNCHRONIZED WITH PROCCLK)

BIT

POSITION

FUNCTION

Reserved

DESCRIPTION

31-26

Reserved.

25

Data Source for

Least Significant

Bytes of AOUT and

BOUT

Output LSBytes, bits (7:0), of AOUT and BOUT can provide:

0- Buffer RAM Mode Output or.

1- Parallel Direct Mode Output.

24

Buffered Output

Mode Interface

Buffered Mode Output interfaces to either:

0- 8-bit µP (address = µP ASEL(5:#); CLK = µP RAM read).

1- 16-bit µP (address = SEL(2:0); CLK = OEBL).

23-22

AOUT Direct Parallel

Output Mode Data

Source

The data word sent by the Direct Parallel Output Mode to AOUT is:

00- I Data.

01- Magnitude.

1X- Frequency.

21-20

BOUT Direct Parallel

Output Mode Data

Source

The data word sent by the Direct Parallel Output Mode to BOUT is:

00- Q Data.

01- Phase.

1X- Magnitude.

19

18

Serial Output Sync

Polarity

0- Normal Sync Mode (active high).

1- Sync Inverted (active low).

Serial Output Clock

Polarity

0- Output Clock Inverted rising edge aligns with data transitions.

1- Output Clock Normal falling edge aligns with data transitions.

0

1

17

Serial Output Sync

Position

0- Sync is asserted one bit time after the last bit of the serial word (Late Mode).

1- Sync is asserted one bit time prior to the first bit of the serial word (Early Mode).

16-14

Serial Out Clock

Divider

000- Serial Output at PROCCLK/16.

001- Serial Output at PROCCLK/8.

010- Serial Output at PROCCLK/4.

011- Serial Output at PROCCLK/2.

1XX- Serial Output at PROCCLK rate.

13-12

I Data Serial Output

Tag Bit

00- No Tag Bit. LSB of word is passed.

01- 0 Tag Bit. LSB of word is set to zero.

1X- 1 Tag Bit. LSB of word is set to one.

11-10

9-8

Q Data Serial Output (See I Data Serial Output Tag Selection above).

Tag Bit

Magnitude Data Se-

rial Output Tag Bit

(See I Data Serial Output Tag Selection above).

7-6

Phase Data Serial

Output Tag Bit

5-4

Frequency Data Se-

rial Output Tag Bit

3-2

AGC Data Serial

Output Tag Bit

47

HSP50214

CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION

(SYNCHRONIZED WITH PROCCLK) (Continued)

BIT

POSITION

FUNCTION

DESCRIPTION

(See I Data Serial Output Tag Selection above).

1-0

Timing Error Data

Serial Output Tag Bit

CONTROL WORD 21: BUFFER RAM OUTPUT CONTROL REGISTER (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

Reserved

DESCRIPTION

31-16

15

Reserved.

Output Buffer Mode

0- The output buffer operates in snapshot mode.

1- The output buffer operates in FIFO mode.

14-12

11-4

3-0

FIFO Mode Depth

Threshold

In FIFO mode, when the FIFO depth reaches this threshold, an interrupt is generated and the

READY ﬂag is asserted. The threshold may be set from 0 to 7. Bit 14 is the MSB. The interrupt

is generated when the FIFO depth reaches the threshold, as the FIFO ﬁlls.

Snapshot Mode

Interval

In snapshot mode, the interval between snapshots in the output sample times is determined by

8

this 8-bit binary number, i.e. 256, (2 ), sample time counts between snapshot samples. Program

this parameter to 1 less than the desired interval. Bit 11 is the MSB.

Snapshot Mode

Number of Samples

In snapshot mode, the number of samples stored each time the snapshot interval counter times

out is equal to the decimal version of this 4-bit number. The range is 1- 8. Bit 3 is the MSB.

CONTROL WORD 22: BUFFER RAM OUTPUT FIFO RESET (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

FIFO reset

DESCRIPTION

N/A

A write to this address increments the output FIFO RAM address pointers to READ = 111 and

WRITE = 000.

CONTROL WORD 23: INCREMENT OUTPUT FIFO (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

FIFO Strobe

DESCRIPTION

N/A

A write to this address increments the output FIFO/buffer to the next sample set.

CONTROL WORD 24: SYNCOUT STROBE OUTPUT PIN

(SYNCHRONIZED TO CLKIN OR PROCCLK DEPENDING ON PROGRAMMING IN CONTROL WORD 0)

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

SYNCOUT Strobe

A write to this address generates a one clock period wide strobe on the SYNCOUT pin that is

synchronized to the clock. This strobe may be synchronized to CLKIN or PROCCLK based on

the programming of bit 3 of Control Word 0.

48

HSP50214

CONTROL WORD 25: COUNTER AND ACCUMULATOR RESET (SYNCHRONIZED TO BOTH CLKIN AND PROCCLK)

BIT

POSITION

FUNCTION

DESCRIPTION

N/A

Counter and

Accumulator Reset

A write to this address initializes the counters and accumulators for testing. Items that are reset are:

Carrier NCO

1. Loads phase offset <9:0> into register to be used for adding to accumulator.

2. Enables feedback on the accumulator.

CIC Filter

1. Resets the decimation counter.

2. Clears enables to CIC.

3. Clears accumulators in CIC.

4. Clears enable leaving CIC.

Halfband Filters

1. Resets compute counter in Halfband control.

2. Resets read address for all Halfband Filters.

3. Resets write address for all Halfband Filters.

4. Clears input available strobe.

5. Resets Halfband control logic.

255 Tap FIR

1. Resets FIR read and write address pointers.

2. Zero’s coefﬁcient read address.

AGC Loop

1. Clears accumulator in loop ﬁlter.

Resampler and Interpolation Halfband Filters.

1. Resets counters for Halfband addresses for writing.

2. Resets output enable.

3. Reset controller for Resampler.

Timing NCO

1. Initializes counters for inserting extra pulses when interpolating halfbands are enabled.

Discriminator

1. Resets read and write address pointers.

2. Zero’s coefﬁcient read address.

Cartesian to Polar Coordinate Counter.

1. Resets Cordic counters (stops current computation).

FIFO Control

1. Resets decoder for controlling FIFO.

2. Resets write address for FIFO.

3. Clears RD and INTRRPT.

4. Resets “depth” and “full” ﬂags.

5. Sets the empty ﬂag.

6. Sets the read address to “7”, write address to “0”.

Snapshot Control

1. Zeros the group number.

2. Load interval counter.

3. Resets write address and read address for FIFO.

Output Serial Control

1. Reloads shift counter.

2. Reloads “Number of Words” counter.

3. Reloads counter for sync (for early or late).

4. Reloads counter for dividing down SERCLK.

49

HSP50214

CONTROL WORD 26: LOAD AGC GAIN (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

AGC Load

DESCRIPTION

N/A

Writing to this location generates a strobe to load the AGC loop accumulator with bits (15:5) to

the master registers. These bits are loaded into the MSBs of the AGC loop ﬁlter accumulator

with bits (15:12) mapping to the shift (exponent) control bits and bits (11:5) mapping to the mul-

tiplier (mantissa) bits. Bits (11:5) represent a binary mantissa mapped to the linear gain as:

01.XXXXXXX. See AGC Section.

CONTROL WORD 27: TEST REGISTER (SYNCHRONIZED TO CLKIN)

BIT

POSITION

FUNCTION

Reserved

DESCRIPTION

31-0

A ﬁxed value 0000 0010 0111 1000 [0278]

is loaded here for normal operation. A ﬁxed value

HEX

0000 0010 0111 1010 [027A]

7FFF.

is loaded here for setting the Sin/Cos generator outputs to

HEX

CONTROL WORDS 64-95: DISCRIMINATOR COEFFICIENT REGISTERS (SYNCHRONIZED TO PROCCLK)

BIT

POSITION

FUNCTION

DESCRIPTION

31-10

Discriminator FIR

Coefficient

The discriminator FIR coefﬁcients are 22-bit-two’s complement. If the ﬁlter is symmetric, the co-

efﬁcients are loaded from the center coefﬁcient at address 64 to the last coefﬁcient. If the ﬁlter

is asymmetric the coefﬁcients C to C are loaded with C in address 64 up to 64+N, where N

0

N

0

is number of asymmetric coefﬁcients.

CONTROL WORDS 128-255: 255 PROGRAMMABLE COEFFICIENT REGISTERS

BIT

POSITION

FUNCTION

DESCRIPTION

31-10

Programmable FIR

Coefficient

The programmable FIR coefﬁcients are 22-bit-two’s complement. If the ﬁlter is symmetric, the

coefﬁcients are loaded from the center coefﬁcient at address 128 to the last coefﬁcient. If the

ﬁlter is asymmetric the coefﬁcients C to C are loaded with C in address 128 up to 128+N,

0

N

0

where N is number of asymmetric coefﬁcients.

Real Filters are computed as:

Xn-k+1 Ck1 + Xn-k+2 Ck-2 + ... XnC0).

where C0 is the coefﬁcient in address 128 and Xo is the oldest data sample.

Complex ﬁlters outputs are computed as follows:

Xn is the most recent data sample.

k is the number of samples = number of (complex) taps.

C0_re is the coefﬁcient loaded into CW128.

C0_im is the coefﬁcient loaded into CW129.

The convolution starts with the oldest data, times the last complex coefﬁcient, and ends with

the newest data, times the ﬁrst complex coefﬁcient loaded.

Iout = (-Xn-k+1_q * Ck-1_im + Xn-k+1_i * Ck-1_re).

+ (-Xn-k+2_q * Ck-2_im + Xn-1+2_i * Ck-2_re).

+...

+ (-Xn_q * C0_im + Xn_i * C0_re).

Qout = (Xn-k+1_i * Ck-1_im + Xn-k+1_q * Ck-1_re).

+ (Xn-k+2_i * Ck-2_im + Xn-1+2_q * Ck-2_re).

+...

+ (Xn_i * C0_im + Xn_q * C0_re).

50

HSP50214

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to V +0.5V

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

Thermal Resistance (Typical, Note 1)

θ_JA( C/W)

CC

MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28

o

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C

o

Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C

o

Operating Conditions

(Lead Tips Only)

Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V

Temperature Range

o

Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to 70 C

o

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C

Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V

Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2V to V

CC

Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . 1V/ns Max

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

5. θ is measured with the component mounted on an evaluation PC board in free air.

JA

o

DC Electrical Speciﬁcations

V

= 5 ±5%, T = 0 C to 70 C, Commercial; -40 C to 85 C, Industrial

A

CC

PARAMETER

Logical One Input Voltage

Logical Zero Input Voltage

Clock Input High

SYMBOL

TEST CONDITIONS

= 5.25V

MIN

2.0

-

MAX

-

UNITS

V

IH

CC

V

= 4.75V

= 5.25V

0.8

-

V

IL

V

3.0

-

V

IHC

Clock Input Low

V

= 4.75V

0.8

-

V

ILC

OH

Output High Voltage

V

I

= -400µA, V

= 4.75V

2.6

-

V

OH

CC

Output Low Voltage

V

= +2.0mA, V

CC

0.4

10

500

10

364

V

OL

Input Leakage Current

Standby Power Supply Current

Output Leakage Current

Operating Power Supply Current

I

V

= V

CC

or GND, V

= 5.25V

-10

-

µA

I

IN

CC

I

= 5.25V, Outputs Not Loaded

CCSB

CC

I

= V

CC

or GND, V

= 5.25V

-10

-

O

IN

CC

I

f = 52MHz, V = V

IN

or GND,

mA

(Note 2)

CCOP

CC

= 5.25V, Outputs Not Loaded

V

CC

Input Capacitance

Output Capacitance

NOTES:

C

Freq = 1MHz, V

open, all measure-

-

10

pF

(Note 3)

IN

CC

ments are referenced to device ground

C

OUT

6. Power Supply current is proportional to operation frequency. Typical rating for I

o

is 6mA/MHz.

CCOP

7. Capacitance T = 25 C, controlled via design or process parameters and not directly tested. Characterized upon initial design and at

A

major process or design changes.

o

AC Electrical Speciﬁcations

V

= 5 ±5%, T = 0 to 70 C, Commercial; -40 C to 85 C, Industrial

CC A

52MHz

MAX

PARAMETER

SYMBOL

MIN

19

7

UNITS

ns

CLKIN Clock Period

CLKIN High

t

-

CP

t

-

ns

CH

CLKIN Low

t

7

-

ns

CL

PROCCLK Period

PROCCLK High

PROCCLK Low

REFCLK Clock Frequency

REFCLK High

t

28.5

7

-

ns

PCP

PCH

t

-

ns

t

7

-

ns

PCL

RCP

RCH

f

-

PROCCLK/2

-

ns

t

7

ns

51

HSP50214

o

AC Electrical Speciﬁcations

V

= 5 ±5%, T = 0 to 70 C, Commercial; -40 C to 85 C, Industrial (Continued)

CC

A

52MHz

PARAMETER

SYMBOL

MIN

7

MAX

UNITS

ns

REFCLK Low

t

-

RCL

Setup Time GAINADJ(2:0), IN(13:0), ENI, COF, COFSYNC, and SYNCIN1 to CLKIN

Hold Time GAINADJ(2:0), IN(13:0), ENI, COF, COFSYNC, and SYNCIN1 to CLKIN

Setup Time AGCGNSEL, SOF, MCSYNCI, SOFSYNC, and SYNCIN2 to PROCCLK

Hold Time AGCGNSEL, SOF, MCSYNCI, SOFSYNC, and SYNCIN2 to PROCCLK

Setup Time A(2:0), C(7:0) to Rising Edges of WR

t

7

ns

DS

DH

t

0

ns

t

7

ns

DSS

DHS

t

0

ns

t

8

ns

WS

WH

WC

Hold Time A(2:0), C(7:0) to Rising Edges of WR

t

3

ns

WR to CLKIN

15

ns

(Note 6)

PROCCLK to AOUT(15:0), BOUT(15:0), DATARDY, SEROUTA, SEROUTB,

SERSYNC, INTRRP, MCSYNCO SYNCOUT Valid

t

-

10

ns

DO

PROCCLK to SERCLK Valid

WR High

t

-

15

10

25

-

15

-

ns

DOS

t

WRH

WR Low

t

-

WRL

RD Low

t

-

RL

Address Setup to Read Low

RD LOW to Data Valid

RD HIGH to Output Disable

t

3

AS

t

-

24

10

RDO

t

-

ns

ROD

(Note 5)

Output Enable Time

Output Disable Time

t

-

8

ns

OE

t

ns

OD

(Note 5)

Output Rise, Fall Time

NOTES:

t

-

3

ns

(Note 5)

RF

8. AC tests performed with C = 40pF, I = 2mA, and I

OL

= -400µA. Input reference level for CLK is 2.0V, all other inputs 1.5V.

OH

L

Test V = 3.0V, V

= 4.0V, V = 0V.

IH

IHC

IL

9. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design

changes.

10. Setup time required to ensure action initiated by WR will be seen by a particular CLKIN.

AC Test Load Circuit

S

DUT

1

C

(NOTE)

L

±

I

1.5V

I

OL

OH

SWITCH S1 OPEN FOR I

AND I

CCOP

CCSB

EQUIVALENT CIRCUIT

NOTE: Test head capacitance.

52

HSP50214

Waveforms

t

RL

RD

t

AS

t

WRH

WRL

A(2-0)

WR

t

WS

t

WH

C(0-7)

C(0-7), A(0-2)

t

ROD

RDO

FIGURE 47. TIMING RELATIVE TO WR

FIGURE 48. TIMING RELATIVE TO RD

t

CP

t

CH

CL

CLKIN

t

DS

DH

IN(13:0), COF

GAINADJ(2:0), ENI,

COFSYNC, SYNCIN1

t

RF

2.0V

0.8V

WR

t

WC

FIGURE 49. OUTPUT RISE AND FALL TIMES

FIGURE 50. TIMING RELATIVE TO CLKIN

t

PCP

t

PCH

PCL

PROCCLK

t

DHS

DSS

AGCGNSEL, MCSYNC1

SOF, SOFSYNC, SYNCIN2

OEAH, OEAL,

OEBH, OEBL

AOUT(15:0), BOUT(15:0),

DATARDY, INTRRP, MCSYNC0,

SYNCOUT, SEROUTA,

1.5V

SEROUTB, SERSYNC

t

OD

OE

t

DO

OUTA(15:8), OUTA(7:0),

OUTB(15:8), OUTB(7:0)

1.7V

1.3V

SERCLK

DOS

FIGURE 51. OUTPUT ENABLE/DISABLE

FIGURE 52. TIMING RELATIVE TO PROCCLK

t

RCP

I

f

RCP =

t

RCP

2 t

t

RCP =

RCP

t

RCH

t

RCL

FIGURE 53. REFCLK

53

HSP50214

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Ofﬁce Headquarters

NORTH AMERICA

EUROPE

ASIA

Intersil Corporation

Intersil SA

Mercure Center

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

Intersil (Taiwan) Ltd.

Taiwan Limited

7F-6, No. 101 Fu Hsing North Road

Taipei, Taiwan

Republic of China

TEL: (886) 2 2716 9310

FAX: (886) 2 2715 3029

P. O. Box 883, Mail Stop 53-204

Melbourne, FL 32902

TEL: (321) 724-7000

FAX: (321) 724-7240

54


型号：	HSP50214
厂家：	Intersil
描述：	Programmable Downconverter 可编程下变频器
文件：	总54页 (文件大小：394K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HSP50214 [INTERSIL]

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