HSP43881GC-30 [INTERSIL]
Digital Filter; 数字滤波器型号: | HSP43881GC-30 |
厂家: | Intersil |
描述: | Digital Filter |
文件: | 总21页 (文件大小:151K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HSP43881
Data Sheet
May 1999
File Number 2758.4
Digital Filter
Features
The HSP43881 is a video speed Digital Filter (DF) designed
to efficiently implement vector operations such as FIR digital
filters. It is comprised of eight filter cells cascaded internally
and a shift and add output stage, all in a single integrated
circuit. Each filter cell contains a 8 x 8-bit multiplier, three
decimation registers and a 26-bit accumulator. The output
stage contains an additional 26-bit accumulator which can
add the contents of any filter cell accumulator to the output
stage accumulator shifted right by 8 bits. The HSP43881 has
a maximum sample rate of 30MHz. The effective multiply
accumulate (mac) rate is 240MHz.
• Eight Filter Cells
• 0MHz to 30MHz Sample Rate
• 8-Bit Coefficients and Signal Data
• 26-Bit Accumulator Per Stage
• Filter Lengths Over 1000 Taps
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
The HSP43881 DF can be configured to process expanded
coefficient and word sizes. Multiple DFs can be cascaded for
larger filter lengths without degrading the sample rate or a
single DF can process larger filter lengths at less than
30MHz with multiple passes. The architecture permits
processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter coefficients
are less than 1.0, making even larger filter lengths possible.
The DF provides for 8-bit unsigned or two’s complement
arithmetic, independently selectable for coefficients and
signal data.
• 1-D and 2-D FIR Filters
• Radar/Sonar
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add
• Sample Rate Converters
Ordering Information
PART
NUMBER
TEMP. RANGE
o
( C)
PACKAGE
84 Ld PLCC
84 Ld PLCC
84 Ld PLCC
85 Ld PGA
85 Ld PGA
85 Ld PGA
PKG. NO.
N84.1.15
N84.1.15
N84.1.15
G85.A
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
HSP43881JC-20
HSP43881JC-25
HSP43881JC-30
HSP43881GC-20
HSP43881GC-25
HSP43881GC-30
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
1
1
1
of / , / or / the input sample rate. These registers also
2
3
4
provide the capability to perform 2-D operations such as
matrix multiplication and N x N spatial
correlations/convolutions for image processing applications.
G85.A
G85.A
Block Diagram
V
V
SS
CC
DIN0 - DIN7 TCS
8
DIENB
CIENB
5
DCMO - 1
ERASE
8
8
8
8
8
8
8
8
TCCI
TCCO
DF
DF
DF
DF
DF
DF
DF
DF
FILTER
CELL 0
FILTER
CELL 1
FILTER
CELL 2
FILTER
CELL 3
FILTER
CELL 4
FILTER
CELL 5
FILTER
CELL 6
FILTER
CELL 7
8
5
8
8
8
8
8
8
8
8
CIN0 - 7
COUT0 - 7
RESET
CLK
26
26
26
26
26
26
26
5
26
COENB
3
ADR0 - 2
MUX
26
RESET
CLK
ADR0, ADR1, ADR2
2
OUTPUT
STAGE
SHADD
SENBL
SENBH
2
26
SUM0 - 25
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HSP43881
Pinouts
85 PIN GRID ARRAY (PGA)
TOP VIEW, PINS DOWN
1
2
3
4
5
6
7
8
9
10
11
V
V
V
SS
A
B
C
D
E
RESET DIN7 DIN6 DIN3 DIN0 TCCI
COENB
CC
CC
V
V
SS
CIENB
COUT7 TCCO ERASE TCS
ALIGN
DIN1 DIN2
DIN5 DIN4
CIN7 CIN6 CIN4
CIN5 CIN3
CC
DIENB
COUT5 COUT6
PIN
V
COUT3 COUT4
CIN2
CIN0
CC
SENBL
COUT1
COUT2
V
CIN1
SS
V
V
V
F
COUT0 SHADD
CC
SS
SS
SUM0
SUM1
G
ADR2 DCM0 CLK
ADR1 ADR0
SUM3 SUM2
H
J
SUM5 SUM4
V
V
SUM25
SUM24
SUM20 SUM17 SUM16
SUM7
SS
CC
K
SENBH
V
SUM19
SUM15 SUM12 SUM10 SUM8 SUM6
V
V
SS
CC
SS
L
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14
SUM13
SUM11 SUM9
V
V
SS
CC
HSP43881
TOP VIEW, PINS UP
1
2
3
4
5
6
7
8
9
10
11
L
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14
V
SUM13
V
SUM11 SUM9
CC
SS
K
SENBH SUM24
V
V
SUM19
V
SS
SUM15 SUM12 SUM10 SUM8
SUM6
SS
CC
J
V
SUM25
ADR0
DCM0
SUM20 SUM17 SUM16
SUM7
SUM5
SUM3
V
CC
SS
H
ADR1
ADR2
SUM4
SUM2
G
F
CLK
SUM1
SUM0
CIN1
V
COUT0 SHADD
V
V
SS
CC
SS
E
D
COUT1
V
COUT2
CIN0 SENBL
SS
V
CIN2
CIN5
CIN6
COUT3 COUT4
COUT5 COUT6
CC
C
B
ALIGN
PIN
DIENB
DIN5
DIN4
CIN3
CIN4
V
COUT7 COUT8 ERASE DIN8
DIN1
DIN6
DIN2
DIN3
CIENB
DIN0
CIN7
CIN8
CC
A
V
COENB
V
DIN7
V
V
RESET
SS
CC
CC
SS
2
HSP43881
Pinouts (Continued)
84 LEAD PLCC PACKAGE
BOTTOM VIEW
11 10
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
SUM23
SUM22
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
COUT6
COUT7
V
V
SS
CC
SUM21
SUM20
SUM19
SUM18
TCCO
COENB
V
CC
ERASE
RESET
DIENB
TCS
V
SS
SUM17
SUM16
DIN7
V
CC
SUM15
SUM14
SUM13
SUM12
DIN6
DIN5
DIN4
DIN3
DIN2
V
SS
SUM11
SUM10
SUM9
SUM8
SUM7
DIN1
DIN0
CIENB
TCCI
V
CC
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
NOTE: An overbar on a signal name represents an active LOW signal.
3
HSP43881
Pin Description
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
V
A3, A10, B1,
D11, F10, J1,
K4, L7
+5V Power Supply Input.
CC
V
A1, A11, E2,
F1, E11, H11,
K3, K6, L9
Power Supply Ground Input.
SS
CLK
G3
I
I
The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz.
DIN0-7
A58, B67, C67
These eight inputs are the data sample input bus. Eight bit data samples are synchronously loaded
through these pins to the X register of each filter cell simultaneously. The DIENB signal enables
loading, which is synchronous on the rising edge of the clock signal.
TCS
B5
C5
I
The TCS input determines the number system interpretation of the data input samples on pins
DIN0-7 as follows:
TCS = Low → Unsigned Arithmetic.
TCS = High → Two's Complement Arithmetic.
The TCS signal is synchronously loaded into the X register in the same way as the DIN0-7
inputs.
DIENB
I
A low on this enables the data sample input bus (DIN0-7) to all the filter cells. A rising edge of the
CLK signal occurring while DIENB is low will load the X register of every filter cell with the 8-bit value
present on DIN0-7. A high on this input forces all the bits of the data sample input bus to zero; a
rising CLK edge when DIENB is high will load the X register of every filter cell with all zeros. This
signal is latched inside the DF, delaying its effect by one clock internal to the DF. Therefore, it must
be low during the clock cycle immediately preceding presentation of the desired data on the
DIN0-7 inputs. Detailed operation is shown in later timing diagrams.
CIN0-7
TCCI
B9-11,
C10-11, D10,
E9-10
I
I
These eight inputs are used to input the 8-bit coefficients. The coefficients are synchronously load-
ed into the C register of filter CELL 0 if a rising edge of CLK occurs while CIENB is low. The CIENB
signal is delayed by one clock as discussed below.
A9
The TCCI input determines the number system interpretation of the coefficient inputs on pins CIN07
as follows:
TCCI = LOW E Unsigned Arithmetic.
TCCI = HIGH E Two's Complement Arithmetic.
The TCCI signal is synchronously loaded into the C register in the same way as the CIN0-7 inputs.
CIENB
B8
I
A low on this input enable the C register of every filter cell and the D registers (decimation) of every
filter cell according to the state of the DCM0-1 inputs. A rising edge of the CLK signal occurring while
CIENB is low will load the C register and appropriate D registers with the coefficient data present at
their inputs. This provides the mechanism for shifting the coefficients from cell to cell through the
device. A high on this input freezes the contents of the C register and the D registers ignoring the
CLK signal. This signal is latched and delayed by one clock internal to the DF. Therefore, it must be
low during the clock cycle immediately preceding presentation of the desired coefficient of the CIN0-
7 inputs. Detailed operation is shown in the Timing Diagrams Section.
COUT0-7
B2, C1-2,
D1-2, E1, E3,
F2
O
These eight three-state outputs are used to output the 8-bit coefficients from filter cell 7. These out-
puts are enabled by the COENB signal low. These outputs may be tied to the CIN0-7 inputs of the
same DF to recirculate the coefficients, or they may be tied to the CIN0-7 inputs of another DF to
cascade DFs for longer filter lengths.
TCCO
B3
A2
O
I
The TCCO three-state output determines the number system representation of the coefficients out-
put on COUTO-7. It tracks the TCCI signal to this same DF. It should be tied to the TCCI input of the
next DF in a cascade of DFs for increased filter lengths. This signal is enabled by COENB low.
COENB
A low on the COENB input enables the COUT0-7 and the TCCO output. A high on this input places
all these outputs in their high impedance state.
4
HSP43881
Pin Description (Continued)
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
These two inputs determine the use of the internal decimation registers as follows:
DCM0-1
G2, L1
DCM1
DCM0
Decimation Function
0
0
1
1
0
1
0
1
Decimation Registers not used.
One Decimation Register is used.
Two Decimation Registers are used.
Three Decimation Registers are used.
The coefficients pass from cell to cell at a rate determined by the number of decimation registers
used. When no decimation registers are used, coefficients move from cell to cell on each clock.
When one decimation register is used, coefficients move from cell to cell on every other clock, etc.
These signals are latched and delayed by one clock internal to the DF.
SUM0-25
J2, J5-8, J10,
K2, K5-11,
L-26, L8,
O
These 26 three-state outputs are used to output the results of the internal filter cell computations.
Individual filter cell results or the result of the shift and add output stage can be output. If an individ-
ual filter cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD signal
determines whether the selected filter cell result or the output stage adder result is output. The sig-
nals SENBH and SENBL enable the most significant and least significant bits of the SUM0-25 result,
respectively. Both SENBH and SENBL may be enabled simultaneously if the system has a 26-bit or
larger bus. However, individual enables are provided to facilitate use with a 16-bit bus.
L10-11
SENBH
SENBL
ADR0-2
K1
E11
I
I
I
A low on this input enables result bits SUM16-25. A high on this input places these bits in their high
impedance state.
A low on this input enables result bits SUM0-15. A high on this input places these bits in their high
impedance state.
G1, H1-2
These inputs select the one cell whose accumulator will be read through the output bus (SUM0-25)
or added to the output stage accumulator. They also determine which accumulator will be cleared
when ERASE is low. For selection of which accumulator to read through the output bus (SUM0-25)
or which to add to the output stage accumulator, these inputs are latched in the DF and delayed by
one clock internal to the device. If the ADR0-2 lines remain at the same address for more than one
clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the
addressed cell. Only the result available during the first clock, when ADR0-1 selects the cell, will be
output. This does not hinder normal operation since the ADR0-1 lines are changed sequentially.
This feature facilitates the interface with slow memories where the output is required to be fixed for
more than one clock.
SHADD
RESET
F3
A4
I
I
I
The SHADD input controls the activation of the shift-and-add operation in the output stage. This
signal is latched in the DF and delayed by one clock internal to the device. A detailed explanation is
given in the DF Output Stage Section.
A low on this input synchronously clears all the internal registers, except the cell accumulators. It
can be used with ERASE to also clear all the accumulators simultaneously. This signal is latched in
the DF and delayed by one clock internal to the DF.
ERASE
B4
C3
A low on this input synchronously clears the cell accumulator selected by the ADR0-1 signals. If
RESET is also low simultaneously, all cell accumulators are cleared.
ALIGN PIN
Used for aligning chip in socket or printed circuit board. Must be left as a no connect in circuit.
COUT0-7. With no decimation, the coefficient moves directly
from the C register to the output, and is valid on the clock
following its entrance. When decimation is selected the
coefficient exit is delayed by 1, 2 or 3 clocks by passing through
one or more decimation registers (D1, D2 or D3).
Functional Description
The Digital Filter Processor (DF) is composed of eight filter cells
cascaded together and an output stage for combining or
selecting filte5r cell outputs (See Block Diagram). Each filter cell
contains a multiplier accumulator and several registers (Figure
1). Each 8-bit coefficient is multiplied by an 8-bit data sample,
with the result added to the 26-bit accumulator contents. The
coefficient output of each cell is cascaded to the coefficient
input of the next cell to its right.
The combination of D registers through which the coefficient
passes is determined by the state of DCM0 and DCM1. The
output signals (COUT0-7) are connected to the CIN0-7 inputs
of the next cell to its right. The COENB input signal enables the
COUT0-7 outputs of the right most cell to the COUT-07 pins of
the device.
DF Filter Cell
An 8-bit coefficient (CIN0-7) enters each cell through the C
register on the left and exits the cell on the right as signals
The C and D registers are enabled for loading by CIENB.
Loading is synchronous with CLK when CIENB is low. Note that
5
HSP43881
CIENB is latched internally. It enables the register for loading
after the next CLK following the onset of CIENB low. Actual
loading occurs on the second CLK following the onset of
CIENB low. Therefore, CIENB must be low during the clock
cycle immediately preceding presentation of the coefficient on
the CIN0-7 inputs. In most basic FIR operations, CIENB will be
low throughout the process, so this latching and delay
sequence is only important during the initialization phase.
When CIENB is high, the coefficients are frozen.
decoded from ADR0-2 and the ERASE signal enable clearing
of the accumulator on the next CLK.
The ERASE and RESET signals clear the DF internal
registers and states as follows:
ERASE RESET
CLEARING EFFECT
1
1
No clearing occurs, internal state remains
same.
1
0
RESET only active, all registers except accu-
mulators are cleared, including the internal
pipeline registers.
These registers are cleared synchronously under control of
RESET, which is latched and delayed exactly like CIENB. The
output of the C register (C0-8) is one input to 8 x 8 multiplier.
0
0
1
0
ERASE only active, the accumulator whose
address is given by the ADR0-2 inputs is
cleared.
The other input to the 8 x 8 multiplier comes from the output of
the X register. This register is loaded with a data sample from
the device input signals DIN0-7 discussed above. The X
register is enabled for loading by DIENB. Loading is
Both RESET and ERASE active, all accumula-
tors, as well as all other registers are cleared.
synchronous with CLK when DIENB is low. Note that DIENB is
latched internally. It enables the register for loading after the
next CLK following the onset of DIENB low. Actual loading
occurs on the second CLK following the onset of DIENB low;
therefore, DIENB must be low during the clock cycle
The DF Output Stage
The output stage consists of a 26-bit adder, 26-bit register,
feedback multiplexer from the register to the adder, an output
multiplexer and a 26-bit three-state driver stage (Figure 2).
immediately preceding presentation of the data sample on the
DIN0-7 inputs. In most basic FIR operations, DIENB will be low
throughout the process, so this latching and delay sequence is
only important during the initialization phase. When DIENB is
high, the X register is loaded with all zeros.
The 26-bit output adder can add any filter cell accumulator
result to the 18 most significant bits of the output buffer. This
result is stored back in the output buffer. This operation takes
place in one clock period. The eight LSBs of the output buffer
are lost. The filter cell accumulator is selected by the ADR0-2
inputs.
The multiplier is pipelined and is modeled as a multiplier core
followed by two pipeline registers, MREG0 and MREG1 (Figure
1). The multiplier output is sign extended and input as one
operand of the 26-bit adder. The other adder operand is the
output of the 26-bit accumulator. The adder output is loaded
synchronously into both the accumulator and the TREG.
The 18 MSBs of the output buffer actually pass through the
zero mux on their way to the output adder input. The zero mux
is controlled by the SHADD input signal and selects either the
output buffer 18 MSBs or all zeros for the adder input. A low
on the SHADD input selects zero. A high on the SHADD input
selects the output buffer MSBs, thus, activating the shift and
add operation. The SHADD signal is latched and delayed by
one clock internally.
The TREG loading is disabled by the cell select signal,
CELLn, where n is the cell number. The cell select is decoded
from the ADR0-2 signals to generate the TREG load enable.
The cell select is inverted and applied as the load enable to
the TREG. Operation is such that the TREG is loaded
whenever the cell is not selected. Therefore, TREG is loaded
every clock except the clock following cell selection. The
purpose of the TREG is to hold the result of a sum of products
calculation during the clock when the accumulator is cleared
to prepare for the next sum of products calculation. This
allows continuous accumulation without wasting clocks.
The accumulator is loaded with the adder output every clock
unless it is cleared. It is cleared synchronously in two ways.
When RESET and ERASE are both low, the accumulator is
cleared along with all other registers on the device. Since
ERASE and RESET are latched and delayed one clock
internally, clearing occurs on the second CLK following the
onset of both ERASE and RESET low.
The second accumulator clearing mechanism clears a single
accumulator in a selected cell. The cell select signal, CELLn,
6
HSP43881
DCM1.D
DCM0.D
RESET.D
CIENB.D
TCCI
THREE-STATE BUFFERS
ON CELL 7 ONLY
C.TCCI
LD CLR
C REG
LD CLR
D1 REG
LD CLR
D2 REG
LD CLR
D3 REG
1
1
C0-7
0-7
7
TCCO
CIN0-7
MUX
MUX
D.TCCI
D0-7
CLK
CLK
CLK
COUT0-7
0
0
C0-8
B
RESET.D
DIENB.D
COENB
LD CLR
X REG
TCS
C
X0-8
7
MULTIPLIER
CORE
X
DIN0-7
P0-17
CLK
MREG0
CLR
LATCHES
RESET.D
CLK
DCM1
DCM0
RESET
DIENB
CIENB
ADR0
DCM1.D
DCM0.D
RESET.D
DIENB.D
CIENB.D
ADR0.D
ADR1.D
ADR2.D
ERASE.D
MREG1
CLR
ADR1
0-17 SIGN EXTENSION
18-25
ACC.D0-25
ADR2
ERASE
ADDER
CLK
ACC0-25
CLK
ERASE.D
CELLn
ACC
CLR
ADR0
ADR1
ADR2
CELL 0
CELL 1
DECODER
T REG
LD
CELLn
CLK
D
Q
CELL 7
AOUT0-25
FIGURE 1. FILTER CELL
7
HSP43881
0
1
6
7
26
26
26
26
3
CELL RESULT
MUX
ADR0.D-ADR2.D
0-18
18
SIGN EXT
18-25
8
26
RESET.D
CLR
18 (LSBs)
0-17
+
26
SHADD
SHADD.D
ZERO
MUX
RESET.D
D
Q
OUTPUT
BUFFER
CLK
0
1
26
26
8-25
18
CLK
0
18 MSBs SHIFTED
8 BITS TO RIGHT
(BITS 0 - 17)
1
0
OUTPUT
MUX
RESET.D
26
CLR
Q
2
SENBL
SENBH
THREE-STATE
BUFFER
D
26
CLK
SUM0-25
FIGURE 2. DF OUTPUT STAGE
The 26 least significant bits (LSBs) from either a cell
accumulator or the output buffer are output on the SUM0-25
bus. The output mux determines whether the cell
accumulator selected by ADR0-2 or the output buffer is
output to the bus. This mux is controlled by the SHADD input
signal. Control is based on the state of the SHADD during
two successive clocks; in other words, the output mux
selection contains memory. If SHADD is low during a clock
cycle and was low during the previous clock, the output mux
selects the contents of the filter cell accumulator addressed
by ADR0-2. Otherwise the output mux selects the contents
of the output buffer.
The SUM0-25 output bus is controlled by the SENBH and
SENBL signals. A low on SENBL enables bits SUM0-15. A
low on SENBH enables bits SUM16-25. Thus, all 26 bits can
be output simultaneously if the external system has a 26-bit
or larger bus. If the external system bus is only 16 bits, the
bits can be enabled in two groups of 16 and 10 bits (sign
extended).
DF Arithmetic
Both data samples and coefficients can be represented as
either unsigned or two's complement numbers. The TCS and
TCCI inputs determine the type of arithmetic representation.
Internally all values are represented by a 9-bit two's
complement number. The value of the additional ninth bit
depends on the arithmetic representation selected. For two's
complement arithmetic, the sign is extended into the ninth
bit. For unsigned arithmetic, bit-9 is 0.
If the ADR0-2 lines remain at the same address for more
than one clock, the output at SUM0-25 will not change to
reflect any subsequent accumulator updates in the
addressed cell. Only the result available during the first clock
when ADR0-2 selects the cell will be output. This does not
hinder normal FIR operation since the ADR0-2 lines are
changed sequentially. This feature facilitates the interface
with slow memories where the output is required to be fixed
for more than one clock.
The multiplier output is 18 bits and the accumulator is 26
bits. The accumulator width determines the maximum
possible number of terms in the sum of products without
8
HSP43881
overflow. The maximum number of terms depends also on
For practical FIR filters, the coefficients are never all near
maximum value, so even larger vectors are possible in
practice.
the number system and the distribution of the coefficient and
data values. Then maximum numbers of terms in the sum
products are:
Basic FIR Operation
MAX #
A simple, 30MHz 8-tap filter example serves to illustrate
more clearly the operation of the DF. The sequence table
(Table 1) shows the results of the multiply accumulate in
each cell after each clock. The coefficient sequence, Cn,
enters the DF on the left and moves from left to right through
the cells. The data sample sequence, Xn, enters the DF from
the top, with each cell receiving the same sample
NUMBER SYSTEM
Two Unsigned Vectors
OF TERMS
1032
Two Two's Complement:
• Two Positive Vectors
2080
2047
• Negative Vectors
• One Positive and One Negative Vector
2064
simultaneously. Each cell accumulates the sum of products
for one output point. Eight sums of products are calculated
simultaneously, but staggered in time so that a new output is
available every system clock.
One Unsigned and One Two's Complement
Vector:
• Positive Two's Complement Vector
1036
1028
• Negative Two's Complement Vector
TABLE 1. 30MHz, 8-TAP FIR FILTER SEQUENCE
X ...X
X
...X
X
X
1, 0
15
9, 8,
7
HSP43881
C ...C
C
C ...C
6,
C
Y
...Y ...Y
15 14,
Y
8, 7
0
6, 7,
0
7
CLK
0
CELL 0
x X
CELL 1
CELL 2
CELL 3
CELL 4
CELL 5
CELL 6
CELL 7
SUM/CLR
C
0
0
0
-
7
0
1
+C x X
C
x X
1
0
0
-
6
1
2
3
4
5
6
7
7
2
+C x X
+C x X
C
x X
2
0
-
5
6
2
3
4
7
3
+C x X
+C x X
+C x X
C
x X
3
-
4
5
6
3
4
7
4
+C x X
+C x X
+C x X
+C x X
C
x X
4
-
3
4
5
6
4
5
7
5
+C x X
C
x X
+C x X
+C x X
+C x X
C
x X
5
-
2
3
5
4
5
5
6
5
6
7
6
+C x X
+C x X
+C x X
+C x X
+C x X
+C x X
C
x X
6
-
1
2
6
7
8
3
6
4
6
5
6
6
7
7
7
+C x X
+C x X
+C x X
+C x X
+C x X
+C x X
+C x X
C
x X
7
Cell 0 (Y7)
Cell 1 (Y8)
Cell 2 (Y9)
Cell 3 (Y10)
Cell 4 (Y11)
Cell 5 (Y12)
Cell 6 (Y13)
Cell 7 (Y14)
Cell 0 (Y15)
0
1
2
7
3
7
4
7
5
6
7
7
8
C
x X
+C x X
+C x X
+C x X
+C x X
+C x X
+C x X
+C x X
6
7
8
0
1
8
2
8
3
8
4
8
5
8
8
9
+C x X
C
x X
+C x X
+C x X
+C x X
+C x X
+C x X
+C x X
5
6
9
7
9
0
9
1
9
2
9
3
9
4
9
9
10
11
12
13
14
15
+C x X
+C x X
C x X
+C x X
+C x X
+C x X
+C x X
+C x X
4
5
10
11
12
13
14
15
6
10
11
12
13
14
15
7
10
0
10
1
10
2
10
11
12
3
10
11
12
13
14
15
10
11
12
13
14
+C x X
+C x X
+C x X
C x X
+C x X
+C x X
+C x X
+C x X
3
4
5
6
11
12
13
14
15
7
11
0
11
1
2
+C x X
+C x X
+C x X
+C x X
C x X
+C x X
+C x X
+C x X
2
3
4
5
6
12
13
14
15
7
12
0
1
+C x X
+C x X
+C x X
+C x X
+C x X
C
x X
+C x X
+C x X
1
2
3
4
5
6
13
14
15
7
13
0
+C x X
+C x X
+C x X
+C x X
+C x X
+C x X
+C x X
+C x X
0
1
2
3
4
5
6
14
7
+C x X
+C x X
1
+C x X
+C x X
+C x X
+C x X
+C x X
C x X
7 15
0
2
3
4
5
15
6
9
HSP43881
SAMPLE
DATA IN
(X )
n
3-BIT
COUNTER
30MHz
+5V
CLOCK
Y
Y
Y
1 0
2
ADR2 ADR1 ADR0
V
SHADD SENBH SENBL
CC
8
DIN0-7
DIENB
TCS
SUM
OUT
26
SUM0-25
(Y )
n
HSP43881
TCCO
NC
NC
CLK
A2 A1 A0
D0-D7
TCCI
8
COUT0-7
COENB
8
CIN0-7
8 x 8 COEFF.
RAM/ROM
CIENB DCM1 DCM0 RESET ERASE
V
SS
SYSTEM
RESET
ERASE
FIGURE 3. 30MHZ, 8 TAP FIR FILTER APPLICATION SCHEMATIC
Detailed operation of the DF to perform a basic 8-tap, 8-bit
coefficient, 8-bit data, 30MHz FIR filter is best understood by
observing the schematic (Figure 3) and timing diagram
(Figure 4). The internal pipeline length of the DF is four (4)
clock cycles, corresponding to the register levels CREG (or
XREG), MREG0, MREG1, and TREG (Figures 1 and 2).
Therefore, the delay from presentation of data and
coefficients at the DIN0-7 and CIN0-7 inputs to a sum
appearing at the SUM0-25 output is:
Extended FIR Filter Length
Filter lengths greater that eight taps can be created by either
cascading together multiple DF devices or “reusing” a single
device. Using multiple devices, an FIR filter of over 1000-
taps can be constructed to operate at a 30MHz sample rate.
Using a single device clocked at 30MHz, a FIR filter of over
1000 taps can be constructed to operate at less than a
30MHz sample rate. Combinations of these two techniques
are also possible.
k + Td
Where:
k = filter length
Td = 4, the internal pipeline delay of DF
After the pipeline has filled, a new output sample is available
every clock. The delay to last sample output from last
sample input is Td.
The output sums, Yn, shown in the Timing Diagram are
derived from the sum of products equation:
Y(n) = C(0) x X(n) + C(1) x X(n1) + C(2) x X(n -2) + C(3)
x X(n -3) + C(4) x X(n -4) + C(5) x X(n -5) + C(6) x X(n -6)
+ C(7) x X(n -7)
10
HSP43881
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
CLK
RESET
ERASE
X
X
X
C
X
X
X
X
C
X
X
C
X
C
X
X
X
X
X
X
X
X
X
17 18
DIN0-7
DIENB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
5
CIN0-7
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
CIENB
ADR0-2
0
1
2
3
4
5
6
7
0
Y
Y
Y
Y
Y
Y
Y
Y
13 14
SUM0-24
SHADD
7
8
9
10
11
12
SENBL
SENBH
DCM0-1
0
7
Y
=
C
× X
∑
N
K
N – K
K = 0
FIGURE 4. 30MHz, 8-TAP FIR FILTER TIMING
11
SAMPLE
DATA IN
(X )
n
C
D
Q
Q
30MHz
CLOCK
2
+5V
+5V
ADR1 ADR0 ADR2
V
SHADD SENBH SENBL
SUM0-24
ADR1 ADR0 ADR2
V
SHADD SENBH SENBL
SUM0-24
CC
CC
25
8
25
8
DIN0-7
DIENB
TCS
DIN0-7
DIENB
TCS
HSP43881
DF0
HSP43881
DF1
8
TCCO
NC
NC
CLK
CLK
8x16 COEFF.
RAM/ROM
CLK
TCCI
TCCO
TCCI
Y0
A0
8
8
8
D0-D7
A1
CIN0-7
COUT0-7
CIN0-7
COUT0-7
COENB
4-BIT
COUNTER
Y1
Y2
Y3
A2
A3
CIENB DCM1 DCM0 RESET ERASE
V
COENB
CIENB DCM1 DCM0 RESET ERASE V
SS
SS
RESET
SUM
OUT
SYSTEM
RESET
(Y )
n
FIGURE 5. 30MHz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC
HSP43881
Extended Coefficient and Data Sample
Cascade Configuration
Word Size
To design a filter length L>8, L/8 DFs are cascaded by
connecting the COUT0-7 outputs of the (i)th DF to the CIN0-
7 inputs of the (i+1)th DF. The DIN0-7 inputs and SUM0-25
outputs of all the DFs are also tied together. A specific
example of two cascaded DFs illustrates the technique
(Figure 5). Timing (Figure 6) is similar to the simple 8-tap
FIR, except the ERASE and SENBL/SENBH signals must be
enabled independently for the two DFs in order to clear the
correct accumulators and enable the SUM0-25 output
signals at the proper times.
The sample and coefficient word size can be extended by
utilizing several DFs in parallel to get the maximum sample
rate or a single DF with resulting lower sample rates. The
technique is to compute partial products of 8 x 8 and
combine these partial products by shifting and adding to
obtain the final result. The shifting and adding can be
accomplished with external adders (at full speed) or with the
DF's shift and add mechanism contained in its output stage
(at reduced speed).
Single DF Configuration
Decimation/Resampling
Using a single DF, a filter of length L>8 can be constructed
by processing in L/8 passes as illustrated in the following
table (Table 2) for a 16-tap FIR. Each pass is composed of
Tp = 7 + L cycles and computes eight output samples. In
pass i, the sample with indices i*8 to i*8 +(L1) enter the
The HSP43881 DF provides a mechanism for decimating by
factors of 2, 3, or 4. From the DF filter cell block diagram
(Figure 1), note the three D registers and two multiplexers in
the coefficient path through the cell. These allow the
coefficients to be delayed by 1, 2, or 3 clocks through the
cell. The sequence table (Table 3) for a decimate by two filter
illustrates the technique (internal cell pipelining ignored for
simplicity).
DIN0-7 inputs. The coefficients C -C
enter the CIN0-7
0
L -1
inputs, followed by seven zeros. As these zeros are entered,
the result samples are output and the accumulators reset.
Initial filing of the pipeline is not shown in this sequence
table. Filter outputs can be put through a FIFO to even out
the sample rate.
Detailed timing for a 30MHz input sample rate, 15MHz
output sample rate (i.e., decimate by two), 16-tap FIR filter,
including pipelining, is shown in Figure 7. This filter requires
only a single HSP43881 DF.
13
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
0
1
2
3
4
5
CLK
RESET
DF0 ERASE
DF1 ERASE
DIN0-7
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X X X X X X X
31 32 33 34 35 36 37
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14 15 16 17 18 19 20
21 22 23 24 25 26 27 28 29 30
DIENB
CIN0-7
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C C C C C C
15 14 13 12 11 10
15
14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
8
CIENB
ADR0-2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
Y
Y Y
31 32 33
Y
Y
Y
Y
Y
Y
Y
Y
DF0 SUM0-25
DF1 SUM0-25
SHADD
15 16 17 18 19 20
21 22
Y
Y
Y
Y
Y
Y Y Y
27 28 29 30
23 24 25 26
DF0 SENBL/H
DF1 SENBL/H
DCM0-1
0
15
Y
=
C
× X
K N – K
∑
N
K = 0
FIGURE 6. 16-TAP 30MHz FIR FILTER TIMING USING TWO CASCADED HSP43881s
HSP43881
TABLE 2. 16-TAP FIR FILTER SEQUENCE USING A SINGLE DF
Data
Sequence
Input
X
...X , X
30
X
...X
X
1, 0
9
8, 22
Coefficient
Sequence
Input
HSP43881
CELL 4
C ...C , C
14 15,
0...0, C ...C
0
C
...0, Y ...Y
30 23,
0...0, Y ...Y
22,
0...0
15,
0
14, 15
CLK
6
CELL 0
CELL 1
CELL 2
CELL 3
CELL 5
CELL 6
CELL 7
SUM/CLR
C
x X
0
0
0
0
0
0
-
15
0
7
+C x X
C
x X
-
14
1
2
3
4
5
15
1
8
+C x X
C
x X
2
-
13
15
9
+C x X
C
x X
3
-
12
15
10
11
12
13
14
15
16
17
18
19
20
21
22
+C x X
+C x X
C
x X
4
-
11
14
4
5
6
7
8
15
+C x X
+C x X
C
x X
5
-
10
13
15
+C x X
+C x X
C
x X
-
9
6
12
15
6
+C x X
+C x X
C
C
C
x X
x X
x X
-
8
7
11
15
14
13
7
+C x X
+C x X
-
7
8
10
+C9 x X
8
+C x X
-
6
9
9
9
+C x X
+C x X
C
C
C
x X
x X
x X
-
5
10
11
12
13
14
15
8
10
11
12
13
14
15
16
12
11
10
10
11
12
13
14
15
16
+C x X
+C x X
-
4
7
+C x X
+C x X
-
3
6
+C x X
+C x X
C
x X
x X
x X
x X
-
2
5
9
8
7
6
+C x X
+C x X
C
-
1
4
+C x X
0
+C x X
C
C
CELL 0 (Y15)
CELL 1 (Y16)
3
0
+C x X
2
+C x X
0
16
23
24
25
26
27
28
0
0
0
0
0
0
0
0
0
0
0
0
C
x X
17
+C x X
C
C
x X
x X
CELL 2 (Y17)
CELL 3 (Y18)
CELL 4 (Y19)
CELL 5 (Y20)
CELL 6 (Y21)
CELL 7 (Y22)
0
1
17
5
17
18
19
20
21
22
0
0
0
0
0
+C x X
0
18
4
C
x X
19
0
C x X
3
0
C
x X
20
0
0
0
C
x X
x X
0
0
0
0
2
1
C x X
0
0
0
C
21
0
C x X
0
15
HSP43881
TABLE 2. 16-TAP FIR FILTER SEQUENCE USING A SINGLE DF (Continued)
Data
Sequence
Input
X
...X , X
30
X
...X
X
1, 0
9
8, 22
Coefficient
Sequence
Input
HSP43881
C ...C , C
14 15,
0...0, C ...C
0
C
...0, Y ...Y
30 23,
0...0, Y ...Y
22,
0...0
15,
0
14, 15
CLK
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
CELL 0
CELL 1
CELL 2
CELL 3
CELL 4
CELL 5
CELL 6
CELL 7
SUM/CLR
C
x X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
15
8
0
0
0
+C x X
C
x X
0
-
14
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
15
9
0
+C x X
+C x X
15 10
0
-
13
+C x X
-
12
+C x X
C
x X
12
-
11
15
+C x X
C
x X
15 13
-
10
+C x X
C
x X
15 14
-
9
+C x X
C
C
C
C
C
C
x X
x X
x X
x X
x X
x X
-
8
15
14
13
12
11
10
15
16
17
18
19
20
21
22
23
24
+C x X
-
7
+C x X
-
6
+C x X
-
5
+C x X
-
4
+C x X
-
3
+C x X
C
x X
x X
x X
x X
-
2
9
8
7
6
+C x X
C
-
1
+C x X
0
C
C
CELL 0 (Y23)
CELL 1 (Y24)
0
C
x X
24
0
46
47
0
0
0
0
C
x X
0
C
x X
CELL 2 (Y25)
CELL 3 (Y26)
0
25
C
x X
5
25
0
26
C x X
4
26
48
0
0
0
C x X
C
x X
CELL 4 (Y27)
0
27
3
27
16
HSP43881
TABLE 3. 16-TAP DECIMATE BY TWO FIR FILTER SEQUENCE; 30MHz IN, 15MHz OUT
Data
Sequence ...X , X
X
0
2
1,
Input
Coefficient
Sequence
Input
HSP43881
...C , C , ...C
15
C
, C
...Y , -, ...Y -, Y
19 17, 15
0
13, 14 15
CLK
6
CELL 0
x X
CELL 1
CELL 2
CELL 3
CELL 4
CELL 5
CELL 6
CELL 7
SUM/CLR
C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
15
0
7
+C x X
14
-
1
2
3
4
5
8
+C x X
13
C
x X
-
15
2
9
+C x X
12
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
+C x X
11
C
x X
-
15
4
+C x X
-
10
+C x X
C
x X
6
-
9
6
15
+C x X
-
8
7
+C x X
C
x X
8
-
7
8
15
+C x X
-
6
9
+C x X
C x X
15 10
-
5
10
11
12
13
14
15
16
+C x X
-
4
+C x X
C
x X
-
3
15 12
+C x X
-
2
+C x X
C
x X
-
1
15 14
+C x X
+C x X
14
CELL 0 (Y15)
0
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
C
x X
+C x X
13
-
15
+C x X
+C x X
12
CELL 1 (Y17)
14
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
+C x X
+C x X
11
-
13
+C x X
+C x X
10
CELL 2 (Y19)
12
+C x X
+C x X
-
11
9
+C x X
+C x X
CELL 3 (Y21)
10
8
+C x X
+C x X
-
9
7
+C x X
+C x X
CELL 4 (Y23)
8
6
+C x X
+C x X
-
7
5
+C x X
+C x X
CELL 5 (Y25)
6
4
+C x X
+C x X
-
5
3
+C x X
+C x X
CELL 6 (Y27)
4
2
+C x X
+C x X
-
3
1
+C x X
+C x X
CELL 7 (Y29)
-
2
0
+C x X
C
x X
1
15
+C x X
14 31
+C x X
14 31
+C x X
14 31
+C x X
14 31
+C x X
14 31
+C x X
14
31
+C x X
+C x X
CELL 8 (Y31)
0
14 31
17
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
0
1
2
3
4
5
CLK
RESET
ERASE
X
X
X
X
X
X
X
X
X
X
X X X X X X X X X X X X X X X X X X X X X X X X X X X X
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
DIN0-7
0
1
2
3
4
5
6
7
8
9
8
DIENB
CIN0-7
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C C C C C C
15 14 13 12 11 10
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CIENB
ADR0-2
0
1
2
3
4
5
6
7
0
1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
33
SUM0-25
SHADD
15
17
19
21
23
25
27
29
31
8
SENBL
SENBH
DCM0-1
1
FIGURE 7. 16-TAP DECIMATE-BY-TWO FIR FILTER TIMING; 30MHz, 15MHz OUT
HSP43881
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V
Input, Output Voltage . . . . . . . . . . . . . . . . . . . GND -0.5 to V 0.5V
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1
Thermal Resistance (Typical, Note 1)
PLCC Package . . . . . . . . . . . . . . . . . .
PGA Package . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
θ
( C/W)
θ
( C/W)
JA
JC
34
36
N/A
7
CC
o
PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Maximum Storage Temperature Range. . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
Operating Conditions
o
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%
o
o
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
o
(PLCC - Lead Tips Only)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17,763 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
PARAMETER
SYMBOL
NOTES
TEST CONDITIONS
= Max
MIN
MAX
UNITS
Power Supply Current
I
Notes 2, 4
V
-
140
mA
CCOP
CC
CLK Frequency 20MHz
Standby Power Supply Current
Input Leakage Current
Output Leakage Current
Logical One Input Voltage
Logical Zero Input Voltage
Logical One Output Voltage
Logical Zero Output Voltage
Clock Input High
I
Note 4
V
V
V
V
V
= Max
-
-10
-10
2.0
-
500
10
10
-
µA
µA
µA
V
CCSB
CC
CC
CC
CC
CC
I
= Max, Input = 0V or V
= Max, Input = 0V or V
= Max
I
CC
I
O
CC
V
IH
V
= Min
0.8
-
V
IL
V
I
I
= 400µA, V
= Min
= Min
2.6
-
V
OH
OH
CC
V
= 2mA, V
CC
0.4
-
V
OL
OL
V
V
V
= Max
= Min
3.0
-
V
IHC
CC
CC
Clock Input Low
V
0.8
V
ILC
Input Capacitance PLCC
PGA
C
Note 3
CLK Frequency 1MHz
All measurements referenced to
-
10
15
pF
pF
IN
GND
Output CapacitancePLCC
PGA
C
-
10
15
pF
pF
o
OUT
T = 25 C
A
NOTES:
2. Operating supply current is proportional to frequency. Typical rating is 7mA/MHz.
3. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.
4. Output load per test load circuit and C = 40pF.
L
19
HSP43881
o
o
AC Electrical Specifications
V
= 5V ±5%, T = 0 C to + 70 C
CC
A
-20 (20MHz)
-25 (25.6MHz)
-30 (30MHz)
PARAMETER
TEST CONDITIONS
SYMBOL
NOTES
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
ns
Clock Period
t
t
t
50
20
20
16
0
-
-
39
16
16
14
0
-
-
33
13
13
13
0
-
-
CP
CL
CH
Clock Low
ns
Clock High
-
-
-
ns
Input Setup
t
-
-
-
ns
IS
IH
Input Hold
t
-
-
-
ns
CLK to Coefficient Output Delay
Output Enable Delay
Output Disable Delay
CLK to SUM Output Delay
Output Rise
t
t
t
t
-
24
20
20
27
6
-
20
15
15
25
6
-
18
15
15
21
6
ns
ODC
OED
ODD
ODS
-
-
-
ns
Note 5
-
-
-
ns
-
-
-
ns
t
t
Note 5
Note 5
-
-
-
ns
OR
OF
Output Fall
-
6
-
6
-
6
ns
NOTE:
5. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.
Test Load Circuit
S
1
DUT
(NOTE 6) C
L
I
1.5V
I
OL
±
OH
EQUIVALENT CIRCUIT
NOTES:
6. Includes stray and jig capacitance.
7. Switch S Open for I and I Tests.
CCOP
1
CCSB
20
HSP43881
Waveforms
4.0V
0.0V
2.0V
IS
t
CP
CLK
3.0V
t
t
IH
t
t
CL
CH
1.5V
1.5V
INPUT†
2.0V
CLK
2.0V
2.0V
0.0V
†
Input includes: DIN0-7, CIN0-7, DIENB, CIENB, ERASE,
RESET,DCM0-1, ADRO-2, TCS, TCCI, SHADD
FIGURE 8. CLOCK AC PARAMETERS
2.0V
FIGURE 9. INPUT SETUP AND HOLD
CLK
SUM0-25
2.0V
0.8V
t
t
ODC, ODS
1.5V
COUT0-7
TCCO
t
OR
t
OF
†
SUM-25, COUTO-7, TCCO are assumed not to be in high-
impedance state.
FIGURE 10. SUM0-25, COUT0-7, TCCO OUTPUT DELAYS
FIGURE 11. OUTPUT RISE AND FALL TIMES
SENBL
SENBH
COENB
DEVICE
UNDER
TEST
3.0V
0.0V
1.5V
1.5V OUTPUT
INPUT
1.5V
1.5V
t
t
ODD
OED
SUM0-25
COUT0-7
TCCO
1.7V
1.3V
NOTE: AC Testing: Inputs are driven at 3.0V for Logic and “1” and
0.0V for Logic “0”. Input and output timing measurements are made
at 1.5 for both a Logic “1” and “0”. CLK is driven at 4.0 and 0V and
measured at 2.0V.
HIGH
IMPEDANCE
HIGH
IMPEDANCE
FIGURE 12. OUTPUT ENABLE, DISABLE TIMING
FIGURE 13. AC TESTING INPUT, OUTPUT WAVEFORM
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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21
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