HSP43891GC-25_技术文档

HSP43891

Data Sheet

May 1999

File Number 2785.5

Digital Filter

Features

The HSP43891 is a video-speed Digital Filter (DF)

designed to efficiently implement vector operations such as

FIR digital filters. It is comprised of eight filter cells

cascaded internally and a shift and add output stage, all in

a single integrated circuit. Each filter cell contains a 9x9

two’s complement multiplier, three decimation registers and

a 26-bit accumulator. The output stage contains an

additional 26-bit accumulator which can add the contents of

any filter cell accumulator to the output stage accumulator

shifted right by 8-bits. The HSP43891 has a maximum

sample rate of 30MHz. The effective multiply-accumulate

(mac) rate is 240MHz.

• Eight Filter Cells

• 0MHz to 30MHz Sample Rate

• 9-Bit Coefﬁcients and Signal Data

• 26-Bit Accumulator per Stage

• Filter Lengths Over 1000 Taps

• Expandable Coefficient Size, Data Size and Filter Length

• Decimation by 2, 3 or 4

Applications

• 1-D and 2-D FIR Filters

• Radar/Sonar

The HSP43891 DF can be configured to process expanded

coefficient and word sizes. Multiple DFs can be cascaded

for larger filter lengths without degrading the sample rate or

a single DF can process larger filter lengths at less than

30MHz with multiple passes. The architecture permits

processing filter lengths of over 1000 taps with the

guarantee of no overflows. In practice, most filter

coefficients are less than 1.0, making even larger filter

lengths possible. The DF provides for 8-bit unsigned or

9-bit two’s complement arithmetic, independently

selectable for coefficients and signal data.

• Digital Video

• Adaptive Filters

• Echo Cancellation

• Complex Multiply-Add

- Sample Rate Converters

Ordering Information

TEMP.

o

PART NUMBER RANGE ( C)

PACKAGE

PKG. NO.

HSP43891VC-20

HSP43891VC-25

HSP43891VC-30

HSP43891JC-20

HSP43891JC-25

HSP43891JC-30

HSP43891GC-20

HSP43891GC-25

HSP43891GC-30

0 to 70

100 Lead MQFP Q100.14x20

84 Lead PLCC N84.1.15

85 Pin CPGA G85.A

Each DF ﬁlter cell contains three resampling or decimation

registers which permit output sample rate reduction at rates

1

of / , / or / the input sample rate. These registers also

2

3

4

provide the capability to perform 2-D operations such as

matrix multiplication and NxN spatial

correlations/convolutions for image processing applications.

85 Pin CPGA G85.A

Block Diagram

V

DIN0 - DIN8

9

CC

SS

DIENB

CIENB

5

DCM0 - 1

ERASE

DF

FILTER

CELL 0

DF

FILTER

CELL 1

DF

FILTER

CELL 2

DF

FILTER

CELL 3

DF

FILTER

CELL 4

DF

FILTER

CELL 5

DF

FILTER

CELL 6

DF

FILTER

CELL 7

9

CIN0 - 8

COUT0 - 8

COENB

RESET

CLK

ADRO - 2

26

5

26

3

MUX

26

RESET

CLK

ADR0, ADR1, ADR2

2

OUTPUT

STAGE

SHADD

SENBL

SENBH

2

26

SUM0 - 25

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

HSP43891

Pinout

85 PIN GRID ARRAY (PGA)

1

2

3

4

5

6

7

8

9

10

11

1

2

3

4

5

6

7

8

9

10

11

V

SS

L

A

B

RESET DIN7 DIN6 DIN3 DIN0 CIN8

COENB

CC

V

CC

SS

DCM1SUM23 SUM22 SUM21 SUM18 SUM14 V

SUM13

V

SUM11 SUM9

CC

SS

K

CIENB

V

COUT7 COUT8 ERASE DIN8 DIN1 DIN2

ALIGN

CIN7 CIN6 CIN4

CIN5 CIN3

CC

SENBH SUM24

V

SUM19

V

SUM15 SUM12 SUM10 SUM8 SUM6

SS

CC

SS

J

DIENB

DIN5 DIN4

C

D

E

COUT5 COUT6

V

SUM25

SUM20 SUM17 SUM16

SUM7

V

SS

CC

H

V

COUT3 COUT4

CIN2

CIN0

CC

ADR1 ADR0

SUM5 SUM4

G

F

SENBL

COUT1

V

COUT2

CIN1

SS

ADR2 DCM0 CLK

SUM1 SUM3 SUM2

HSP43891

TOP VIEW

PINS DOWN

BOTTOM VIEW

PINS UP

V

CC

F

SS COUT0 SHADD

SS

SUM0

SUM1

V

COUT0 SHADD

SUM0

V

SS

CC

E

G

ADR2 DCM0 CLK

ADR1 ADR0

SUM3 SUM2

COUT1

V

COUT2

CIN1 CIN0 SENBL

SS

D

H

J

SUM5 SUM4

V

CIN2

COUT3 COUT4

COUT5COUT6

CC

C

B

V

SUM25

SUM20 SUM17 SUM16

SUM7

SS

CC

ALIGN

DIENB DIN5 DIN4

CIN5 CIN3

K

SENBH SUM24

V

SUM19

V

SUM15 SUM12 SUM10 SUM8 SUM6

CC

SS

V

COUT7 COUT8 ERASE DIN8 DIN1 DIN2 CIENB CIN7 CIN6 CIN4

CC

A

L

DCM1 SUM23 SUM22 SUM21 SUM18 SUM14

SUM13

SUM11 SUM9

V

SS

CC

V

COENB

V

DIN7 DIN6 DIN3 DIN0 CIN8

V

SS

RESET

SS

CC

84 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)

11 10 9

8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

COUT6

COUT7

SUM23

SUM22

V

SS

CC

COUT8

COENB

SUM21

SUM20

SUM19

SUM18

V

CC

ERASE

RESET

DIENB

DIN8

DIN7

DIN6

DIN5

DIN4

DIN3

DIN2

V

SS

SUM17

SUM16

HSP43891

TOP VIEW

V

CC

SUM15

SUM14

SUM13

SUM12

V

SS

SUM11

SUM10

SUM9

SUM8

SUM7

DIN1

DIN0

CIENB

CIN8

V

CC

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

2

HSP43891

Pinout (Continued)

100 LEAD MQFP

TOP VIEW

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

80

COUT4

COUT5

1

2

DCM1

SUM24

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V

3

4

5

6

7

8

9

V

CC

SS

CC

SS

COUT6

COUT7

V

COUT8

COENB

V

SUM23

SUM22

V

SS

CC

V

SS

CC

SUM21

SUM20

SUM19

SUM18

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

CC

ERASE

RESET

DIENB

DIN8

DIN7

DIN6

DIN5

DIN4

DIN3

DIN2

DIN1

DIN0

CIENB

CIN8

V

CIN7

CIN6

V

SS

SUM17

SUM16

V

CC

SUM15

SUM14

SUM13

SUM12

V

SS

SUM11

SUM10

SUM9

SUM8

SUM7

NC

CC

SUM6

SS

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

3

HSP43891

Pin Description

SYMBOL

NUMBER

TYPE

NAME AND FUNCTION

V

B1, J1, A3, K4,

L7, A10, F10,

D11

+5 power supply input.

CC

V

A1, F1, E2, K3,

K6, L9, A11,

F11, J11

Power supply ground input.

SS

CLK

G3

I

The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz.

DIN0-8

A5-8, B5-7, C6,

C7

These nine inputs are the data sample input bus. Nine-bit data samples are synchronously loaded

through these pins to the X register of each ﬁlter cell of the DF simultaneously. The DIENB signal en-

ables loading, which is synchronous on the rising edge of the clock signal.

The data samples can be either 9-bit two’s complement or 8-bit unsigned values. For 9-bit two’s com-

plement values, DIN8 is the sign bit. For 8-bit unsigned values, DIN8 must be held at logical zero.

DIENB

CIN0-8

C5

I

A low on this input enables the data sample input bus (DIN0-8) to all the ﬁlter cells. A rising edge of the

CLK signal occurring while DIENB is low will load the X register of every ﬁlter cell with the 9-bit value

present on DIN0-8. A high on this input forces all the bits of the data sample input bus to zero; a rising

CLK edge when DIENB is high will load the X register of every ﬁlter cell with all zeros. This signal is

latched inside the device, delaying its effect by one clock internal to the device. Therefore it must be low

during the clock cycle immediately preceding presentation of the desired data on the DIN0-8 inputs. De-

tailed operation is shown in later timing diagrams.

A9, B9-11, C10,

C11, D10, E9,

E10

These nine inputs are used to input the 9-bit coefﬁcients. The coefﬁcients are synchronously loaded

into the C register of ﬁlter CELL0 if a rising edge of CLK occurs while CIENB is low. The CIENB signal

is delayed by one clock as discussed below.

The coefﬁcients can be either 9-bit two’s complement or 8-bit unsigned values. For 9-bit two’s comple-

ment values, CIN8 is the sign bit. For 8-bit unsigned values, CIN8 must be held at logical zero.

ALIGN PIN

CIENB

C3

B8

Used for aligning chip on socket or printed circuit board. This pin must be left as a no connect in circuit.

A low on this input enables the C register of every ﬁlter cell and the D (decimation) registers of every

ﬁlter cell according to the state of the DCM0-1 inputs. A rising edge of the CLK signal occurring while

CIENB is low will load the C register and appropriate D registers with the coefﬁcient data present at

their inputs. This provides the mechanism for shifting coefﬁcients from cell to cell through the device. A

high on this input freezes the contents of the C register and the D registers, ignoring the CLK signal.

This signal is latched and delayed by one clock internal to the DF. Therefore it must be low during the

clock cycle immediately preceding presentation of the desired coefﬁcient on the CIN0-8 inputs. Detailed

operation is shown in later timing diagrams.

COUT0-8 B2, B3, C1, D1,

O

These nine three-state outputs are used to output the 9-bit coefﬁcients from ﬁlter CELL7. These outputs

are enabled by the COENB signal low. These outputs may be tied to the CIN0-8 inputs of the same DF

to recirculate to coefﬁcients, or they may be tied to the CIN0-8 inputs of another DF to cascade DFs for

longer ﬁlter lengths.

E1, C2, D2, F2,

E3

COENB

DCM0-1

A2

I

A low on the COENB input enables the COUT0-8 outputs. A high on this input places all these outputs

in their high impedance state.

L1, G2

These two inputs determine the use of the internal decimation registers as follows:

DCM1

DCM0

DECIMATION FUNCTION

Decimation registers not used

0

1

0

1

0

1

One decimation register is used

Two decimation registers are used

Three decimation registers are used

The coefﬁcients pass from cell to cell at a rate determined by the number of decimation registers used.

When no decimation registers are used, coefﬁcients move from cell to cell on each clock. When one

decimation register is used, coefﬁcients move from cell to cell on every other clock, etc. These signals

are latched and delayed by one clock internal to the device.

4

HSP43891

Pin Description (Continued)

SYMBOL

NUMBER

TYPE

NAME AND FUNCTION

SUM0-25

F9, G9-G11,

H10, H11, J2,

J5-J7, J10, K2,

K5, K7-K11,

L2-L6, L8, L10,

L11

O

These 26 three-state outputs are used to output the results of the internal ﬁlter cell computations. Indi-

vidual ﬁlter cell results or the result of the shift and add output stage can be output. If an individual ﬁlter

cell result is to be output, the ADR0-2 signals select the ﬁlter cell result. The SHADD signal determines

whether the selected ﬁlter cell result or the output stage adder result is output. The signals SENBH and

SENBL enable the most signiﬁcant and least signiﬁcant bits of the SUM0-25 result respectively. Both

SENBH and SENBL may be enabled simultaneously if the system has a 26-bit or larger bus. However

individual enables are provided to facilitate use with a 16-bit bus.

SENBH

SENBL

ADR0-2

K1

E11

I

A low on this input enables result bits SUM16-25. A high on this input places these bits in their high

impedance state.

A low on this input enables result bits SUM0-15. A high on this input places these bits in their high im-

pedance state.

G1, H1, H2

These three inputs select the one cell whose accumulator will be read through the output bus (SUM0-

25) or added to the output stage accumulator. They also determine which accumulator will be cleared

when ERASE is low. These inputs are latched in the DF and delayed by one clock internal to the device.

If ADR0-2 remains at the same address for more than one clock, the output at SUM0-25 will not change

to reﬂect any subsequent accumulator updates in the addressed cell. Only the result available during

the ﬁrst clock, when ADR0-2 selects the cell, will be output. This does not hinder normal operation since

the ADR0-2 lines are changed sequentially. This feature facilitates the interface with slow memories

where the output is required to be ﬁxed for more than one clock.

SHADD

RESET

ERASE

F3

A4

B4

I

The SHADD input controls the activation of the shift and add operation in the output stage. This signal

is latched on chip and delayed by one clock internal to the device. Detailed explanation is given in the

DF Output Stage section.

A low on this input synchronously clears all the internal registers, except the cell accumulators It can

be used with ERASE to also clear all the accumulators simultaneously. This signal is latched in the DF

and delayed by one clock internal to the device.

A low on this input synchronously clears the cell accumulator selected by the ADR0-2 signals. If RESET

is also low simultaneously, all cell accumulators are cleared.

The C and D registers are enabled for loading by CIENB.

Loading is synchronous with CLK when CIENB is low. Note

Functional Description

The Digital Filter Processor (DF) is composed of eight ﬁlter

cells cascaded together and an output stage for combining

or selecting ﬁlter cell outputs (See Block Diagram). Each

ﬁlter cell contains a multiplier-accumulator and several

registers (Figure 1). Each 9-bit coefﬁcient is multiplied by a

9-bit data sample, with the result added to the 26-bit

accumulator contents. The coefﬁcient output of each cell is

cascaded to the coefﬁcient input of the next cell to its right.

that CIENB is latched internally. It enables the register for

loading after the next CLK following the onset of CIENB low.

Actual loading occurs on the second CLK following the onset

of CIENB low. Therefore CIENB must be low during the clock

cycle immediately preceding presentation of the coefﬁcient

on the CIN0-8 inputs. In most basic FIR operations, CIENB

will be low throughout the process, so this latching and delay

sequence is only important during the initialization phase.

When CIENB is high, the coefﬁcients are frozen.

DF Filter Cell

The C and D registers are cleared synchronously under control

of RESET, which is latched and delayed exactly like CIENB.

The output of the C register (C0-8) is one input to 9 x 9

multiplier.

A 9-bit coefﬁcient (CIN0-8) enters each cell through the C

register on the left and exits the cell on the right as signals

COUT0-8. With no decimation, the coefﬁcient moves directly

from the C register to the output, and is valid on the clock

following its entrance. When decimation is selected the

coefﬁcient exit is delayed by 1, 2 or 3 clocks by passing

through one or more decimation registers (D1, D2 or D3).

The other input to the 9 x 9 multiplier comes from the output

of the X register. This register is loaded with a data sample

from the device input signals DIN0-8 discussed above. The

X register is enabled for loading by DIENB. Loading is

synchronous with CLK when DIENB is low. Note that DIENB

is latched internally. It enables the register for loading after

the next CLK following the onset of DIENB low. Actual

loading occurs on the second CLK following the onset of

DIENB low; therefore, DIENB must be low during the clock

The combination of D registers through which the coefﬁcient

passes is determined by the state of DCM0 and DCM1. The

output signals (COUT0-8) are connected to the CIN0-8

inputs of the next cell to its right. The COENB input signal

enables the COUT0-8 outputs of the right most cell to the

COUT0-8 pins of the device.

5

HSP43891

cycle immediately preceding presentation of the data sample

The second accumulator clearing mechanism clears a single

accumulator in a selected cell. The cell select signal, CELLn,

decoded from ADR0-2 and the ERASE signal enable

clearing of the accumulator on the next CLK.

on the DIN0-8 inputs. In most basic FIR operations, DIENB

will be low throughout the process, so this latching and delay

sequence is only important during the initialization phase.

When DIENB is high, the X register is loaded with all zeros.

The ERASE and RESET signals clear the DF internal

registers and states as follows:

The multiplier is pipelined and is modeled as a multiplier core

followed by two pipeline registers, MREG0 and MREG1

(Figure 1). The multiplier output is sign extended and input as

one operand of the 26-bit adder. The other adder operand is

the output of the 26-bit accumulator. The adder output is

loaded synchronously into both the accumulator and the

TREG.

ERASE

RESET

CLEARING EFFECT

1

No clearing occurs, internal state remains

same.

1

0

1

0

RESET only active, all registers except ac-

cumulators are cleared, including the inter-

nal pipeline registers.

The TREG loading is disabled by the cell select signal,

CELLn, where n is the cell number. The cell select is decoded

from the ADR0-2 signals to generate the TREG load enable.

The cell select is inverted and applied as the load enable to

the TREG. Operation is such that the TREG is loaded

whenever the cell is not selected. Therefore, TREG is loaded

every clock except the clock following cell selection. The

purpose of the TREG is to hold the result of a sum-of-

products calculation during the clock when the accumulator is

cleared to prepare for the next sum-of-products calculation.

This allows continuous accumulation without wasting clocks.

ERASE only active, the accumulator

whose address is given by the ADR0-2 in-

puts is cleared.

Both RESET and ERASE active, all accu-

mulators as well as all other registers are

cleared.

The DF Output Stage

The output stage consists of a 26-bit adder, 26-bit register,

feedback multiplexer from the register to the adder, an output

multiplexer and a 26-bit three-state driver stage (Figure 2).

The accumulator is loaded with the adder output every clock

unless it is cleared. It is cleared synchronously in two ways.

When RESET and ERASE are both low, the accumulator is

cleared along with all other registers on the device. Since

ERASE and RESET are latched and delayed one clock

internally, clearing occurs on the second CLK following the

onset of both ERASE and RESET low.

The 26-bit output adder can add any ﬁlter cell accumulator

result to the 18 most signiﬁcant bits of the output buffer. This

result is stored back in the output buffer. This operation takes

place in one clock period. The eight LSBs of the output

buffer are lost. The ﬁlter cell accumulator is selected by the

ADR0-2 inputs.

The 18 MSBs of the output buffer actually pass through the

zero mux on their way to the output adder input. The zero

mux is controlled by the SHADD input signal and selects

either the output buffer 18 MSBs or all zeros for the adder

input. A low on the SHADD input selects zero. A high on the

SHADD input selects the output buffer MSBs, thus,

activating the shift-and-add operation. The SHADD signal is

latched and delayed by one clock internally.

6

HSP43891

DCM1.D

DCM0.D

RESET.D

CIENB.D

CLR

LD

THREE-STATE BUFFERS

ON CELL 7 ONLY

C REG

D1 REG

D2 REG

D3 REG

1

C0-8

CIN0-8

MUX

COUT0-8

CLK

D0-8

0

C0-8

RESET.D

DIENB.D

COENB

CLR

LD

C

X REG

X0-8

MULTI-

PLIER

CORE

DIN0-8

X

P0-17

CLK

MREG0

CLK

RESET.D

CLR

LATCHES

DCM1

DCM0

RESET

DIENB

CIENB

ADR0

DCM1.D

DCM0.D

RESET.D

DIENB.D

CIENB.D

ADR0.D

ADR1.D

ADR2.D

ERASE.D

MREG1

CLR

0-17

SIGN EXTENSION

ADR1

ACC.D0-25

ADR2

ERASE

ADDER

CLK

ACC0-25

ACC

CLR

ERASE.D

CELLn

CLK

CELL 0

CELL 1

ADR0

ADR1

ADR2

DE-

CODER

CELL 7

T REG

LD

D

Q

CELLn

CLK

AOUT0-25

FIGURE 1. HSP43891 DF FILTER CELL

7

HSP43891

The SUM0-25 output bus is controlled by the SENBH and

0

1

6

7

SENBL signals. A low on SENBL enables bits SUM0-15. A

low on SENBH enables bits SUM16-25. Thus, all 26 bits can

be output simultaneously if the external system has a 26-bit

or larger bus. If the external system bus is only 16 bits, the

bits can be enabled in two groups of 16 and 10 bits (sign

extended).

CELL RESULTS

26 26

3

CELL RESULT

MUX

ADR0.D - ADR2.D

0-18

18

DF Arithmetic

SIGN EXT

18-25

8

26

Both data samples and coefﬁcients can be represented as

either 8-bit unsigned or 9-bit two’s complement numbers.

The 9x9 bit multiplier in each cell expects 9-bit two’s

complement operands. The binary format of 8-bit two’s

complement is shown below. Note that if the most signiﬁcant

or sign bit is held at logical zero, the 9-bit two’s complement

multiplier can multiply 8-bit unsigned operands. Only the

upper (positive) half of the two’s complement binary range is

used.

18 (LSBs)

0-17

+

RESET.D

CLR

26

SHADD.D

ZERO

MUX

OUTPUT

BUFFER

CLK

8-25

Q

D

SHADD

0

1

RESET.D

26

18

CLK

0-17

0’s

The multiplier output is 18 bits and the accumulator is 26

bits. The accumulator width determines the maximum

possible number of terms in the sum of products without

overﬂow. The maximum number of terms depends also on

the number system and the distribution of the coefﬁcient and

data values. Then maximum numbers of terms in the sum

products are:

26 26

18 MSBs SHIFTED

8 BITS TO RIGHT

1

0

OUTPUT

MUX

RESET.D

26

CLR

CLK

MAXIMUM # OF TERMS

2

3-STATE

BUFFER

SENBL

SENBH

Q

D

NUMBER SYSTEM

Two Unsigned Vectors

8-BIT

9-BIT

1032

N/A

26

Two Two’s Complement Vectors

• Two Positive Vectors

• Negative Vectors

SUM0-25

2080

2047

2064

1032

1024

1028

FIGURE 2. HSP43891 DFP OUTPUT STAGE

The 26 least signiﬁcant bits (LSBs) from either a cell

• One Positive and One Negative

Vector

accumulator or the output buffer are output on the SUM0-25

bus. The output mux determines whether the cell

accumulator selected by ADR0-2 or the output buffer is

output to the bus. This mux is controlled by the SHADD input

signal. Control is based on the state of the SHADD during

two successive clocks; in other words, the output mux

selection contains memory. If SHADD is low during a clock

cycle and was low during the previous clock, the output mux

selects the contents of the ﬁlter cell accumulator addressed

by ADR0-2. Otherwise the output mux selects the contents

of the output buffer.

One Unsigned 8-Bit Vector and One

Two’s Complement Vector

• Positive Two’s Complement Vector

• Negative Two’s Complement Vector

1036

1028

1032

1028

For practical FIR ﬁlters, the coefﬁcients are never all near

maximum value, so even larger vectors are possible in

practice.

Basic FIR Operation

A simple, 30MHz 8-tap ﬁlter example serves to illustrate

more clearly the operation of the DF. The sequence table

(Table 1) shows the results of the multiply accumulate in

If the ADR0-2 lines remain at the same address for more

than one clock, the output at SUM0-25 will not change to

reﬂect any subsequent accumulator updates in the

addressed cell. Only the result available during the ﬁrst clock

when ADR0-2 selects the cell will be output.

each cell after each clock. The coefﬁcient sequence, C ,

N

enters the DF on the left and moves from left to right through

the cells. The data sample sequence, X , enters the DF

N

This does not hinder normal FIR operation since the ADR0-2

lines are changed sequentially. This feature facilitates the

interface with slow memories where the output is required to

be ﬁxed for more than one clock.

from the top, with each cell receiving the same sample

simultaneously. Each cell accumulates the sum of products

for one output point. Eight sums of products are calculated

simultaneously, but staggered in time so that a new output is

available every system clock.

8

HSP43891

TABLE 1. HSP43891 30MHz, 8-TAP FIR FILTER SEQUENCE

X

. . . X , X , X . . . X , X

9 8 7 1

15

0

. . . Y , Y . . . Y , Y

HSP43891

C

. . . C , C , C . . . C , C

6 7 0 6

15 14

8

7

0

7

CLK

0

CELL 0

x X

CELL 1

CELL 2

CELL 3

CELL 4

CELL 5

CELL 6

CELL 7

SUM/CLR

C

0

-

7

0

1

+C x X

C x X

7 1

6

1

2

3

4

5

6

7

2

+C x X

C x X

7 2

5

6

2

3

4

5

6

7

8

3

+C x X

C x X

7 3

4

5

6

3

4

+C x X

C x X

7 4

3

4

5

6

4

5

+C x X

C x X

7 5

2

3

4

5

6

5

6

+C x X

C x X

7 6

1

2

3

6

4

6

5

6

7

+C x X

C

x X

Cell 0 (Y )

7

0

1

2

7

3

7

4

7

5

6

7

8

C

x X

+C x X

Cell 1 (Y )

8

7

8

0

1

8

2

8

3

8

4

8

5

8

6

8

9

+C x X

C

x X

+C x X

Cell 2 (Y )

9

6

9

7

9

0

9

1

9

2

9

3

9

4

9

5

9

10

11

12

13

14

15

+C x X

C

x X

+C x X

Cell 3 (Y

Cell 4 (Y

Cell 5 (Y

Cell 6 (Y

Cell 7 (Y

Cell 0 (Y

)

5

10

11

12

13

14

15

6

10

11

12

13

14

15

7

10

0

10

1

10

2

10

11

12

3

10

11

12

13

14

15

4

10

11

12

13

14

10

11

12

13

14

15

+C x X

C

x X

+C x X

3

4

5

6

11

12

13

14

15

7

11

0

11

1

2

+C x X

C

x X

+C x X

2

3

4

5

6

12

13

14

15

7

12

0

1

+C x X

C

x X

+C x X

1

2

3

4

5

6

13

14

15

7

13

0

+C x X

0

1

2

3

4

5

6

14

7

+C x X

2

+C x X

C x X

7 15

0

1

3

4

5

15

6

SAMPLE

DATA IN (X )

N

3-BIT

COUNTER

30MHz

CLOCK

+5V

Y

0

2

1

ADR2 ADR1 ADR0 V

DIN0-8

SHADD SENBH SENBL

SUM0-25

CC

26

9

SUM

OUT (Y )

N

DIENB

CLK

A

0

2

1

HSP43891

D0-D8

9 x 8 COEFF.

RAM/ROM

9

CIN0-8

COUT0-8

COENB

NC

CIENB DCM1 DCM0 RESET ERASE V

SS

SYSTEM

RESET

ERASE

FIGURE 3. HSP43891 30MHz, 8-TAP FIR FILTER APPLICATION SCHEMATIC

9

HSP43891

Detailed operation of the DF to perform a basic 8-tap, 9-bit

length and Td = 4, the internal pipeline delay of the DF. After

the pipeline has ﬁlled, a new output sample is available

every clock. The delay to last sample output from last

coefﬁcient, 9-bit data, 30MHz FIR ﬁlter is best understood by

observing the schematic (Figure 3) and timing diagram

(Figure 4). The internal pipeline length of the DF is four (4)

clock cycles, corresponding to the register levels CREG (or

XREG), MREG0, MREG1, and TREG (Figures 1 and 2).

Therefore, the delay from presentation of data and

sample input is Td. The output sums, Y , shown in the

N

timing diagram are derived from the sum-of-products

equation.

7

Y

=

C

X

K N–K

Σ

coefﬁcients at the DIN0-8 and CIN0-8 inputs to a sum

appearing at the SUM0-25 output is: k + Td, where k = ﬁlter

N

K = 0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

CLK

RESET

ERASE

DIN0-8

X

17 18

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

DIENB

C

5

CIN0-8

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

CIENB

ADR0-2

SUM0-25

SHADD

SENBL

SENBH

DCM0-1

0

1

2

3

4

5

6

7

0

Y

13 14

7

8

9

10

11

12

0

FIGURE 4. HSP43891 30MHz, 8-TAP FIR FILTER TIMING

SAMPLE

D

Q

DATA IN (X )

N

C

Q

30MHz

CLOCK

+5V

ADR1

ADR2

SHADD

SENBL

ADR1

ADR2

SHADD

SENBL

ADR0

V

SENBH

ADR0

V

CC

SENBH

CC

26

9

DIN0-8

DIENB

SUM0-25

DIN0-8

DIENB

SUM0-25

CLK

HSP43891

DF0

HSP43891

DF1

9x16 COEFF

RAM/ROM

CLK

Y

A

0

1

2

3

0

1

2

3

D0-D8

4-BIT

CTR

NC

9

CIN0-8

COUT0-8

CIN0-8

COUT0-8

DCM1

CIENB

RESET

V

DCM1

CIENB

RESET

V

SS

RESET

DCM0

ERASE

COENB

DCM0

ERASE

COENB

SUM

OUT

(Y )

N

SYSTEM

RESET

FIGURE 5. HSP43891 30MHz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC

10

HSP43891

Cascade Conﬁguration

Extended FIR Filter Length Filter

lengths greater that eight taps can be created by either

cascading together multiple DF devices or “reusing” a single

device. Using multiple devices, an FIR ﬁlter of over 1000

taps can be constructed to operate at a 30MHz sample rate.

Using a single device clocked at 30MHz, an FIR ﬁlter of over

500 taps can be constructed to operate at less than a

30MHz sample rate. Combinations of these two techniques

are also possible.

To design a ﬁlter length L>8, L/8 DFs are cascaded by

connecting the COUT0-8 outputs of the (i)th DF to the CIN0-

8 inputs of the (i+1)th DF. The DIN0-8fs inputs and SUM0-25

outputs of all the DFs are also tied together. A speciﬁc

example of two cascaded DFs illustrates the technique

(Figure 5). Timing (Figure 6) is similar to the simple 8-tap

FIR, except the ERASE and SENBL/SENBH signals must be

enabled independently for the two DFs in order to clear the

correct accumulators and enable the SUM0-25 output

signals at the proper times.

TABLE 2.

DATA SEQUENCE INPUT X . . . X , X , X . . . X , X

30 22 0

9

8

1

. . . 0, Y . . . Y , 0. . . 0, Y . . . Y , 0. . . 0

HSP43891

COEFFICIENT SEQUENCE INPUT C . . . C , C , 0 . . . C . . . C , C

14 15

30

23

22

15

0

14 15

0

CLK

CELL 0

x X

CELL 1

CELL 2

CELL 3

CELL 4

CELL 5

CELL 6

CELL 7

SUM/CLR

6

7

8

9

C

0

-

15

0

+C x X

C

15

x X

14

1

2

3

4

5

1

+C x X

13

C

15

x X

2

+C x X

C

x X

12

15

3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

+C x X

11

+C x X

C

x X

4

14

4

5

6

7

8

15

+C x X

C

x X

10

+C x X

13

15

5

+C x X

C

x X

6

9

6

12

+C x X

15

+C x X

C

x X

8

7

11

15

7

+C x X

7

8

10

+C x X

14

8

9

+C x X

6

9

13

+C x X

5

10

11

12

13

14

15

8

10

11

12

13

14

15

16

17

18

12

10

11

12

13

14

15

16

17

18

19

20

21

22

+C x X

4

7

11

+C x X

3

6

10

+C x X

2

5

9

+C x X

1

4

8

+C x X

Cell 0 (Y

Cell 1 (Y

Cell 2 (Y

Cell 3 (Y

Cell 4 (Y

Cell 5 (Y

Cell 6 (Y

Cell 7 (Y

)

0

3

7

15

16

17

18

19

20

21

22

0

C

x X

16

+C x X

0

2

6

0

C

x X

17

+C x X

0

1

5

0

+C x X

0

4

0

C

x X

+C x X

0

19

3

0

C x X

0

+C x X

20

2

0

C

x X

21

+C x X

0

1

0

+C x X

0

C

x X

0

-

15

8

+C x X

15

14

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

9

0

+C x X

13

15 10

+C x X

15 11

12

+C x X

11

+C x X

15 12

+C x X

15

10

+C x X

12

+C x X

15 14

9

+C x X

C

x X

8

15

+C x X

7

14

16

17

18

19

20

21

22

23

24

25

26

27

+C x X

13

6

+C x X

5

12

+C x X

11

4

+C x X

3

10

+C x X

-

2

9

+C x X

1

8

+C x X

Cell 0 (Y

Cell 1 (Y

Cell 2 (Y

Cell 3 (Y

Cell 4 (Y

)

0

7

23

24

25

26

27

0

C

x X

0

+C x X

0

23

6

C

x X

0

+C x X

5

0

25

0

C

x X

0

+C x X

0

26

4

0

C

x X

+C x X

3

0

27

11

HSP43891

Single DF Conﬁguration

Decimation/Resampling

Using a single DF, a ﬁlter of length L>8 can be constructed

by processing in L/8 passes, as illustrated in Table 2, for a

16-tap FIR. Each pass is composed of Tp = 7 + L cycles and

computes eight output samples. In pass i, the sample with

indices i*8 to i*8 +(L-1) enter the DIN0-8 inputs. The

The HSP43891 DF provides a mechanism for decimating by

factors of 2, 3, or 4. From the DF ﬁlter cell block diagram

(Figure 1), note the three D registers and two multiplexers in

the coefﬁcient path through the cell. These allow the

coefﬁcients to be delayed by 1, 2, or 3 clocks through the

cell. The sequence table (Table 3) for a decimate-by-two

ﬁlter illustrates the technique (internal cell pipelining ignored

for simplicity). Detailed timing for a 30MHz input sample rate,

15MHz output sample rate (i.e., decimate-by-two), 16-tap

FIR ﬁlter, including pipelining, is shown in Figure 7. This ﬁlter

requires only a single HSP43891 DF.

coefﬁcients C - C - 1 enter the CIN0-8 inputs, followed by

0

L

seven zeros. As these zeros are entered, the result samples

are output and the accumulators reset. Initial ﬁling of the

pipeline is not shown in this sequence table. Filter outputs

can be put through a FIFO to even out the sample rate.

Extended Coefﬁcient and Data Sample

Word Size

The sample and coefﬁcient word size can be extended by

utilizing several DFs in parallel to get the maximum sample

rate or a single DF with resulting lower sample rates. The

technique is to compute partial products of 9 x 9 and

combine these partial products by shifting and adding to

obtain the ﬁnal result. The shifting and adding can be

accomplished with external adders (at full speed) or with the

DF’s shift-and-add mechanism contained in its output stage

(at reduced speed).

12

HSP43891

TABLE 3. HSP43891 16-TAP DECIMATE-BY-TWO FIR FILTER SEQUENCE; 30MHz IN, 15MHz OUT

DATA SEQUENCE INPUT . . . X , X , X

0

2

1

. . . Y , - ,Y , - , Y

19 17

HSP43891

COEFFICIENT SEQUENCE INPUT . . . C , C . . . C , C , C

15

0

13 14 15

CLK

6

CELL 0

x X

CELL 1

CELL 2

CELL 3

CELL 4

CELL 5

CELL 6

CELL 7

SUM/CLR

C

0

-

15

0

7

+C x X

14

0

1

2

3

4

5

8

+C x X

13

C

x X

0

15

2

9

+C x X

12

+C x X

0

14

3

4

5

6

7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

+C x X

11

+C x X

C

x X

4

0

13

15

+C x X

0

10

12

14

5

6

+C x X

C

x X

6

0

9

6

11

13

15

+C x X

0

8

7

10

12

7

14

7

8

+C x X

C

x X

8

0

7

8

9

8

11

8

13

15

+C x X

0

6

9

8

9

10

+C x X

9

12

9

14

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

+C x X

11

+C x X

13

C x X

15 10

0

5

10

11

12

13

14

15

16

7

10

11

12

13

14

15

16

17

18

9

10

11

12

13

14

15

16

17

18

19

20

10

11

12

13

14

15

16

17

18

19

20

21

22

+C x X

12

+C x X

14

0

4

6

8

10

11

12

13

14

15

+C x X

11

+C x X

13

C

x X

12

3

5

7

9

15

+C x X

12

+C x X

14

2

4

6

8

10

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

+C x X

11

+C x X

13

C x X

15 14

1

3

5

7

9

+C x X

12

+C x X

14

Cell0 (Y

)

0

2

4

6

8

10

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

15

17

19

21

23

25

27

29

31

C

x X

+C x X

11

+C x X

13

-

15

1

3

5

7

9

16

+C x X

10

+C x X

12

Cell1 (Y

14

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

0

2

4

6

8

17

18

19

20

21

22

23

24

25

+C x X

C

x X

+C x X

11

-

13

15

1

3

5

7

9

+C x X

10

Cell2 (Y

12

14

19

20

21

22

23

24

25

26

27

28

29

30

31

0

2

4

6

8

+C x X

C

x X

+C x X

-

11

13

15

1

3

5

7

9

+C x X

Cell3 (Y

10

12

14

21

22

23

24

25

26

27

28

29

30

31

0

2

4

6

8

+C x X

C

x X

+C x X

-

9

11

13

15

1

3

5

7

+C x X

Cell4 (Y

8

10

12

14

23

24

25

26

27

28

29

30

31

0

2

4

6

+C x X

15

+C x X

-

7

9

11

13

24

25

26

27

28

29

30

31

1

3

5

+C x X

12

+C x X

14

+C x X

Cell5 (Y

6

8

10

0

2

4

+C x X

11

+C x X

13

+C x X

15

+C x X

-

Cell6 (Y

-

5

7

9

26

27

28

29

30

31

1

3

+C x X

12

+C x X

14

+C x X

2

4

6

8

10

0

+C x X

11

+C x X

13

+C x X

15

+C x X

1

3

5

7

9

28

29

30

31

+C x X

10

+C x X

12

+C x X

14

+C x X

Cell7 (Y

-

2

4

6

8

0

+C x X

11

+C x X

13

C

x X

1

3

5

7

9

15

+C x X

31

+C x X

10

+C x X

12

Cell8 (Y

0

2

4

6

8

14

HSP43891

Absolute Maximum Ratings

Thermal Information

o

Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V

Input, Output Voltage . . . . . . . . . . . . . . . . .GND -0.5V to V +0.5V

Thermal Resistance (Typical, Note 1)

MQFP Package . . . . . . . . . . . . . . . . . . . .

PLCC Package. . . . . . . . . . . . . . . . . . . . .

CPGA Package . . . . . . . . . . . . . . . . . . . .

θ

( C/W)θ ( C/W)

JC

JA

47

37

34.66

N/A

7.78

CC

o

Maximum Storage Temperature. . . . . . . . . . . . . . . . -65 C to 150 C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1

Junction Temperature

o

Typical Package Power Dissipation at 70 C

o

PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C

MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.7W

PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2W

CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.88W

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17763

(PLCC MQFP Lead Tips Only)

o

CPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 C

o

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

Operating Conditions

Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5

o

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

JA

DC Electrical Speciﬁcations

PARAMETER

Power Supply Current

SYMBOL

TEST CONDITIONS

= Max, CLK Frequency 20MHz (Notes 2, 4)

= Max (Note 4)

MIN

MAX

140

500

10

-

UNITS

mA

µA

V

I

V

-

CCOP

CC

Standby Power Supply Current

Input Leakage Current

Output Leakage Current

Logical One Input Voltage

Logical Zero Input Voltage

Logical One Output Voltage

Logical Zero Output Voltage

Clock Input High

I

-

-10

2.0

-

CCSB

I

= Max, Input = 0V or V

= Max

I

CC

I

O

V

IH

V

= Min

0.8

-

V

IL

V

I

= -400µA, V

= Min

2.6

-

V

OH

OL

CC

V

= 2mA, V

CC

0.4

-

V

OL

V

= Max

= Min

3.0

-

V

IHC

CC

Clock Input Low

V

0.8

10

15

10

15

V

ILC

Input Capacitance

Output Capacitance

NOTES:

PLCC

C

CLK Frequency 1MHz

All measurements referenced to GND, T = 25 C

-

pF

IN

o

A

CPGA

PLCC

CPGA

-

(Note 3)

C

-

OUT

-

2. Operating supply current is proportional to frequency. Typical rating is 7mA/MHz.

3. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design

changes.

4. Output load per test load circuit and C = 40pF.

L

16

HSP43891

o

AC Electrical Speciﬁcations

V

= 5V, ±5%, T = 0 C to 70 C

CC

A

-20 (20MHz)

MIN MAX

50

-25 (25.6MHz)

-30 (30MHz)

MIN MAX

33

TEST

CONDITIONS

PARAMETER

Clock Period

SYMBOL

MIN

MAX

UNITS

ns

t

-

39

16

14

0

-

CP

Clock Low

t

20

16

0

-

13

0

-

ns

CL

Clock High

t

-

ns

CH

Input Setup

t

-

ns

IS

IH

Input Hold

t

-

ns

CLK to Coefficient Output Delay

Output Enable Delay

Output Disable Delay

CLK to SUM Output Delay

Output Rise

t

24

20

27

6

-

20

15

25

6

18

15

21

6

ns

ODC

t

-

ns

OED

ODD

t

Note 5

-

ns

t

-

ns

ODS

t

Note 5

-

ns

OR

Output Fall

t

-

6

-

6

-

6

ns

OF

NOTE:

5. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design

changes.

Test Load Circuit

S

1

DUT

† C

L

I

1.5V

I

OL

±

OH

(NOTE) INCLUDES STRAY

AND JIG CAPACITANCE

EQUIVALENT CIRCUIT

NOTE: Switch S Open for I

and I

Tests.

CCOP

1

CCSB

17

HSP43891

Waveforms

4.0V

0.0V

2.0V

CLK

3.0V

t

CP

t

IH

IS

t

CH

CL

INPUT†

0.0V

1.5V

2.0V

CLK

NOTE: Input includes:DIN0-7, CIN0-7, DIENB, CIENB, ERASE, RE-

SET, DCM0-1, ADR0-1, TCS, TCCI, SHADD

FIGURE 9. INPUT SETUP AND HOLD

FIGURE 8. CLOCK AC PARAMETERS

2.0

0.8

2.0V

CLK

t

, t

ODC ODS

t

OF

SUM0-25

COUT0-8

OR

1.5V

OUTPUT

FIGURE 10. SUM0-25, COUT0-8, OUTPUT DELAYS

FIGURE 11. RISE AND FALL TIMES

ENABLE

DEVICE

UNDER

TEST

3.0V

INPUT

0.0V

1.5V

t

OED

t

ODD

1.7V

1.3V

OUTPUT 1.5V

NOTE: AC Testing: Inputs are driven at 3.0V for a Logic “1” and 0.0V

for a Logic “0”. Input and output timing measurements are made at

1.5V for both a Logic “1” and “0”. CLK is driven at 4.0V and 0V and

measured at 2.0V.

FIGURE 12. OUTPUT ENABLE, DISABLE TIMING

FIGURE 13. AC TESTING INPUT, OUTPUT WAVEFORM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Ofﬁce Headquarters

NORTH AMERICA

EUROPE

ASIA

Intersil Corporation

Intersil SA

Mercure Center

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

Intersil (Taiwan) Ltd.

7F-6, No. 101 Fu Hsing North Road

Taipei, Taiwan

Republic of China

TEL: (886) 2 2716 9310

FAX: (886) 2 2715 3029

P. O. Box 883, Mail Stop 53-204

Melbourne, FL 32902

TEL: (407) 724-7000

FAX: (407) 724-7240

18


型号：	HSP43891GC-25
厂家：	Intersil
描述：	Digital Filter 数字滤波器外围集成电路 LTE 时钟
文件：	总18页 (文件大小：145K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HSP43891GC-25 [INTERSIL]

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