HSP43881883 [INTERSIL]
Digital Filter; 数字滤波器
| 型号： | HSP43881883 |
| 厂家： | 
Intersil |
| 描述： | Digital Filter |
| 文件： | 总7页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HSP43881/883
TM
Data Sheet
May 1999
FN2449.4
Digital Filter
Features
The HSP43881/883 is a video speed Digital Filter (DF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of eight filter cells cascaded
internally and a shift and add output stage, all in a single
integrated circuit. Each filter cell contains a 8 x 8-bit
multiplier, three decimation registers and a 26-bit
accumulator. The output stage contains an additional 26-bit
accumulator which can add the contents of any filter cell
accumulator to the output stage accumulator shifted right by
8-bits. The HSP43881/883 has a maximum sample rate of
25.6MHz. The effective multiply accumulate (mac) rate is
204MHz.
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• 0MHz to 25.6MHz Sample Rate
• Eight Filter Cells
• 8-Bit Coefficients and Signal Data
• Low Power CMOS Operation
• I
• I
500µA Maximum
CCSB
CCOP
160mA Maximum at 20MHz
• 26-Bit Accumulator Per Stage
• Filter Lengths Up to 1032 Taps
The HSP43881/883 DF can be configured to process
expanded coefficient and word sizes. Multiple DFs can be
cascaded for larger filter lengths without degrading the
sample rate or a single DF can process larger filter lengths
at less than 25.6MHz with multiple passes. The architecture
permits processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter coefficients
are less than 1.0, making even larger filter lengths possible.
The DF provides for 8-bit unsigned or two’s complement
arithmetic, independently selectable for coefficients and
signal data.
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
• 1-D and 2-D FIR Filters
• Radar/Sonar
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add
• Sample Rate Converters
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
1
1
1
of / , / or / the input sample rate. These registers also
2
3
4
Ordering Information
provide the capability to perform 2-D operations such as
matrix multiplication and N x N spatial correlations/convolutions
for image processing applications.
TEMP.
PKG.
NO.
o
PART NUMBER
RANGE ( C)
PACKAGE
HSP43881GM-25/883
-55 to 125 85 Ld PGA
G85.A
Block Diagram
V
V
CC
SS
DIN0 - DIN7 TCS
8
DIENB
CIENB
5
DCMO - 1
ERASE
8
8
8
8
8
8
8
8
TCCI
TCCO
DF
DF
DF
DF
DF
DF
DF
DF
FILTER
CELL 0
FILTER
CELL 1
FILTER
CELL 2
FILTER
CELL 3
FILTER
CELL 4
FILTER
CELL 5
FILTER
CELL 6
FILTER
CELL 7
8
8
8
8
8
8
8
8
8
CIN0 - 7
COUT0 - 7
COENB
RESET
CLK
26
26
26
26
26
26
26
5
5
26
3
ADR0 - 2
MUX
26
RESET
CLK
ADR0, ADR1, ADR2
2
OUTPUT
STAGE
SHADD
SENBL
SENBH
2
26
SUM0 - 25
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
HSP43881/883
Pinouts
85 PIN PGA
TOP VIEW, PINS DOWN
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
V
COENB
V
RESET
ERASE
DIN7
TCS
DIN6
DIN1
DIN3
DIN2
DIN0
CIENB
TCCI
CIN7
V
V
SS
SS
CC
CC
CC
V
COUT7 TCCO
ALIGN
CIN6
CIN4
CIN3
DIENB
COUT5 COUT6
DIN5
DIN4
CIN5
CIN2
CIN0
PIN
V
COUT3 COUT4
CC
SENBL
COUT1
COUT2
V
CIN1
SS
V
V
V
F
COUT0 SHADD
CC
SS
SS
SUM0
SUM1
G
ADR2
ADR1
DCM0
ADR0
CLK
SUM3
SUM5
SUM7
SUM8
SUM2
SUM4
H
J
V
V
SUM25
SUM24
SUM20 SUM17 SUM16
SS
CC
K
SENBH
V
SUM19
SUM15 SUM12 SUM10
SUM6
SUM9
V
V
SS
CC
SS
L
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14
SUM13
SUM11
V
V
SS
CC
2
HSP43881/883
Pinouts (Continued)
85 PIN PGA
BOTTOM VIEW, PINS UP
1
2
3
4
5
6
7
8
9
10
11
L
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14
SUM13
SUM11 SUM9
V
V
SS
CC
K
SENBH SUM24
SUM19
SUM15 SUM12 SUM10 SUM8
SUM6
V
V
V
SS
SS
CC
J
V
SUM25
ADR0
DCM0
SUM20 SUM17 SUM16
SUM7
SUM5
SUM3
V
CC
SS
H
ADR1
ADR2
SUM4
SUM2
G
F
CLK
SUM1
SUM0
CIN1
V
COUT0 SHADD
V
V
SS
CC
SS
E
D
COUT1
COUT2
V
SENBL
CIN0
CIN2
SS
V
COUT3 COUT4
COUT5 COUT6
CC
C
B
ALIGN
PIN
DIENB
DIN5
DIN4
CIN5
CIN6
CIN3
CIN4
COUT7 COUT8 ERASE TCS
DIN1
DIN6
DIN2
DIN3
CIENB
DIN0
CIN7
CIN8
V
CC
A
COENB
V
DIN7
V
V
V
RESET
SS
CC
CC
SS
NOTE: An overbar on a signal name represents an active LOW signal.
3
HSP43881/883
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V
Input, Output Voltage . . . . . . . . . . . . . . . . . . GND -0.5 to V +0.5V
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
CC
PGA Package. . . . . . . . . . . . . . . . . . . .
Maximum Package Power Dissipation at 125 C
36.0
7.0
o
PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.44W
o
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Operating Conditions
o
o
Maximum Storage Temperate Range . . . . . . . . . . . -65 C to 150 C
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17,762 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS
TEST
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
o
PARAMETER
SYMBOL
( C)
MIN
MAX
UNITS
Logical One Input
Voltage
V
V
V
= 5.5V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
-55 ≤ T ≤ 125
2.2
-
V
IH
CC
CC
A
Logical Zero Input
Voltage
V
= 4.5V
-55 ≤ T ≤ 125
-
0.8
-
V
V
IL
A
Output HIGH Voltage
Output LOW Voltage
Input Leakage Current
Output Leakage Current
V
I
= -400µA
= 4.5V (Note 2)
-55 ≤ T ≤ 125
2.6
-
OH
OH
A
V
CC
V
I
= -400mA
= 4.5V (Note 2)
-55 ≤ T ≤ 125
0.4
+10
+10
V
OL
OH
A
V
CC
I
V
V
= V
or GND
= 4.5V
-55 ≤ T ≤ 125
-10
-10
µA
µA
I
IN
CC
A
CC
I
V
V
= V
or GND
-55 ≤ T ≤ 125
A
O
IN
CC
= 5.5V
CC
Clock Input High
Clock Input Low
V
V
V
= 5.5V
= 4.5V
1, 2, 3
1, 2, 3
1, 2, 3
-55 ≤ T ≤ 125
3.0
-
V
V
IHC
CC
CC
A
V
-55 ≤ T ≤ 125
-
-
0.8
500
ILC
A
Standby Power Supply
Current
I
V
V
= V
or GND
-55 ≤ T ≤ 125
µA
CCSB
IN
CC
A
= 5.5V,
CC
Outputs Open
Operating Power Supply
Supply Current
I
f = 20.0MHz
1, 2, 3
7, 8
-55 ≤ T ≤ 125
-
-
160.0
-
mA
CCOP
A
V
= 5.5V (Note 3)
CC
Functional Test
NOTES:
FT
(Note 4)
-55 ≤ T ≤ 125
A
2. Interchanging of force and sense conditions is permitted.
3. Operating supply current is proportional to frequency, typical rating is 8.0mA/MHz.
4. Tested as follows: f = 1MHz, V = 2.6, V = 0.4, V ≥ 1.5V, V ≤ 1.5V, V = 3.4V and V = 0.4V.
ILC
IH IL OH OL
IHC
4
HSP43881/883
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
GROUP A
-25 (25.6MHz)
SUBGROUP
S
TEMPERATURE
o
PARAMETER
Clock Period
SYMBOL
NOTES
Note 5
Note 5
Note 5
Note 5
Note 5
Note 5
( C)
MIN
39
16
16
17
0
MAX
UNITS
ns
t
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
-
-
CP
A
Clock Low
Clock High
Input Setup
Input Hold
t
-55 ≤ T ≤ 125
ns
CL
A
t
-55 ≤ T ≤ 125
-
ns
CH
A
t
-55 ≤ T ≤ 125
-
ns
IS
IH
A
t
-55 ≤ T ≤ 125
-
ns
A
CLK to Coefficient
Output Delay
t
-55 ≤ T ≤ 125
-
20
ns
ODC
A
Output Enable Delay
t
t
Note 5
Note 5
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
-
-
15
25
ns
ns
OED
A
CLK TO SUM
Output Delay
-55 ≤ T ≤ 125
A
ODS
NOTE:
5. AC Testing: V
- 4.5V and 5.5V. Inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements are
CC
made at 1.5V for both a Logic “1” an”). CLK is driven at 4.0V and 0V and measured at 2.0V.
TABLE 3. AC ELECTRICAL PERFORMANCE SPECIFICATIONS
-25 (25.6MHz)
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
SYMBOL
NOTES
MIN
MAX
UNITS
Input Capacitance
C
VCC = Open, f = 1MHz
All measurements are
referenced to device GND
6
T
= 25
-
15
pF
IN
A
Output Capacitance
Output Disable Delay
Output Rise Time
Output Fall Time
NOTES:
C
6
T
= 25
-
-
-
-
15
15
6
pF
ns
ns
ns
OUT
A
t
6, 7
6, 7
6, 7
-55 ≤ T ≤ 125
A
ODD
t
t
-55 ≤ T ≤ 125
A
OR
OF
-55 ≤ T ≤ 125
6
A
6. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.
7. Loading is as specified in the test load circuit, C = 40pF.
L
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test
METHOD
100%/5004
100%/5004
100%
SUBGROUPS
-
Interim Test
PDA
-
1
Final Test
Group A
100%
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
-
Groups C and D
Samples/5005
5
HSP43881/883
Burn-In Circuit
BOTTOM VIEW, PINS UP
1
2
3
4
5
6
7
8
9
10
11
L
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14
SUM13
SUM11 SUM9
V
V
SS
CC
K
SENBH SUM24
SUM19
SUM15 SUM12 SUM10 SUM8
SUM6
V
V
V
SS
SS
CC
J
V
SUM25
ADR0
DCM0
SUM20 SUM17 SUM16
SUM7
SUM5
SUM3
V
CC
SS
H
ADR1
ADR2
SUM4
SUM2
G
F
CLK
SUM1
SUM0
CIN1
V
COUT0 SHADD
V
V
SS
CC
SS
E
D
COUT1
COUT2
V
CIN0
CIN2
SENBL
SS
V
COUT3 COUT4
COUT5 COUT6
CC
C
B
ALIGN
PIN
DIENB
DIN5
DIN4
CIN5
CIN6
CIN3
CIN4
COUT7 TCCO
ERASE TCS
DIN1
DIN6
DIN2
DIN3
CIENB
DIN0
CIN7
TCCI
V
CC
A
COENB
V
DIN7
V
V
V
RESET
SS
CC
CC
SS
6
HSP43881/883
BURN-IN SIGNALS
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
V
GND
F10
C1
C2
COUT5
COUT6
ALIGN
DIENB
DIN5
V
V
/2
/2
F10
F11
G1
G2
G3
G9
G10
G11
H1
H2
H10
H11
J1
V
V
K4
K5
K6
K7
K8
K9
K10
K11
L1
V
V
CC
SS
COENB
CC
CC
CC
CC
SUM19
V
GND
F2
V
/2
CC
SS
CC
V
V
C3
NC
ADR2
DCMO
CLK
V
SS
GND
CC
CC
RESET
DIN7
F11
F8
F6
F3
F0
F8
C5
F10
F5
F4
F5
F3
F5
SUM15
SUM12
SUM10
SUM8
V
/2
CC
CC
CC
CC
C6
F0
V
V
V
V
/2
/2
/2
/2
DIN6
C7
DIN4
SUM1
SUM3
SUM2
ADR1
ADR0
SUM5
SUM4
V
/2
CC
CC
DIN3
C10
C11
D1
CIN5
V
V
/2
/2
DIN0
CIN3
SUM6
CC
F1
CC
F6
CIN8/5CCI
COUT3
COUT4
CIN2
V
/2
DCM1
CC
V
V
V
V
D2
V
/2
F0
L2
SUM23
SUM22
SUM21
SUM18
SUM14
V
V
V
V
V
/2
/2
/2
/2
/2
CC
SS
CC
CC
GND
CC
F2
CC
CC
CC
CC
CC
D10
D11
E1
V
V
/2
/2
L3
CC
CC
V
V
V
CC
L4
CC
CC
COUT1
COUT7
COUT8/TCC0
ERASE
DIN8/TCS
DIN1
V
/2
V
/2
V
V
CC
L5
CC
CC
CC
V
/2
E2
V
GND
J2
SUM25
SUM20
SUM17
SUM16
SUM7
V
V
V
V
V
/2
/2
/2
/2
/2
L6
CC
SS
CC
CC
CC
CC
CC
F10
F7
E3
COUT2
CIN1
V
/2
J5
L7
V
V
CC
CC
F1
CC
SUM13
E9
J6
L8
V
/2
CC
F1
E10
E11
F1
CIN0
F0
J7
L9
V
GND
SS
DIN2
F2
SENBL
F10
GND
J10
J11
K1
L10
L11
SUM11
SUM9
V
/2
CC
CIENB
F10
F7
V
V
GND
F10
V
/2
SS
SS
CC
CIN7
F2
COUT0
SHADD
SUM0
V
/2
SENBH
SUM24
CC
B10 CIN6
B11 CIN4
F6
F3
F9
K2
V
/2
CC
F4
F9
V
/2
K3
V
GND
CC
SS
NOTES:
8. V /2 (2.7 ±10% used for outputs only.
CC
9. 47kΩ (±20%) resistor connected to all pins except V
and GND.
CC
10. V
= 5.5V ±0.5V.
11. 0.1µF (minimum) capacitor between V
CC
and GND per device.
CC
12. F0 = 100kHz ±10%, F1 = F0/2, F2 = F1/2..., F11 = F10/2, 40% - 60% duty cycle.
13. Input voltage limits: V = 0.8V maximum, V = 4.5V ±10%.
IL
IH
Die Characteristics
DIE DIMENSIONS:
GLASSIVATION
328 mils x 283 mils x ±1 mil
Type: Nitrox
Silox Thickness: 10kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Type: Si-Al or Si-AI-Cu
Thickness: 8kÅ
5
2
1.2 x 10 A/cm
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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7
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