HS0-5104AEH-Q [INTERSIL]
Radiation Hardened, Low Noise Quad Operational Amplifiers;
| 型号： | HS0-5104AEH-Q |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened, Low Noise Quad Operational Amplifiers 放大器 CD |
| 文件： | 总5页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Radiation Hardened, Low Noise Quad Operational
Amplifiers
HS-5104ARH, HS-5104AEH
Features
The HS-5104ARH, HS-5104AEH are radiation hardened,
monolithic quad operational amplifiers that provide highly
reliable performance in harsh radiation environments.
Excellent noise characteristics coupled with a unique array of
dynamic specifications make these amplifiers well-suited for a
variety of satellite system applications. Dielectrically isolated,
bipolar processing makes these devices immune to Single
Event Latch-Up.
• Electrically screened to SMD # 5962-95690
• QML qualified per MIL-PRF-38535 requirements
• Radiation environment
- High dose rate (50-300rad(Si)/s). . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . . .50krad(Si)
• No latch-up, dielectrically isolated device islands
• Low noise
The HS-5104ARH, HS-5104AEH show almost no change in offset
voltage after exposure to 100kRAD(Si) gamma radiation, with
only a minor increase in current. Complementing these
- At 1kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3nV/√Hz (Typ)
- At 1kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6pA/√Hz (Typ)
specifications is a post radiation open loop gain in excess of 40k.
• Low offset voltage . . . . . . . . . . . . . . . . . . . . . . . . .3.0mV (Max)
• High slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V/µs (Typ)
• Gain bandwidth product . . . . . . . . . . . . . . . . . . . .8.0MHz (Typ)
These quad operational amplifiers are available in an industry
standard pinout, allowing for immediate interchangeability
with most other quad operational amplifiers.
Applications
• High Q, active filters
• Voltage regulators
• Integrators
• Signal generators
• Voltage references
• Space environment
Ordering Information
INTERNAL
PACKAGE
MKT. NUMBER
(NOTE 1 )
TEMP. RANGE
PART
MARKING
(RoHS Compliant)
(NOTE 2)
ORDERING/SMD NUMBER
5962R9569001VXC
5962R9569002VXC
5962R9569001VCC
5962R9569002VCC
5962R9569001V9A
5962R9569002V9A
HS1-5104ARH/PROTO
HS0-5104ARH/SAMPLE
HS9-5104ARH/PROTO
(°C)
PKG. DWG. #
K14.A
HS9-5104ARH-Q
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
Q 5962R95 69001VXC
Q 5962R95 69002VXC
Q 5962R95 69001VCC
Q 5962R95 69002VCC
14 Ld Flatpack
14 Ld Flatpack
14 Ld SBDIP
14 Ld SBDIP
Die
HS9-5104AEH-Q
K14.A
HS1-5104ARH-Q
D14.3
HS1-5104AEH-Q
D14.3
HS0-5104ARH-Q
HS0-5104AEH-Q
Die
HS1-5104ARH/PROTO
HS0-5104ARH/SAMPLE
HS9-5104ARH/PROTO
HS1-5104ARH/PROTO
HS9-5104ARH/PROTO
14 Ld SBDIP
Die
D14.3
K14.A
14 Ld Flatpack
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in
the“Ordering Information” table must be used when ordering.
2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
July 12, 2013
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2002, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
FN3025.5
HS-5104ARH, HS-5104AEH
Pin Configuration
HS1-5104ARH, HS1-5104AEH
HS9-5104ARH, HS9-5104AEH
(14 LD FLATPACK)
TOP VIEW
(14 LD SBDIP)
TOP VIEW
OUT 1
-IN1
OUT 4
-IN4
1
2
3
4
5
6
7
14
13
12
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT 1
-IN1
OUT 4
-IN4
+IN1
V+
+IN4
V-
+IN4
+IN1
V+
+IN2
-IN2
+IN3
-IN3
11 V-
+IN2
-IN2
+IN3
10
9
OUT 2
8
OUT 3
-IN3
OUT 2
8
OUT 3
Irradiation Circuit
Burn In Circuit
1
2
14
13
12
11
10
9
1
4
+15V
-
-
R1
3
R4
R3
+
+
-
+
4
-V
C2
+V
D1
R2
2
3
5
6
7
D2
-15V
C1
+
+
-
-
(ONE OF FOUR)
8
NOTES:
3. +V = 15V
4. -V = -15V
NOTES:
5. Group E Sample Size = 4 Die Per Wafer
6. R1 = R2 = R3 = R4 = 1MW, 5%, 1/4W (Min)
7. C1 = C2 = 0.01µF/Socket (Min) or 0.1µF/Row (Min)
8. D1 = D2 = IN4002 or Equivalent/Board
9. |(V+) - (V-)| = 31V ±1V
FN3025.5
July 12, 2013
2
HS-5104ARH, HS-5104AEH
Die Characteristics
DIE DIMENSIONS:
Backside Finish:
95 mils x 99 mils x 19 mils ±1 mils
Silicon
(2420µm x 2530µm x 483µm ±25.4µm)
ASSEMBLY RELATED INFORMATION:
INTERFACE MATERIALS:
Glassivation:
Substrate Potential (Powered Up):
Unbiased
Type: Nitride (SI3N4) over Silox (SIO2, 5% Phos.)
Silox Thickness: 12kÅ ±2kÅ
Nitride Thickness: 3.5kÅ ±1.5kÅ
ADDITIONAL INFORMATION:
Worst Case Current Density:
5
2
Top Metallization:
<2.0 x 10 A/cm
Type: Al, 1% Cu
Thickness: 16kÅ ±2kÅ
Transistor Count:
175
Substrate:
Bipolar Dielectric Isolation
Metallization Mask Layout
HS-5104ARH, HS-5104AEH
+IN2
V+
+IN1
-IN1
-IN2
OUT1
OUT4
OUT2
OUT3
-IN3
-IN4
+IN3
V-
+IN4
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3025.5
July 12, 2013
3
HS-5104ARH, HS-5104AEH
Ceramic Metal Seal Flatpack Packages (Flatpack)
K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
A
e
INCHES MILLIMETERS
MIN
PIN NO. 1
ID AREA
SYMBOL
MAX
0.115
0.022
0.019
0.009
0.006
0.390
0.260
0.290
-
MIN
1.14
0.38
0.38
0.10
0.10
-
MAX
2.92
0.56
0.48
0.23
0.15
9.91
6.60
7.11
-
NOTES
D
A
b
0.045
0.015
0.015
0.004
0.004
-
-
-
-A-
-B-
S1
b1
c
-
-
b
c1
D
-
E1
3
-
0.004
Q
H
A - B
D
0.036
H
A - B
D
S
M
S
S
M
S
C
E
0.235
-
5.97
-
E
E1
E2
E3
e
3
-
-D-
A
0.125
0.030
3.18
0.76
-H-
-C-
-
-
7
-
L
E2
L
E3
E3
0.050 BSC
1.27 BSC
SEATING AND
BASE PLANE
c1
LEAD FINISH
k
0.008
0.270
0.026
0.005
-
0.015
0.370
0.045
-
0.20
6.86
0.66
0.13
-
0.38
9.40
1.14
-
2
-
L
BASE
METAL
Q
S1
M
N
8
6
-
(c)
b1
0.0015
0.04
M
M
(b)
14
14
-
SECTION A-A
Rev. 0 5/18/94
NOTES:
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area
shown. The manufacturer’s identification shall not be used as a pin
one identification mark. Alternately, a tab (dimension k) may be
used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits
of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass over-
run.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness. The maximum limits of
lead dimensions b and c or M shall be measured at the centroid of
the finished lead surfaces, when solder dip or tin plate lead finish is
applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materi-
als shall be molded to the bottom of the package to cover the leads.
8. Dimension Q shall be measured at the point of exit (beyond the me-
niscus) of the lead from the body. Dimension Q minimum shall be
reduced by 0.0015 inch (0.038mm) maximum when solder dip lead
finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
FN3025.5
July 12, 2013
4
HS-5104ARH, HS-5104AEH
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1 LEAD FINISH
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
-A-
-D-
E
INCHES
MIN
MILLIMETERS
BASE
METAL
(c)
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
S
S
S
D
bbb
C
A - B
-
D
4
BASE
S2
Q
PLANE
2
A
-C-
SEATING
PLANE
c1
D
3
L
-
S1
b2
eA
A A
E
0.220
5.59
-
e
eA/2
aaa M C A - B S D S
b
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
M
C A - B S D S
-
NOTES:
0.125
0.200
3.18
5.08
-
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area
shown. The manufacturer’s identification shall not be used as a pin
one identification mark.
Q
0.015
0.005
0.005
0.060
0.38
0.13
0.13
1.52
5
S1
S2
α
-
-
-
-
6
7
2. The maximum limits of lead dimensions b and c or M shall be mea-
sured at the centroid of the finished lead surfaces, when solder dip
or tin plate lead finish is applied.
o
o
o
o
90
105
90
105
-
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness.
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a par-
tial lead paddle. For this configuration dimension b3 replaces di-
mension b2.
2
8
N
14
14
5. Dimension Q shall be measured from the seating plane to the base
plane.
Rev. 0 4/94
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the near-
est metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
FN3025.5
July 12, 2013
5
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