HS-82C08RH [INTERSIL]
Radiation Hardened 8-Bit Bus Transceiver; 抗辐射8位总线收发器
| 型号： | HS-82C08RH |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened 8-Bit Bus Transceiver |
| 文件： | 总6页 (文件大小：48K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HS-82C08RH
Radiation Hardened
8-Bit Bus Transceiver
February 1996
Features
Functional Diagram
• Devices QML Qualified in Accordance With
MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95714 and Intersil’ QM Plan
A0
B0
• Radiation Hardened
- Total Dose 1 x 105 RAD (Si)
- Latch-Up Immune EPI-CMOS > 1 x 1012 RAD (Si)/s
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
PORT
A
PORT
B
• Bidirectional Three-State Input/Outputs
• Low Propagation Delay Time
• Low Power Consumption
• Single Power Supply +5V
T/R
• Electrically Equivalent to Sandia SA2997
• Military Temperature Range -55oC to +125oC
OE
Description
TRUTH TABLE
The Intersil HS-82C08RH is a radiation-hardened octal bus
transceiver with three-state outputs. It is manufactured using
a self-aligned, junction isolated CMOS process and is
designed for use with the HS-80C08RH radiation-hardened
microprocessor. The HS-82C08RH allows asynchronous
two-way communication between data buses. The direction
of data flow is determined by the logic level on the transmit/
receive (T/R) input. A logic high on the T/R input specifies
data flow from Port A to Port B of the device. Conversely, a
logic low on the T/R input specifies data flow from Port B to
Port A. The Output Enable input disables both ports by
placing them in the high impedance state.
INPUTS
OPERATION
OUTPUT
ENABLE
TRANSMIT
/RECEIVE
PORT A PORT B
0
0
1
X
Out
In
In
0
Out
1
High Z
High Z
X = Don’t Care
The HS-82C08RH is ideally suited for a wide variety of
buffering applications in radiation-hardened microcomputer
systems.
Ordering Information
PART NUMBER
5962R9571401QRC
5962R9571401QXC
5962R9571401VRC
5962R9571401VXC
HS1-82C08RH/SAMPLE
HS9-82C08RH/SAMPLE
TEMPERATURE RANGE
SCREENING LEVEL
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level V
SAMPLE
PACKAGE
o
o
-55 C to +125 C
20 Lead SBDIP
o
o
-55 C to +125 C
20 Lead Ceramic Flatpack
20 Lead SBDIP
o
o
-55 C to +125 C
o
o
-55 C to +125 C
20 Lead Ceramic Flatpack
20 Lead SBDIP
o
+25 C
o
+25 C
SAMPLE
20 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Spec Number 518057
File Number 3040.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HS-82C08RH
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
METAL-SEAL PACKAGE (SBDIP) MIL-STD-1835, CDIP2-T20
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK) MIL-STD-1835, CDFP4-F20
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
VDD
B0
A0
A1
A2
A3
A4
A5
A6
A7
OE
20
19
A0
A1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
B0
B1
B2
B3
B4
B5
B6
B7
T/R
A2
18 B1
17 B2
16 B3
A3
A4
A5
15
B4
A6
14 B5
13 B6
A7
OE
GND
12
B7
GND 10
11 T/R
PIN
DESCRIPTION
PIN
DESCRIPTION
A0-A7
B0-B7
Local Bus Data I/O Pins
System Bus Data I/O Pins
T/R
OE
Transmit/Receive Input
Active Low Output Enable
Logic Diagram
TSB
TSB
TSB
TSB
TSB
TSB
TSB
TSB
1
2
3
4
5
6
7
8
19
18
17
16
15
14
13
12
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
TSB
TSB
TSB
TSB
TSB
TSB
TSB
TSB
OE
9
B ENABLE
A ENABLE
T/R
11
NOTE: An Important caveat that is applicable to CMOS devices in general is that unused inputs should never be left floating. This rule applies
to inputs connected to a three-state bus. The need for external pull-up resistors during three-state bus conditions is eliminated by the
presence of regenerative latches on the following HS-82C08RH pins. A0-7 and B0-7 The functional block diagram depicts one of
these pins with the regenerative latch. When the CMOS driver assumes the high impedance state, the latch holds the bus in whatever
logic state (high or low) it was before the three-state condition. A transient drive current of ±1.5mA at VDD/2 ±0.5V for 10ns is required
to switch the latch. Thus, CMOS device inputs connected to the bus are not allowed to float during three-state conditions.
Spec Number 518057
2
Specifications HS-82C08RH
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Thermal Resistance
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V 20 Lead SBDIP Package. . . . . . . . . . . . .
20 Lead Ceramic Flatpack Package . . . .
θ
θ
JA
JC
o
o
71 C/W
17 C/W
o
o
o
o
Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C
85 C/W
25 C/W
o
o
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300 C
Maximum Package Power Dissipation at +125 C Ambient
o
20 Lead SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.70W
20 Lead Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . 0.59W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
20 Lead SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . .14.1mW/C
20 Lead Ceramic Flatpack Package . . . . . . . . . . . . . . .11.8mW/C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +1V
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . .VDD -1V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
All Devices Guaranteed at Worst Case Limits and Conditions.
LIMITS
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
o
o
Input Leakage Current
IIL
VDD = 5.25V, VIN = VDD
Pin Under Test = 0V
1, 2, 3
-55 C, +25 C,
-1.0
-
µA
o
+125 C
o
o
IIH
VOH
VOL
SIDD
FT
VDD = 5.25V, VIN = 0V
Pin Under Test = 5.25V
1, 2, 3
1, 2, 3
-55 C, +25 C,
-
1.0
-
µA
V
o
+125 C
o
o
High Level Output
Voltage
VDD = 4.75V, IOH = -2.0mA
VDD = 5.25V, IOL = 2.0mA
VDD = 5.25V, VIN = GND
-55 C, +25 C,
4.25
o
+125 C
o
o
Low Level Output
Voltage
1, 2, 3
-55 C, +25 C,
-
-
-
0.5
100
-
V
o
+125 C
o
o
Static Current
1, 2, 3
-55 C, +25 C,
µA
-
o
+125 C
o
o
Functional Test
VDD = 4.75V to 5.25V
VIH = VDD -1.0V, VIL = 1.0V
7, 8A, 8B
-55 C, +25 C,
o
+125 C
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
LIMITS
PARAMETER
SYMBOL
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
PORT DATA/MODE SPECIFICATIONS
o
o
o
Propagation Delay to Logical “1” from Port
A, B to Port B, A
TPDLH
TPDHL
TPRTH
TPRTL
TPZH
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C, +25 C, +125 C
-
-
-
-
-
-
65
80
ns
ns
ns
ns
ns
ns
o
o
o
Propagation Delay to Logical “0” from Port
A, B to Port B, A
-55 C, +25 C, +125 C
o
o
o
Propagation Delay from High-Impedance
to Logical “1” from T/R to Port
-55 C, +25 C, +125 C
75
o
o
o
Propagation Delay from High-Impedance
to Logical “0” from T/R to Port
-55 C, +25 C, +125 C
130
70
o
o
o
Propagation Delay from High-Impedance
to Logical “1” from OE to Port
-55 C, +25 C, +125 C
o
o
o
Propagation Delay from High-Impedance
to Logical “0” from OE to Port
TPZL
-55 C, +25 C, +125 C
130
Spec Number 518057
3
Specifications HS-82C08RH
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
(NOTE)
PARAMETER
In/Out Capacitance
SYMBOL
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
o
CI/O
VDD = Open, f = 1MHz
All Measurements Referenced
to GND.
+25 C
-
10
pF
TRANSMIT/RECEIVE MODE SPECIFICATIONS (AC Parameters)
o
Propagation Delay from Logical “1” to
High-Impedance from T/R to Port
TPHZTR
TPLZTR
TPHZ
+25 C
-
-
-
-
35
35
35
35
ns
ns
ns
ns
o
Propagation Delay from Logical “0” to
High-Impedance from T/R to Port
+25 C
o
Propagation Delay from Logical “1” to
High-Impedance from OE to Port
+25 C
o
Propagation Delay from Logical “0” to
High-Impedance from OE to Port
TPLZ
+25 C
NOTE:
1. The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design release and upon design changes which could affect these characteristics.
TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS
NOTE: The Post Irradiation test conditions and limits are the same as those listed in Table 1 and Table 2.
o
TABLE 5. BURN-IN DELTA PARAMETERS (+25 C; In Accordance With SMD)
Switching Time Waveforms
TR
0.5VDD
tPLH
TF
DEVICE
UNDER
TEST
VDD
0V
TEST POINTS
CL (NOTE)
INPUT
AN OR BN
0.5VDD
tPHL
0.5VDD
VDD
OUTPUT
BN OR AN
0.5VDD
0V
TR = TF ≤ 20ns
10% to 90%
NOTE: CL includes stray and jig capacitance.
FIGURE 1. PORT TO PORT
FIGURE 2. AC TESTING LOAD CIRCUIT
VDD
TR
TF
TR = TF ≤ 20ns
INPUT OE
10% to 90%
0.5VDD
0.5VDD
tPZH
0V
0.1VDD
PORT
OUTPUT
VOH
0.5VDD
0.5VDD
0V
tPHZ
tPLZ
VDD
PORT
OUTPUT
VOL
tPZL
0.1VDD
FIGURE 3. OE TO HIGH-IMPEDANCE, OE TO PORT OUTPUT
Spec Number 518057
4
HS-82C08RH
Metallization Topology
DIE DIMENSIONS:
76.0 mils x 89.4 mils x 14 mils ±1 mil
METALLIZATION:
Type: Si - Al
Thickness: 11kÅ ±2kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
Metallization Mask Layout
HS-82C08RH
A1 (2)
A2 (3)
(18) B1
(17) B2
A3 (4)
A4 (5)
A5 (6)
A6 (7)
A7 (8)
(16) B3
(15) B4
(14) B5
(13) B6
(12) B7
Spec Number 518057
5
HS-82C08RH
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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Spec Number
6
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