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HS-82C08RH_00 [INTERSIL]

Radiation Hardened 8-Bit Bus Transceiver; 抗辐射8位总线收发器
HS-82C08RH_00
型号： HS-82C08RH_00
厂家： Intersil    Intersil
描述：

Radiation Hardened 8-Bit Bus Transceiver
抗辐射8位总线收发器

总线收发器
文件： 总4页 (文件大小：57K)
中文：  中文翻译
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HS-82C08RH  
TM  
Data Sheet  
August 2000  
File Number 3040.3  
Radiation Hardened 8-Bit Bus Transceiver  
Features  
The Intersil HS-82C08RH is a radiation-hardened octal bus  
transceiver with three-state outputs. It is manufactured using  
a self-aligned, junction isolated CMOS process and is  
designed for use with the HS-80C08RH radiation-hardened  
microprocessor. The HS-82C08RH allows asynchronous  
two-way communication between data buses. The direction  
of data flow is determined by the logic level on the  
transmit/receive (T/R) input. A logic high on the T/R input  
specifies data flow from Port A to Port B of the device.  
Conversely, a logic low on the T/R input specifies data flow  
from Port B to Port A. The Output Enable input disables both  
ports by placing them in the high impedance state.  
• Electrically Screened to SMD # 5962-95714  
• QML Qualified per MIL-PRF-38535 Requirements  
• Radiation Performance  
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)  
12  
- Latch-Up Immune EPI-CMOS . . . . .>1 x 10 rad(Si)/s  
• Bidirectional Three-State Input/Outputs  
• Low Propagation Delay Time  
• Low Power Consumption  
• Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V  
• Electrically Equivalent to Sandia SA2997  
The HS-82C08RH is ideally suited for a wide variety of  
buffering applications in radiation-hardened microcomputer  
systems.  
o
o
• Military Temperature Range . . . . . . . . . . . -55 C to 125 C  
Ordering Information  
Specifications for Rad Hard QML devices are controlled  
by the Defense Supply Center in Columbus (DSCC). The  
SMD numbers listed here must be used when ordering.  
INTERNAL  
TEMP. RANGE  
o
ORDERING NUMBER  
5962R9571401QRC  
5962R9571401QXC  
5962R9571401VRC  
5962R9571401VXC  
MKT. NUMBER  
( C)  
HS1-82C08RH-8  
HS9-82C08RH-8  
HS1-82C08RH-Q  
HS9-82C08RH-Q  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
Detailed Electrical Specifications for these devices are  
contained in SMD 5962-95714. A “hot-link” is provided  
on our homepage for downloading.  
www.intersil.com/spacedefense/space.asp  
Functional Diagram  
TRUTH TABLE  
INPUTS  
OPERATION  
OUTPUT  
ENABLE  
TRANSMIT  
/RECEIVE  
A0  
B0  
PORT A PORT B  
0
0
1
Out  
In  
In  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
0
1
Out  
X
High Z  
High Z  
PORT  
A
PORT  
B
X = Don’t Care  
T/R  
OE  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000  
1
HS-82C08RH  
Pinouts  
20 LEAD CERAMIC DUAL-IN-LINEMETAL-SEAL PACKAGE  
(SBDIP) MIL-STD-1835, CDIP2-T20  
TOP VIEW  
20 LEAD CERAMIC METAL SEALFLATPACK PACKAGE  
(FLATPACK) MIL-STD-1835, CDFP4-F20  
TOP VIEW  
1
2
3
4
5
6
7
8
9
V
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
OE  
20  
19  
A0  
A1  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
DD  
DD  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
T/R  
B0  
A2  
18 B1  
17 B2  
16 B3  
15 B4  
14 B5  
13 B6  
A3  
A4  
A5  
A6  
A7  
OE  
GND  
12  
B7  
GND 10  
11 T/R  
PIN  
DESCRIPTION  
PIN  
T/R  
OE  
DESCRIPTION  
A0-A7  
B0-B7  
Local Bus Data I/O Pins  
System Bus Data I/O Pins  
Transmit/Receive Input  
Active Low Output Enable  
Logic Diagram  
TSB  
TSB  
TSB  
TSB  
TSB  
TSB  
TSB  
TSB  
1
2
3
4
5
6
7
8
19  
18  
17  
16  
15  
14  
13  
12  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
TSB  
TSB  
TSB  
TSB  
TSB  
TSB  
TSB  
TSB  
OE  
9
B ENABLE  
A ENABLE  
T/R  
11  
NOTE: An Important caveat that is applicable to CMOS devices in general is that unused inputs should never be left floating. This rule applies to  
inputs connected to a three-state bus. The need for external pull-up resistors during three-state bus conditions is eliminated by the presence of  
regenerative latches on the following HS-82C08RH pins. A0-7 and B0-7 The functional block diagram depicts one of these pins with the regenerative  
latch. When the CMOS driver assumes the high impedance state, the latch holds the bus in whatever logic state (high or low) it was before the three-  
state condition. A transient drive current of ±1.5mA at V /2 ±0.5V for 10ns is required to switch the latch. Thus, CMOS device inputs connected to  
DD  
the bus are not allowed to float during three-state conditions.  
2
HS-82C08RH  
Switching Time Waveforms  
t
t
f
r
V
V
DD  
0V  
INPUT  
AN OR BN  
0.5V  
0.5V  
DD  
DD  
PLH  
DEVICE  
UNDER  
TEST  
t
t
PHL  
TEST POINTS  
DD  
0V  
OUTPUT  
BN OR AN  
C
(NOTE)  
0.5V  
0.5V  
L
DD  
DD  
t = t ≤ 20ns  
r
f
10% TO 90%  
NOTE: C includes stray and jig capacitance.  
L
FIGURE 1. PORT TO PORT  
FIGURE 2. AC TESTING LOAD CIRCUIT  
V
DD  
0V  
t
t
t = t ≤ 20ns  
r
f
r
f
INPUT OE  
0.5V  
0.5V  
t
10% TO 90%  
DD  
DD  
0.1V  
DD  
PORT  
OUTPUT  
PZH  
V
OH  
0.5V  
0.5V  
DD  
DD  
0V  
DD  
t
t
PHZ  
PLZ  
V
PORT  
OUTPUT  
V
OL  
t
PZL  
0.1V  
DD  
FIGURE 3. OE TO HIGH-IMPEDANCE, OE TO PORT OUTPUT  
3
HS-82C08RH  
Die Characteristics  
DIE DIMENSIONS:  
INTERFACE MATERIALS:  
Glassivation:  
Type: SiO  
76.0 mils x 89.4 mils x 14 mils ±1 mil  
2
Thickness: 8kÅ ±1kÅ  
Top Metallization:  
Type: Si - Al  
Thickness: 11kÅ ±2kÅ  
Metallization Mask Layout  
HS-82C08RH  
A1 (2)  
A2 (3)  
(18) B1  
(17) B2  
A3 (4)  
A4 (5)  
A5 (6)  
A6 (7)  
A7 (8)  
(16) B3  
(15) B4  
(14) B5  
(13) B6  
(12) B7  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Intersil Ltd.  
P. O. Box 883, Mail Stop 53-204  
Melbourne, FL 32902  
TEL: (321) 724-7000  
FAX: (321) 724-7240  
Mercure Center  
8F-2, 96, Sec. 1, Chien-kuo North,  
Taipei, Taiwan 104  
Republic of China  
TEL: 886-2-2515-8508  
FAX: 886-2-2515-8369  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
4

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