HS-82C12 [INTERSIL]
Radiation Hardened 8-Bit Input/Output Port; 抗辐射的8位输入/输出端口
| 型号： | HS-82C12 |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened 8-Bit Input/Output Port |
| 文件： | 总8页 (文件大小：52K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HS-82C12RH
Radiation Hardened
8-Bit Input/Output Port
March 1996
Features
Functional Diagram
• Devices QML Qualified in Accordance with
MIL-PRF-38535
DS1
SERVICE
REQUEST
F.F.
2
3
CONTROL
AND
DEVICE
SELECT
LOGIC
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95818 and Intersil’ QM Plan
- Radiation Hardened CMOS Process
DS2
STB
CLR
MD
INT
- Total Dose 1 x 105 RAD (Si)
- Transient Upset > 1 x 108 RAD (Si)/s
DATA
- Latch-Up Immune EPI-CMOS > 1 x 1012 RAD (Si)/s
LATCH
AND
BUFFER
(8)
• Low Power Dissipation
DI0-7
DO0-7
• High Noise Immunity
• Single Power Supply +5V
• Low Input Load Current
• 8-Bit Data Register and Buffer
• Asynchronous Register Clear
• Service Request Flip-Flop for Interrupt Generation
• Three-State Outputs
Pin Description
PIN
DI0-DI7
DO0-DO7
DS1, DS2
MD
DESCRIPTION
Data In
• Bus-Compatible with HS-80C85RH CPU
• Electrically Equivalent to Sandia SA3026
• Military Temperature Range -55oC to +125oC
Data Out
Device Select
Mode
Description
The Intersil HS-82C12RH is a radiation hardened 8-bit input/
output port designed for use with the HS-80C85RH radiation
hardened microprocessor. It is manufactured using a self-
aligned, junction-isolated EPI-CMOS process and features
three-state output buffers and device selection and control
logic. A service request flip-flop is included for the
generation and control of interrupts to the microprocessor.
The device can be used in implement many of the peripheral
and input/output functions of a microcomputer system. The
HS-82C12RH is pinout- and function- compatible with
industry-standard 8212 devices.
STB
Strobe
INT
Interrupt
Clear
CLR
Ordering Information
PART NUMBER
5962R9581801QJC
5962R9581801QXC
5962R9581801VJC
5962R9581801VXC
HS1-82C12RH/Sample
HS9-82C12RH/Sample
TEMPERATURE RANGE
SCREENING LEVEL
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level V
Sample
PACKAGE
o
o
-55 C to +125 C
24 Lead SBDIP
o
o
-55 C to +125 C
24 Lead Ceramic Flatpack
24 Lead SBDIP
o
o
-55 C to +125 C
o
o
-55 C to +125 C
24 Lead Ceramic Flatpack
24 Lead SBDIP
o
+25 C
o
+25 C
Sample
24 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
Spec Number 518063
File Number 3041.2
1
HS-82C12RH
Pinouts
24 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T24
TOP VIEW
DS1
MD
1
2
3
4
5
6
7
8
9
24
VDD
23 INT
22 DI7
21 DO7
20 DI6
19 DO6
18 DI5
17 DO5
16 DI4
15 DO4
14 CLR
13 DS2
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3 10
STB 11
GND 12
24 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F24
TOP VIEW
1
24
23
22
21
20
19
18
17
16
15
14
13
DS1
MD
VDD
INT
2
3
DI7
DI0
4
DO7
DI6
DO0
DI1
5
6
DO6
DI5
DO1
DI2
7
8
DO5
DI4
DO2
DI3
9
DO4
CLR
DS2
10
11
12
DO3
STB
GND
Spec Number 518063
2
Specifications HS-82C12RH
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Thermal Resistance
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V SBDIP Package. . . . . . . . . . . . . . . . . . . .
Ceramic Flatpack Package . . . . . . . . . . .
θ
θ
JA
JC
o
o
55 C/W
14 C/W
o
o
o
o
Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C
74 C/W
13 C/W
o
o
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300 C
Maximum Package Power Dissipation at +125 C Ambient
o
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.91W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18.2mW/C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .13.5mW/C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +1.0V
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . .VDD -1V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS TEMPERATURE
MIN
MAX
UNITS
o
o
High Input Leakage
Current
IIH
VDD = 5.25V, VIN = 0V,
Pin under test = 5.25V
1, 2, 3
1, 2, 3
-55 C, +25 C,
-
1
µA
o
+125 C
o
o
Low Input Leakage
Current
IIL
VOL
VOH
SIDD
FT
VDD = 5.25V, VIN = 5.25V,
Pin under test = 0V
-55 C, +25 C,
-1
-
0.5
-
µA
V
o
+125 C
o
o
Low Output Voltage
High Output Voltage
Static Current
VDD = 5.25V, IOL = 2mA
VDD = 4.75V, IOH = -2mA
VDD = 5.25V, VIN = GND
1, 2, 3
-55 C, +25 C,
-
o
+125 C
o
o
1, 2, 3
-55 C, +25 C,
4.25
V
o
+125 C
o
o
1, 2, 3
-55 C, +25 C,
-
-
100
-
µA
-
o
+125 C
o
o
Functional Tests
VDD = 4.75V and 5.25V,
VIH = VDD-1.0V, VIL = 1.0V
7, 8A, 8B
-55 C, +25 C,
o
+125 C
NOTE: All devices are guaranteed at worst case limits and over radiation.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A SUB-
LIMITS
PARAMETER
Data to Output Delay
Write Enable to Output Delay
Reset to Output Delay
Set to Output Delay
Clear to Output Delay
Output Enable Time
Output Disable Time
NOTE:
SYMBOL
TPD
TWE
TR
GROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
TEMPERATURE
MIN
MAX
UNITS
o
o
o
-55 C, +25 C, +125 C
-
-
-
-
-
-
-
105
200
145
100
135
125
85
ns
ns
ns
ns
ns
ns
ns
o
o
o
-55 C, +25 C, +125 C
o
o
o
-55 C, +25 C, +125 C
o
o
o
TS
-55 C, +25 C, +125 C
o
o
o
TC
-55 C, +25 C, +125 C
o
o
o
TE
-55 C, +25 C, +125 C
o
o
o
TD
-55 C, +25 C, +125 C
1. Output Timings are measured with the following conditions: CL = 100pF, VIH = 3.75V, and VIL = 1.0V
Spec Number 518063
3
Specifications HS-82C12RH
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
GROUP A
PARAMETER
SYMBOL
CONDITIONS
SUBGROUPS TEMPERATURE
MIN
MAX
UNITS
o
Input Capacitance
CIN
VDD = Open, f = 1MHz, All
measurements referenced to
device ground
T = +25 C
-
8
pF
A
o
Output Capacitance
COUT
VDD = Open, f = 1MHz, All
measurements referenced to
device ground
T = +25 C
-
8
pF
A
o
o
Pulse Width
TPW
TSET
TH
VDD = 4.75, VIH = 3.75, VIL = 1.0
VDD = 4.75, VIH = 3.75, VIL = 1.0
VDD = 4.75, VIH = 3.75, VIL = 1.0
9, 10, 11
9, 10, 11
9, 10, 11
-55 C, +25 C,
-
-
-
50
30
40
ns
ns
ns
o
+125 C
o
o
Data Set Up Time
Data Hold Time
-55 C, +25 C,
o
+125 C
o
o
-55 C, +25 C,
o
+125 C
NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.
TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS
NOTE: The Post Irradiation test conditions and limits are the same as those listed in Table 1 and Table 2.
Spec Number 518063
4
HS-82C12RH
Timing Waveforms
(DS, • DS2)
tE
0.5VDD
tD
VOH
VOL
OUTPUT
0.5VDD
FIGURE 1. READ TIMING
DATA
tPW
tWE
tH
MD OR (DS, • DS2)
OUTPUT
FIGURE 2. WRITE TIMING
DATA
tSET
tH
STB OR (DS, • DS2)
tPD
OUTPUT
FIGURE 3. DATA SETUP, HOLD, PROPAGATION DELAY TIMING
tPW
STB
tPW
(DS, • DS2)
tR
tS
INT
FIGURE 4. INTERRUPT TIMING
tPW
tC
CLR
DO
FIGURE 5. CLEAR TIMING
Spec Number 518063
5
HS-82C12RH
Functional Description
Mode
Data Latch
the mode input (MD) is used to control the state of the output
buffer and to determine the source of the data latch clock
(C). When MD is high, the output buffers are enabled and
the source of the data latch clock (C) is the device select
logic (DS1 • DS2).
The data latch is comprised of eight “D” type flip-flops. The
output of each flip-flop will follow the corresponding data
input (DI0 - DI7) when the clock (C) is high. The clock input
is level sensitive and the data becomes latched when the
clock returns low.
When MD is low, the state of the output buffer is controlled
by the device select logic (DS1 • DS2) and the source of the
data latch clock is the strobe (STB) input.
An asynchronous reset (CLR) is used to clear the latched
data. Since the clock (C) overrides the reset (CLR), the data
must be in the latched state in order to clear the flip-flops. If
the data is not latched (i.e. clock is high) when CLR goes
low, then the Q outputs of the data latch will continue to fol-
low the data input, overriding the reset signal.
Strobe
The strobe input (STB) is used as the data latch clock (C)
when the mode input (MD) is low. The service request flip-
flop is synchronously set on the negative going edge of STB.
Output Buffer
Three-state buffers are used to provide output drive for the
data latch. A high level on the “output buffer enable” control
line enables the buffer outputs. When “output buffer enable”
is low the buffer outputs are forced to the high-impedance
state.
Service Request Flip-Flop
The service request flip-flop is to generate interrupts to
microcomputer systems. It is negative edge triggered and
asynchronously cleared (reset).
The output of the service request flip-flop is AND-gated with
the device select logic (DS1 • DS2). The output of the AND
gate is the active low interrupt (INT) signal.
Device Select Logic
The inputs DS1 and DS2 are used for device selection.
When DS1 is low and DS2 is high, the device is selected.
The output buffers are enabled and the service request flip-
flop is asynchronously cleared when the device is selected.
Spec Number 518063
6
HS-82C12RH
Logic Diagram
INT
23
DEVICE
DS1
DATA OUT ENABLE
LATCH RESET
SELECT
13
DI0
3
DO0
4
DS2
D
E
Q
TSB
TSB
TSB
TSB
TSB
TSB
TSB
TSB
Q
S
R
R
R
R
R
R
R
R
D
C
Q
Q
STB
SERVICE
REQUEST
FLIP-FLOP
DI1
5
DO1
6
11
D
E
Q
Q
CLR
14
DI2
7
DO2
8
D
E
Q
Q
LATCH CLOCK
DI3
9
DO3
10
D
E
Q
Q
MD
2
DI4
16
DO4
15
D
E
Q
Q
DI5
18
DO5
17
D
E
Q
Q
DI6
20
DO6
19
D
E
Q
Q
DI7
22
DO7
21
D
E
Q
Q
TRUTH TABLE 1. DATA OUT
TRUTH TABLE 2. INT
STB
MD
0
DS1 • DS2
DATA OUT EQUALS
CLR
DS1 • DS2
STB
Q*
0
INT
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
High Z State
High Z State
Data Latch
Data Latch
Data Latch
Data In
0 RESET
0
0
0
1
1
0
0
1
0
1
1
1
1
0
0
1
0
1 RESET
0
1
1
0
0
0
0
0
0
* Internal Service Request Flip-Flop
1
Data In
1
Data In
Spec Number 518063
7
HS-82C12RH
Metallization Topology
DIE DIMENSIONS:
90 x 76 x 14 ± 1mils
METALLIZATION:
Type: AlSi
Thickness: 11kÅ ± 2kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ± 1kÅ
Metallization Mask Layout
HS-82C12RH
(22) DI7
DO0 (4)
DI1 (5)
(21) DO7
(20) DI6
DO1 (6)
(19) DO6
(18) DI5
DI2 (7)
DO2 (8)
DI3 (9)
(17) DO5
(16) DI4
(15) DO4
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 518063
8
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