HIP6002 [INTERSIL]
Rectifier (PWM) Controller and Output Voltage Monitor; 整流器( PWM)控制器和输出电压监视器![HIP6002](http://pdffile.icpdf.com/pdf1/p00054/img/icpdf/HIP6002_280923_icpdf.jpg)
型号: | HIP6002 |
厂家: | ![]() |
描述: | Rectifier (PWM) Controller and Output Voltage Monitor |
文件: | 总12页 (文件大小:214K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HIP6002
Data Sheet
March 2000
File Number 4270.2
Rectifier (PWM) Controller and Output
Voltage Monitor
Features
• Drives Two N-Channel MOSFETs
• Operates From +5V or +12V Input
The HIP6002 provides complete control and protection for a
DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous-rectified buck
topology. The HIP6002 integrates all of the control, output
adjustment, monitoring and protection functions into a single
package.
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
The output voltage of the converter is easily adjusted and
precisely regulated. The HIP6002 includes a 4-Input
Digital-to-Analog Converter (DAC) that adjusts the output
voltage from 2.0VDC to 3.5VDC in 0.1V increments. The
precision reference and voltage-mode regulator hold the
selected output voltage to within ±1% over temperature and
line voltage variations.
• Excellent Output Voltage Regulation
- ±1% Over Line Voltage and Temperature
• 4-Bit Digital-to-Analog Output Voltage Selection
- Wide Range . . . . . . . . . . . . . . . . . . .2.0VDC to 3.5VDC
- 0.1V Binary Steps
• Power-Good Output Voltage Monitor
The HIP6002 provides simple, single feedback loop, voltage-
mode control with fast transient response. It includes a
200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/µs slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.
• Over-Voltage and Over-Current Fault Monitors
- Does Not Require Extra Current Sensing Element
- Uses MOSFET’s r
DS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator Programmable from
50kHz to Over 1MHz
The HIP6002 monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within ±10%. The HIP6002
protects against over-current conditions by inhibiting PWM
operation. Built-in over-voltage protection triggers an
external SCR to crowbar the input supply. The HIP6002
Applications
• Power Supply for Pentium®, Pentium Pro, PowerPC™ and
Alpha™ Microprocessors
• High-Power 5V to 3.xV DC-DC Regulators
• Low-Voltage Distributed Power Supplies
monitors the current by using the r
of the upper
DS(ON)
MOSFET which eliminates the need for a current sensing
resistor.
Ordering Information
TEMP.
PKG.
NO.
o
Pinout
PART NUMBER RANGE ( C)
PACKAGE
20 Ld SOIC
HIP6002 (SOIC)
TOP VIEW
HIP6002CB 0 to 70
M20.3
1
2
3
4
5
6
7
8
9
RT
VSEN
OCSET
SS
20
19
OVP
18 VCC
VID0
VID1
VID2
VID3
EN
17 LGATE
16 PGND
15
BOOT
14 UGATE
13 PHASE
12
COMP
PGOOD
Alpha Micro™ is a trademark of Digital Computer Equipment Corporation.
Pentium® is a registered trademark of Intel Corporation.
PowerPC™ is a registered trademark of IBM.
FB 10
11 GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000
1
HIP6002
Typical Application
+12V
V
= +5V OR +12V
IN
VCC
PGOOD
OCSET
EN
MONITOR AND
PROTECTION
SS
BOOT
OVP
RT
OSC
UGATE
PHASE
VID0
VID1
VID2
VID3
+V
OUT
HIP6002
D/A
LGATE
PGND
-
+
+
-
FB
COMP
GND
VSEN
Block Diagram
VCC
VSEN
POWER-ON
RESET (POR)
110%
EN
+
-
PGOOD
90%
+
-
OVER-
10µA
VOLTAGE
115%
+
OVP
SS
-
SOFT-
START
+
-
OCSET
OVER-
BOOT
CURRENT
UGATE
200µA
4V
REFERENCE
PHASE
PWM
VID0
VID1
VID2
VID3
COMPARATOR
D/A
CONVERTER
(DAC)
DACOUT
GATE
CONTROL
LOGIC
INHIBIT
PWM
+
+
-
-
ERROR
AMP
LGATE
PGND
GND
FB
COMP
RT
OSCILLATOR
2
HIP6002
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V
CC
Thermal Resistance (Typical, Note 1)
θJA ( C/W)
Boot Voltage, V
- V
. . . . . . . . . . . . . . . . . . . . . . . . +15V
BOOT
PHASE
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to V
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . 150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
115
o
+ 0.3V
CC
o
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2
o
Operating Conditions
(SOIC - Lead Tips Only)
Supply Voltage, V
CC
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . . 0 to 70 C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0 C to 125 C
. . . . . . . . . . . . . . . . . . . . . . . . . +12V to ±10%
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details.
JA
Electrical Specifications Recommended Operating Conditions, unless otherwise noted
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
EN = V ; UGATE and LGATE Open
CC
-
-
5
-
mA
CC
Shutdown Supply
EN = 0V
50
100
µA
POWER-ON RESET
Rising V
CC
Threshold
Threshold
V
V
V
= 4.5V
= 4.5V
= 4.5V
-
-
10.4
V
V
V
V
OCSET
OCSET
OCSET
Falling V
8.2
0.8
-
-
-
-
2.0
-
CC
Enable - Input threshold Voltage
Rising V Threshold
1.26
OCSET
OSCILLATOR
Free Running Frequency
Programmable Variation
Ramp Amplitude
R
= OPEN
185
-15
-
200
-
215
+15
-
kHz
%
T
6kΩ < R to GND < 200kΩ
T
∆V
R
= OPEN
1.9
V
OSC
T
P-P
REFERENCE AND DAC
DACOUT Voltage Accuracy
ERROR AMPLIFIER
DC Gain
-1.0
-
+1.0
%
G
-
-
-
88
15
6
-
-
-
dB
0
Gain-Bandwidth Product
Slew Rate
GBW
SR
MHz
V/µs
COMP = 10pF
GATE DRIVERS
Upper Gate Source
Upper Gate Sink
I
V
- V
= 12V, V
UGATE
= 6V
350
500
5.5
450
3.5
-
10
-
mA
Ω
UGATE
BOOT
PHASE
R
I
= 0.3A
-
300
-
UGATE
LGATE
Lower Gate Source
Lower Gate Sink
I
V
= 12V, V
= 6V
mA
Ω
LGATE
CC
LGATE
R
I
= 0.3A
6.5
LGATE
LGATE
PROTECTION
Over-Voltage Trip
OCSET Current Source
OVP Sourcing Current
Soft Start Current
POWER GOOD
% Over Nominal DACOUT Voltage
-
170
60
-
115
200
-
120
%
µA
mA
µA
I
V
V
= 4.5V
230
OCSET
OCSET
DC
I
= 5.5V, V
= 0V
-
-
OVP
SEN
OVP
I
10
SS
Upper Threshold (V
Lower Threshold (V
/DACOUT)
/DACOUT)
V
V
Rising
Falling
106
-
-
111
%
%
%
V
SEN
SEN
SEN
89
-
94
-
SEN
Hysteresis (V
/DACOUT)
SEN
Upper and Lower Threshold
= -5mA
2
PGOOD Voltage Low
V
I
-
0.5
-
PGOOD
PGOOD
3
HIP6002
Typical Performance Curves
80
70
60
50
40
30
20
10
0
C
= C = C
LOWER GATE
UPPER
1000
C = 3300pF
GATE
R
PULLUP
T
R
TO V
PULLDOWN
T
TO +12V
SS
100
10
C
= 1000pF
GATE
C
= 10pF
GATE
100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
10
100
SWITCHING FREQUENCY (kHz)
1000
FIGURE 1. R RESISTANCE vs FREQUENCY
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
T
VID0-3 (Pins 4-7)
Functional Pin Description
VID0-3 are the input pins to the 4-bit DAC. The states of
these four pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the converter output
voltage. It also sets the PGOOD and OVP thresholds. Table
1 specifies DACOUT for the 16 combinations of DAC inputs.
1
2
3
4
5
6
7
8
9
RT
VSEN
OCSET
SS
20
19
OVP
18 VCC
VID0
VID1
VID2
VID3
EN
17 LGATE
16 PGND
EN (Pin 8)
15
BOOT
This pin is the open-collector enable pin. Pull this pin below
1V to disable the converter. In shutdown, the soft start pin is
discharged and the UGATE pin is held low.
14 UGATE
13 PHASE
12
COMP
PGOOD
COMP (Pin 9) and FB (Pin 10)
FB 10
11 GND
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
VSEN (Pin 1)
This pin is connected to the converters output voltage. The
PGOOD and OVP comparator circuits use this signal to
report output voltage status and for overvoltage protection.
GND (Pin 11)
OCSET (Pin 2)
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
Connect a resistor (R
OCSET
) from this pin to the drain of the
upper MOSFET. R
, an internal 200µA current source
OCSET
PGOOD (Pin 12)
(I
), and the upper MOSFET on-resistance (r
OCS
) set
DS(ON)
PGOOD is an open collector output used to indicate the
status of the converter output voltage. This pin is pulled low
when the converter output is not within ±10% of the
DACOUT reference voltage.
the converter over-current (OC) trip point according to the
following equation:
I
• R
OCSET
OCS
I
= -------------------------------------------
PEAK
r
DS(ON)
PHASE (Pin 13)
Connect the PHASE pin to the upper MOSFET source. This
input pin is used to monitor the voltage drop across the
MOSFET for over-current protection. This pin also provide
the return path for the upper gate drive.
An over-current trip cycles the soft-start function.
SS (Pin 3)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10µA current source, sets the soft-
start interval of the converter.
UGATE (Pin 14)
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.
4
HIP6002
BOOT (Pin 15)
Soft Start
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
The POR function initiates the soft start sequence. An
internal 10µA current source charges an external capacitor
(C ) on the SS pin to 4V. Soft start clamps the error
SS
amplifier output (COMP pin) and reference input (+
terminal of error amp) to the SS pin voltage. Figure 3
PGND (Pin 16)
This is the power ground connection. Tie the lower MOSFET
source to this pin.
shows the soft start interval with C = 0.1µF. Initially the
SS
clamp on the error amplifier (COMP pin) controls the
converter’s output voltage. At t1 in Figure 3, the SS voltage
reaches the valley of the oscillator’s triangle wave. The
oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t2. With
sufficient output voltage, the clamp on the reference input
controls the output voltage. This is the interval between t2
and t3 in Figure 3. At t3 the SS voltage exceeds the
DACOUT voltage and the output voltage is in regulation.
This method provides a rapid and controlled output voltage
rise. The PGOOD signal toggles ‘high’ when the output
voltage (VSEN pin) is with in ±5% of DACOUT. The 2%
hysteresis built into the power good comparators prevents
PGOOD oscillation due to nominal output voltage ripple.
LGATE (Pin 17)
Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.
VCC (Pin 18)
Provide a 12V bias supply for the chip to this pin.
OVP (Pin 19)
The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition.
RT (Pin 20)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R ) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
T
6
5 • 10
Fs ≈ 200kHz + --------------------
(R to GND)
R (kΩ)
T
T
PGOOD
(2V/DIV)
Conversely, connecting a pull-up resistor (R ) from this pin
T
to V
reduces the switching frequency according to the
0V
CC
following equation:
7
SOFT-START
(1V/DIV)
4 • 10
Fs ≈ 200kHz – --------------------
(R to 12V)
T
R (kΩ)
T
OUTPUT
VOLTAGE
(1V/DIV)
Functional Description
0V
Initialization
0V
The HIP6002 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the input supply voltages and the enable (EN) pin. The POR
monitors the bias voltage at the VCC pin and the input
t
t
t
3
1
2
TIME (5ms/DIV)
FIGURE 3. SOFT START INTERVAL
Over-Current Protection
The over-current function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
voltage (V ) on the OCSET pin. The level on OCSET is
equal to V less a fixed voltage drop (see over-current
IN
IN
protection). With the EN pin held to V , the POR function
CC
initiates soft start operation after both input supply voltages
exceed their POR thresholds. For operation with a single
r
to monitor the current. This method enhances the
DS(ON)
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
+12V power source, V and V
are equivalent and the
IN
CC
+12V power source must exceed the rising V
before POR initiates operation.
threshold
CC
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
)
OCSET
The Power-On Reset (POR) function inhibits operation with
the chip disabled (EN pin low). With both input supplies
above their POR thresholds, transitioning the EN pin high
initiates a soft start interval.
programs the over-current trip level. An internal 200µA current
sink develops a voltage across R that is referenced to
OCSET
. When the voltage across the upper MOSFET (also
V
IN
referenced to V ) exceeds the voltage across R
, the
IN OCSET
over-current function initiates a soft-start sequence. The soft-
start function discharges C with a 10µA current sink and
SS
5
HIP6002
(DAC). The level of DACOUT also sets the PGOOD and
OVP thresholds. Table 1 specifies the DACOUT voltage for
the 16 combinations of open or short connections on the VID
pins. The output voltage should not be adjusted while the
converter is delivering power. Remove input power or inhibit the
converter (EN pin to GND) before changing the output voltage.
Adjusting the output voltage during operation could toggle the
PGOOD signal and exercise the overvoltage protection.
4V
2V
0V
15A
10A
5A
The DAC function is a precision non-inverting summation
amplifier shown in Figure 5. The resistor values shown are
only approximations of the actual precision values used.
Grounding any combination of the VID pins increases the
DACOUT voltage. The ‘open’ circuit voltage on the VID pins
is the band gap reference voltage, 1.26V.
0A
TIME (20ms/DIV)
TABLE 1. OUTPUT VOLTAGE PROGRAM
FIGURE 4. OVER-CURRENT OPERATION
PIN NAME
NOMINAL
DACOUT
VOLTAGE
inhibits PWM operation. The soft-start function recharges
, and PWM operation resumes with the error amplifier
VID3
1
VID2
VID1
1
VID0
1
C
SS
clamped to the SS voltage. Should an overload occur while
recharging C , the soft start function inhibits PWM operation
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
SS
1
1
0
while fully charging C to 4V to complete its cycle. Figure 4
SS
1
0
1
shows this operation with an overload condition. Note that the
inductor current increases to over 15A during the C
SS
1
0
0
charging interval and causes an over-current trip. The
converter dissipates very little power with this method. The
measured input power for the conditions of Figure 4 is 2.5W.
1
1
1
1
1
0
The over-current function will trip at a peak inductor current
1
0
1
(I
determined by:
PEAK)
I
• R
1
0
0
OCSET
OCSET
I
= ---------------------------------------------------
PEAK
r
DS(ON)
0
1
1
where I
is the internal OCSET current source (200µA -
OCSET
0
1
0
typical). The OC trip point varies mainly due to the MOSFET’s
variations. To avoid over-current tripping in the normal
0
0
1
r
DS(ON)
operating load range, find the R
equation above with:
resistor from the
OCSET
0
0
0
0
1
1
1. The maximum r
temperature.
at the highest junction
DS(ON)
0
1
0
2. The minimum I
from the Specification Table.
> I + (∆I)/2, where ∆I
is the output inductor ripple current.
OCSET
0
0
1
3. Determine I
PEAK
for I
PEAK OUT(MAX)
0
0
0
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
NOTE: 0 = connected to GND or V , 1 = OPEN.
SS
A small ceramic capacitor should be placed in parallel with
R
to smooth the voltage across R in the
OCSET
OCSET
presence of switching noise on the input voltage.
Output Voltage Program
The output voltage of a HIP6002 converter is digitally
programmed to levels between 2VDC and 3.5VDC. The
voltage identification (VID) pins program an internal voltage
reference (DACOUT) with a 4-bit digital-to-analog converter
6
HIP6002
+V
IN
BAND GAP
REFERENCE
BOOT
D1
Q1
L
C
O
BOOT
ERROR
AMPLIFIER
V
OUT
1.26V
HIP6002
DACOUT
PHASE
+
-
21.5kΩ
+
-
SS
COMP
VID0
VID1
VID2
VID3
C
+12V
Q2
O
10.7kΩ
5.4kΩ
2.7kΩ
1.7kΩ
VCC
C
VCC
C
SS
DAC
GND
FB
2.9kΩ
FIGURE 7. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
FIGURE 5. DAC FUNCTION SCHEMATIC
Figure 7 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
Application Guidelines
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
Layout Considerations
SS
close to the SS pin because the internal current source is
only 10µA. Provide local V decoupling between VCC and
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
CC
GND pins. Locate the capacitor, C
as close as practical
BOOT
to the BOOT and PHASE pins.
Feedback Compensation
Figure 8 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
) is regulated to the Reference voltage level. The error
OUT
Figure 6 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 6 should be located as close together as possible.
amplifier (Error Amp) output (V ) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V at the
PHASE node. The PWM wave is smoothed by the output
E/A
IN
filter (L and C ).
O
O
Please note that the capacitors C and C each represent
IN
O
numerous physical capacitors. Locate the HIP6002 within 3
inches of the MOSFETs, Q1 and Q2. The circuit traces for the
MOSFETs’ gate and source connections from the HIP6002
must be sized to handle up to 1A peak current.
The modulator transfer function is the small-signal transfer
function of V /V . This function is dominated by a DC
OUT E/A
Gain and the output filter (L and C ), with a double pole
O
O
break frequency at F and a zero at F
. The DC Gain of
LC
ESR
the modulator is simply the input voltage (V ) divided by the
IN
peak-to-peak oscillator voltage ∆V
.
OSC
V
IN
Modulator Break Frequency Equations
HIP6002
1
1
F
= --------------------------------------
F
= --------------------------------------------
ESR
LC
2π • (ESR • C
)
2π •
L • C
O O
O
UGATE
Q1
Q2
L
O
V
OUT
PHASE
The compensation network consists of the error amplifier
(internal to the HIP6002) and the impedance networks Z
IN
C
IN
C
O
LGATE
PGND
D2
and Z . The goal of the compensation network is to
FB
provide a closed loop transfer function with the highest 0dB
crossing frequency (f ) and adequate phase margin.
0dB
Phase margin is the difference between the closed loop
phase at f and 180 degrees. The equations below relate
RETURN
0dB
FIGURE 6. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 9. Use
these guidelines for locating the poles and zeros of the
compensation network:
7
HIP6002
multiplying the modulator transfer function to the
V
IN
compensation transfer function and plotting the gain.
OSC
DRIVER
DRIVER
PWM
L
The compensation gain uses external impedance networks
O
COMPARATOR
V
OUT
Z
and Z to provide a stable, high bandwidth (BW) overall
FB
IN
-
PHASE
+
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
∆V
OSC
C
O
ESR
(PARASITIC)
Z
FB
V
E/A
Z
-
IN
100
+
F
F
P1
F
F
Z2
Z1
P2
REFERENCE
ERROR
AMP
80
60
40
20
0
OPEN LOOP
ERROR AMP GAIN
DETAILED COMPENSATION COMPONENTS
20LOG
(R2/R1)
Z
FB
V
OUT
C2
20LOG
Z
IN
(V /∆V
)
IN OSC
C1
C3
R3
R2
COMPENSATION
GAIN
-20
-40
-60
MODULATOR
R1
GAIN
CLOSED LOOP
GAIN
COMP
F
LC
F
FB
ESR
100K
FREQUENCY (Hz)
-
+
10
100
1K
10K
1M
10M
HIP6002
DACOUT
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FIGURE 8. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Compensation Break Frequency Equations
1
1
F
= ----------------------------------
2π • R2 • C1
F
= ------------------------------------------------------
Z1
P1
C1 • C2
----------------------
2π • R2 •
C1 + C2
1
1
----------------------------------
F
= -----------------------------------------------------
2π • (R1 + R3) • C3
F
=
Z2
P2
2π • R3 • C3
1. Pick Gain (R2/R1) for desired converter bandwidth
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (effective series resistance) and
voltage rating requirements rather than actual capacitance
requirements.
ST
2. Place 1 Zero Below Filter’s Double Pole (~75% F
)
LC
ND
3. Place 2
Zero at Filter’s Double Pole
ST
4. Place 1 Pole at the ESR Zero
ND
5. Place 2
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible.
Be careful not to add inductance in the circuit board wiring
that could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1µF
ceramic capacitors in the 1206 surface-mount package.
Figure 9 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 9. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F with the capabilities of
P2
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 9 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
8
HIP6002
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor's ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with your
capacitor supplier and measure the capacitor’s impedance with
frequency to select a suitable component. In most cases,
multiple electrolytic capacitors of small case size perform better
than a single large case capacitor.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surge-
current at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.
V
- V
V
OUT
V
IN
IN
OUT
------------------------------- ---------------
∆I =
•
∆V
OUT
= ∆I x ESR
Fs x L
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
MOSFET Selection/Considerations
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6002 will provide either 0% or 100% duty cycle in response
to a load transient. The response time is the time required to
slew the inductor current from an initial current value to the
transient current level. During this interval the difference
between the inductor current and the transient current level
must be supplied by the output capacitor. Minimizing the
response time can minimize the output capacitance required.
The HIP6002 requires 2 N-channel power MOSFETs. These
should be selected based upon r
, gate supply
DS(ON)
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). Only the
upper MOSFET has switching losses, since the Schottky
rectifier clamps the switching node before the synchronous
rectifier turns on. These equations assume linear
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
L
× I
TRAN
L
× I
TRAN
O
O
t
= ------------------------------
t
= -------------------------------
1
2
FALL
2
RISE
V
V
– V
OUT
P
= I x r
O
x D + Io x V x t
x Fs
OUT
UPPER
DS(ON)
IN SW
IN
2
P
= I x r
x (1 - D)
LOWER
O
DS(ON)
where: I
TRAN
response time to the application of load, and t
is the transient load current step, t
is the
is the
RISE
Where: D is the duty cycle = V ,
/V
is the switching interval, and
FALL
OUT IN
SW
Fs is the switching frequency.
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
DACOUT setting. Be sure to check both of these equations
at the minimum and maximum output levels for the worst
case response time. With a +12V input, and output voltage
t
voltage-current transitions and do not adequately model
power loss due the reverse-recovery of the lower MOSFET’s
body diode. The gate-charge losses are dissipated by the
HIP6002 and don't heat the MOSFETs. However, large gate-
level equal to DACOUT, t
FALL
is the longest response time.
charge increases the switching interval, t
SW
which increases
9
HIP6002
the upper MOSFET switching losses. Ensure that both
MOSFETs are within their maximum junction temperature at
+12V
high ambient temperature by calculating the temperature rise
according to package thermal-resistance specifications. A
separate heatsink may be necessary depending upon
MOSFET power, package type, ambient temperature and air
flow.
+5V OR LESS
VCC
BOOT
HIP6002
Q1
UGATE
PHASE
Standard-gate MOSFETs are normally recommended for
use with the HIP6002. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute
gate-to-source voltage rating determine whether logic-level
MOSFETs are appropriate.
NOTE:
G-S ≈ V -5V
V
CC
D2
Q2
-
LGATE
PGND
+
NOTE:
VG-S ≈ V
CC
GND
+12V
D
BOOT
FIGURE 11. UPPER GATE DRIVE - DIRECT V
DRIVE OPTION
CC
+
-
V
+5V OR +12V
D
VCC
Schottky Selection
BOOT
HIP6002
C
BOOT
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency will drop
one or two percent as a result. The diode’s rated reverse
breakdown voltage must be greater than the maximum input
voltage.
Q1
UGATE
PHASE
NOTE:
G-S ≈ V -V
V
CC
D
Q2
D2
-
LGATE
PGND
+
NOTE:
VG-S ≈ V
CC
GND
FIGURE 10. UPPER GATE DRIVE - BOOTSTRAP OPTION
HIP6002 DC-DC Converter Application
Circuit
Figure 10 shows the upper gate drive (BOOT pin) supplied
by a bootstrap circuit from V . The boot capacitor, C
CC BOOT
Figure 12 shows an application circuit of a DC-DC Converter
for an Intel Pentium Pro microprocessor. Detailed
information on the circuit, including a complete
Bill-of-Materials and circuit board description, can be found
in Application Note AN9668. See Intersil’s home page on the
web: www.intersil.com or Intersil AnswerFAX
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
CC
less the boot diode drop (V ) when the lower MOSFET, Q2
D
turns on. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to V
CC
.
(321-724-7800) document # 99668.
Figure 11 shows the upper gate drive supplied by a direct
connection to V . This option should only be used in
CC
converter systems where the main input voltage is +5 VDC or
less. The peak upper gate-to-source voltage is approximately
V
less the input supply. For + 5V main power and + 12
CC
VDC for the bias, the gate-to-source voltage of Q1 is 7V. A
logic-level MOSFET is a good choice for Q1 and a logic-level
MOSFET can be used for Q2 if its absolute gate-to-source
voltage rating exceeds the maximum voltage applied to V
.
CC
10
HIP6002
L1 - 1µH
F1
+5V
OR
+12V
V
=
IN
C1 - C4
2x 1µF
2N6394
4x 330µF
+12V
2K
D1
0.1µF
100pF
1.1K
10K
VCC
18
OVP
19
2
12
OCSET
PGOOD
BOOT
EN
SS
8
3
MONITOR
AND
PROTECTION
15
1
VSEN
RT
0.1µF
20
0.1µF
OSC
14
13
UGATE
PHASE
L0
Q1
Q2
4
5
6
7
VID0
VID1
VID2
VID3
3µH
+V
O
HIP6002
D/A
D2
C15 - C21
17
16
LGATE
PGND
-
+
+
-
7x 1000µF
FB
10
9
11
COMP
GND
2.2nF
8.2nF
0.1µF
20K
15
1.33K
Component Selection Notes:
C15 - C21 each 1000µF 6.3W VDC, Sanyo MV-GX or Equivalent.
C1 - C4 each 330µF 25W VDC, Sanyo MV-GX or Equivalent.
L0 - Core: Micrometals T50-52B; Each Winding: 10 Turns of 16AWG.
L1 - Core: Micrometals T50-52; Winding: 5 Turns of 18AWG.
D1 - 1N4148 or Equivalent.
D2 - 3A, 40V Schottky, Motorola MBR340 or Equivalent.
Q1 - Q2 - Intersil MOSFET; RFP70N03.
FIGURE 12. PENTIUM PRO DC-DC CONVERTER
11
HIP6002
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
N
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MIN MAX
MILLIMETERS
E
SYMBOL
MIN
2.35
0.10
0.33
0.23
12.60
7.40
MAX
2.65
0.30
0.51
0.32
13.00
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926 0.1043
0.0040 0.0118
-
-
1
2
3
L
0.013
0.0200
9
SEATING PLANE
A
0.0091 0.0125
0.4961 0.5118
0.2914 0.2992
0.050 BSC
-
-A-
o
3
h x 45
D
4
-C-
1.27 BSC
-
α
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
20
20
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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12
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