HIP6004_技术文档

HIP6004

Data Sheet

March 2000

File Number 4275.2

Buck and Synchronous-Rectiﬁer (PWM)

Controller and Output Voltage Monitor

Features

• Drives Two N-Channel MOSFETs

• Operates from +5V or +12V Input

The HIP6004 provides complete control and protection for a

DC-DC converter optimized for high-performance

microprocessor applications. It is designed to drive two

N-Channel MOSFETs in a synchronous-rectiﬁed buck

topology. The HIP6004 integrates all of the control, output

adjustment, monitoring and protection functions into a single

package.

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast Transient Response

- High-Bandwidth Error Ampliﬁer

- Full 0% to 100% Duty Ratio

The output voltage of the converter is easily adjusted and

precisely regulated. The HIP6004 includes a 5-input

digital-to-analog converter (DAC) that adjusts the output

• Excellent Output Voltage Regulation

- ±1% Over Line Voltage and Temperature

• 5-Bit Digital-to-Analog Output Voltage Selection

voltage from 2.1V

to 3.5V

in 0.1V increments and from

DC

in 0.05V steps. The precision reference

1.3V

to 2.1V

- Wide Range . . . . . . . . . . . . . . . . . . . 1.3V

- 0.1V Binary Steps. . . . . . . . . . . . . . . 2.1V

- 0.05V Binary Step. . . . . . . . . . . . . . . 1.3V

to 3.5V

to 2.1V

DC

and voltage-mode regulator hold the selected output voltage

to within ±1% over temperature and line voltage variations.

The HIP6004 provides simple, single feedback loop,

voltage-mode control with fast transient response. It includes

a 200kHz free-running triangle-wave oscillator that is

adjustable from below 50kHz to over 1MHz. The error

ampliﬁer features a 15MHz gain-bandwidth product and

6V/µs slew rate which enables high converter bandwidth for

fast transient performance. The resulting PWM duty ratio

ranges from 0% to 100%.

• Power-Good Output Voltage Monitor

• Over-Voltage and Over-Current Fault Monitors

- Does Not Require Extra Current Sensing Element,

Uses MOSFETs r

DS(ON)

• Small Converter Size

- Constant Frequency Operation

- 200kHz Free-Running Oscillator Programmable from

50kHz to over 1MHz

The HIP6004 monitors the output voltage with a window

comparator that tracks the DAC output and issues a Power

Good signal when the output is within ±10%. The HIP6004

protects against over-current conditions by inhibiting PWM

operation. Built-in over-voltage protection triggers an

external SCR to crowbar the input supply. The HIP6004

Applications

•

Power Supply for Pentium®, Pentium Pro, PowerPC™ and

Alpha™ Microprocessors

•

High-Power 5V to 3.xV DC-DC Regulators

Low-Voltage Distributed Power Supplies

monitors the current by using the r

of the upper

DS(ON)

MOSFET which eliminates the need for a current sensing

resistor.

Pinout

HIP6004

(SOIC)

TOP VIEW

Ordering Information

TEMP.

PKG.

NO.

o

PART NUMBER RANGE ( C)

HIP6004CB 0 to 70

This data sheet describes a pre-released product.

PACKAGE

20 Ld SOIC

M20.3

1

2

3

4

5

6

7

8

9

RT

VSEN

OCSET

SS

20

19

OVP

18 VCC

VID0

17 LGATE

16 PGND

VID1

VID2

BOOT

15

VID3

14 UGATE

13 PHASE

VID4

12

COMP

PGOOD

Alpha Micro™ is a trademark of Digital Computer Equipment Corporation.

Pentium® is a registered trademark of Intel Corporation.

PowerPC™ is a registered trademark of IBM.

FB 10

11 GND

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

HIP6004

Typical Application

+12V

V

= +5V or +12V

IN

VCC

PGOOD

OCSET

EN

MONITOR AND

PROTECTION

SS

BOOT

OVP

RT

OSC

UGATE

PHASE

VID0

VID1

VID2

VID3

VID4

+V

OUT

HIP6004

D/A

LGATE

PGND

-

+

-

FB

COMP

GND

VSEN

Block Diagram

VCC

VSEN

POWER-ON

RESET (POR)

110%

+

-

PGOOD

90%

+

-

OVER-

10µA

115%

VOLTAGE

+

OVP

SS

-

SOFT-

START

+

-

OCSET

OVER-

CURRENT

BOOT

UGATE

200µA

4V

REFERENCE

PHASE

PWM

COMPARATOR

VID0

VID1

VID2

VID3

VID4

D/A

CONVERTER

(DAC)

DACOUT

GATE

CONTROL

LOGIC

INHIBIT

PWM

+

-

ERROR

AMP

LGATE

PGND

GND

FB

COMP

RT

OSCILLATOR

2

HIP6004

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V

Thermal Resistance (Typical, Note 1)

θ_JA( C/W)

CC

Boot Voltage, V

- V

. . . . . . . . . . . . . . . . . . . . . . . . +15V

BOOT

PHASE

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

118

o

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2

o

Operating Conditions

(SOIC - Lead Tips Only)

Supply Voltage, V

CC

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0 C to 125 C

. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details.

JA

Electrical Speciﬁcations Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER

VCC SUPPLY CURRENT

Nominal Supply

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

UGATE and LGATE Open

-

5

-

mA

CC

POWER-ON RESET

Rising VCC Threshold

Falling VCC Threshold

V

= 4.5V

-

8.2

-

10.4

V

OCSET

= 4.5V

-

OCSET

Rising V

OCSET

Threshold

1.26

OSCILLATOR

Free Running Frequency

Total Variation

RT = OPEN

185

-15

-

200

-

215

+15

-

kHz

%

6kΩ < RT to GND < 200kΩ

RT = Open

Ramp Amplitude

∆V

OSC

1.9

V

P-P

REFERENCE AND DAC

DACOUT Voltage Accuracy

ERROR AMPLIFIER

DC Gain

-1.0

-

+1.0

%

-

88

15

6

-

dB

Gain-Bandwidth Product

Slew Rate

GBW

SR

MHz

V/µs

COMP = 10pF

GATE DRIVERS

Upper Gate Source

Upper Gate Sink

I

V

- V

= 12V, V

UGATE

= 6V

350

500

5.5

-

10

-

mA

Ω

UGATE

BOOT

PHASE

R

I

= 0.3A

-

300

-

UGATE

LGATE

Lower Gate Source

Lower Gate Sink

I

VCC = 12V, V

LGATE

= 6V

450

3.5

mA

Ω

LGATE

R

I

= 0.3A

6.5

LGATE

PROTECTION

Over-Voltage Trip (V

/DACOUT)

-

170

60

-

115

200

-

120

%

µA

mA

µA

SEN

OCSET Current Source

OVP Sourcing Current

Soft Start Current

I

V

= 4.5V

230

OCSET

DC

I

= 5.5V, V

= 0V

-

OVP

SEN

OVP

I

10

SS

POWER GOOD

Upper Threshold (V

Lower Threshold (V

/ DACOUT)

VSEN Rising

VSEN Falling

106

-

111

%

V

SEN

89

-

94

-

Hysteresis (VSEN / DACOUT)

PGOOD Voltage Low

Upper and Lower Threshold

= -5mA

2

V

I

-

0.5

-

PGOOD

3

HIP6004

Typical Performance Curves

80

70

60

50

40

30

20

C

= 3300pF

GATE

1000

R

PULLUP

T

C

= C = C

LOWER GATE

UPPER

TO +12V

100

10

C

= 1000pF

GATE

R

PULLDOWN TO V

SS

T

C

= 10pF

800

GATE

10

0

10

100

SWITCHING FREQUENCY (kHz)

1000

100

200

300

400

500

600

700

900 1000

SWITCHING FREQUENCY (kHz)

FIGURE 1. R RESISTANCE vs FREQUENCY

FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

T

VID0-4 (Pins 4-8)

Functional Pin Description

VID0-4 are the input pins to the 5-bit DAC. The states of

these ﬁve pins program the internal voltage reference

(DACOUT). The level of DACOUT sets the converter output

voltage. It also sets the PGOOD and OVP thresholds. Table

1 speciﬁes DACOUT for the 32 combinations of DAC inputs.

1

2

3

4

5

6

7

8

9

RT

VSEN

OCSET

SS

20

19

OVP

18 VCC

VID0

17 LGATE

16 PGND

15 BOOT

14 UGATE

13 PHASE

COMP (Pin 9) and FB (Pin 10)

VID1

COMP and FB are the available external pins of the error

ampliﬁer. The FB pin is the inverting input of the error

ampliﬁer and the COMP pin is the error ampliﬁer output.

These pins are used to compensate the voltage-control

feedback loop of the converter.

VID2

VID3

VID4

12

COMP

PGOOD

FB 10

11 GND

GND (Pin 11)

Signal ground for the IC. All voltage levels are measured with

respect to this pin.

VSEN (Pin 1)

This pin is connected to the converters output voltage. The

PGOOD and OVP comparator circuits use this signal to

report output voltage status and for overvoltage protection.

PGOOD (Pin 12)

PGOOD is an open collector output used to indicate the

status of the converter output voltage. This pin is pulled low

when the converter output is not within ±10% of the

DACOUT reference voltage.

OCSET (Pin 2)

Connect a resistor (R

OCSET

) from this pin to the drain of the

upper MOSFET. R

, an internal 200µA current source

OCSET

PHASE (Pin 13)

(I

), and the upper MOSFET on-resistance (r

OCS

) set

DS(ON)

Connect the PHASE pin to the upper MOSFET source. This

pin is used to monitor the voltage drop across the MOSFET

for over-current protection. This pin also provides the return

path for the upper gate drive.

the converter over-current (OC) trip point according to the

following equation:

I

• R

OCSET

OCS

I

= -------------------------------------------

PEAK

r

DS(ON)

UGATE (Pin 14)

Connect UGATE to the upper MOSFET gate. This pin

provides the gate drive for the upper MOSFET.

An over-current trip cycles the soft-start function.

SS (Pin 3)

BOOT (Pin 15)

Connect a capacitor from this pin to ground. This capacitor,

along with an internal 10µA current source, sets the soft-

start interval of the converter.

This pin provides bias voltage to the upper MOSFET driver.

A bootstrap circuit may be used to create a BOOT voltage

suitable to drive a standard N-Channel MOSFET.

4

HIP6004

increasing width that charge the output capacitor(s). This

PGND (Pin 16)

interval of increasing pulse width continues to t . With sufficient

output voltage, the clamp on the reference input controls the

2

This is the power ground connection. Tie the lower MOSFET

source to this pin.

output voltage. This is the interval between t and t in Figure 3.

2

3

LGATE (Pin 17)

At t the SS voltage exceeds the DACOUT voltage and the

3

Connect LGATE to the lower MOSFET gate. This pin

provides the gate drive for the lower MOSFET.

output voltage is in regulation. This method provides a rapid

and controlled output voltage rise. The PGOOD signal toggles

‘high’ when the output voltage (VSEN pin) is within ±5% of

DACOUT. The 2% hysteresis built into the power good

comparators prevents PGOOD oscillation due to nominal

output voltage ripple.

VCC (Pin 18)

Provide a 12V bias supply for the chip to this pin.

OVP (Pin 19)

The OVP pin can be used to drive an external SCR in the

event of an overvoltage condition.

PGOOD

(2V/DIV.)

RT (Pin 20)

This pin provides oscillator switching frequency adjustment.

0V

By placing a resistor (R ) from this pin to GND, the nominal

T

200kHz switching frequency is increased according to the

following equation:

SOFT-START

(1V/DIV.)

6

5 • 10

Fs ≈ 200kHz + --------------------

OUTPUT

VOLTAGE

(R to GND)

R (kΩ)

T

(1V/DIV.)

0V

Conversely, connecting a pull-up resistor (R ) from this pin

T

to VCC reduces the switching frequency according to the

0V

t

3

1

2

following equation:

TIME (5ms/DIV.)

7

4 • 10

Fs ≈ 200kHz – --------------------

(R to 12V)

T

R (kΩ)

T

FIGURE 3. SOFT START INTERVAL

Functional Description

Over-Current Protection

The over-current function protects the converter from a

shorted output by using the upper MOSFETs on-resistance,

Initialization

The HIP6004 automatically initializes upon receipt of power.

Special sequencing of the input supplies is not necessary.

The Power-On Reset (POR) function continually monitors

the input supply voltages. The POR monitors the bias

r

to monitor the current. This method enhances the

DS(ON)

converter’s efﬁciency and reduces cost by eliminating a

current sensing resistor.

voltage at the VCC pin and the input voltage (V ) on the

IN

OCSET pin. The level on OCSET is equal to V less a ﬁxed

IN

4V

2V

voltage drop (see over-current protection). The POR function

initiates soft start operation after both input supply voltages

exceed their POR thresholds. For operation with a single

0V

+12V power source, V and V

+12V power source must exceed the rising V

before POR initiates operation.

are equivalent and the

IN

CC

15A

10A

5A

threshold

CC

Soft Start

The POR function initiates the soft start sequence. An internal

0A

10µA current source charges an external capacitor (C ) on

SS

the SS pin to 4V. Soft start clamps the error amplifier output

(COMP pin) and reference input (+ terminal of error amp) to the

SS pin voltage. Figure 3 shows the soft start interval with

TIME (20ms/DIV.)

FIGURE 4. OVER-CURRENT OPERATION

C

= 0.1µF. Initially the clamp on the error amplifier (COMP

SS

The over-current function cycles the soft-start function in a

pin) controls the converter’s output voltage. At t in Figure 3, the

1

hiccup mode to provide fault protection. A resistor (R

)

OCSET

SS voltage reaches the valley of the oscillator’s triangle wave.

The oscillator’s triangular waveform is compared to the ramping

error amplifier voltage. This generates PHASE pulses of

programs the over-current trip level. An internal 200µA current

sink develops a voltage across R that is referenced to

OCSET

. When the voltage across the upper MOSFET (also

V

IN

5

HIP6004

referenced to V ) exceeds the voltage across R

, the

over-current function initiates a soft-start sequence. The soft-

I

• R

OCSET

IN OCSET

OCSET

I

= ---------------------------------------------------

PEAK

r

DS(ON)

start function discharges C with a 10µA current sink and

SS

where I

OCSET

is the internal OCSET current source (200µA

inhibits PWM operation. The soft-start function recharges C

and PWM operation resumes with the error amplifier clamped

to the SS voltage. Should an overload occur while recharging

,

SS

typical). The OC trip point varies mainly due to the MOSFETs

variations. To avoid over-current tripping in the

normal operating load range, find the R

the equation above with:

r

DS(ON)

resistor from

OCSET

C

, the soft start function inhibits PWM operation while fully

SS

charging C to 4V to complete its cycle. Figure 4 shows this

SS

1. The maximum r

2. The minimum I

3. Determine I

where ∆I is the output inductor ripple current.

For an equation for the ripple current see the section under

component guidelines titled ‘Output Inductor Selection’.

at the highest junction temperature.

from the speciﬁcation table.

DS(ON)

OCSET

operation with an overload condition. Note that the inductor

current increases to over 15A during the C charging interval

SS

for

I

> I

+ (∆I) ⁄ 2 ,

PEAK

OUT(MAX)

and causes an over-current trip. The converter dissipates very

little power with this method. The measured input power for the

conditions of Figure 4 is 2.5W.

The over-current function will trip at a peak inductor current

(I

determined by:

PEAK)

TABLE 1. OUTPUT VOLTAGE PROGRAM

PIN NAME

NOMINAL

OUTPUT

VOLTAGE

DACOUT

PIN NAME

NOMINAL

OUTPUT

VOLTAGE

DACOUT

VID4

0

VID3

1

VID2

1

VID1

1

VID0

1

VID4

1

VID3

1

VID2

1

VID1

1

VID0

1

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

NOTE: 0 = connected to GND or V , 1 = OPEN.

SS

A small ceramic capacitor should be placed in parallel with

to smooth the voltage across R in the

presence of switching noise on the input voltage.

VID pins. The output voltage should not be adjusted while

the converter is delivering power. Remove input power

before changing the output voltage. Adjusting the output

voltage during operation could toggle the PGOOD signal

and exercise the overvoltage protection.

R

OCSET

Output Voltage Program

The output voltage of a HIP6004 converter is programmed

The DAC function is a precision non-inverting summation

ampliﬁer shown in Figure 5. The resistor values shown are

only approximations of the actual precision values used.

Grounding any combination of the VID pins increases the

DACOUT voltage. The ‘open’ circuit voltage on the VID pins

is the band gap reference voltage, 1.26V.

to discrete levels between 1.3V

and 3.5V . The

DC

voltage identification (VID) pins program an internal voltage

reference (DACOUT) with a 5-bit digital-to-analog converter

(DAC). The level of DACOUT also sets the PGOOD and

OVP thresholds. Table 1 specifies the DACOUT voltage for

the 32 combinations of open or short connections on the

6

HIP6004

Figure 7 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

BAND GAP

REFERENCE

1.26V

current paths on the SS PIN and locate the capacitor, C

ss

close to the SS pin because the internal current source is

only 10µA. Provide local V decoupling between VCC and

12kΩ

CC

GND pins. Locate the capacitor, C

to the BOOT and PHASE pins.

as close as practical

3.6kΩ

2.7kΩ

5.4kΩ

10.7kΩ

BOOT

ERROR

AMPLIFIER

VID4

VID3

VID2

VID1

VID0

DACOUT

+

-

+

-

COMP

Feedback Compensation

Figure 8 highlights the voltage-mode control loop for a

synchronous-rectiﬁed buck converter. The output voltage

1.7kΩ

(V

) is regulated to the Reference voltage level. The error

OUT

21.5kΩ

DAC

2.9kΩ

ampliﬁer (Error Amp) output (V ) is compared with the

E/A

FB

oscillator (OSC) triangular wave to provide a pulse-width

modulated (PWM) wave with an amplitude of V at the

IN

PHASE node. The PWM wave is smoothed by the output

ﬁlter (L and C ).

O

FIGURE 5. DAC FUNCTION SCHEMATIC

+V

IN

BOOT

C

Application Guidelines

D1

Q1

L

O

BOOT

V

Layout Considerations

OUT

PHASE

VCC

As in any high frequency switching converter, layout is very

important. Switching current from one power device to another

can generate voltage transients across the impedances of the

interconnecting bond wires and circuit traces. These

interconnecting impedances should be minimized by using

wide, short printed circuit traces. The critical components

should be located as close together as possible, using ground

plane construction or single point grounding.

HIP6004

C

+12V

SS

Q2

O

C

VCC

C

SS

GND

FIGURE 7. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

V

IN

HIP6004

V

IN

DRIVER

OSC

PWM

L

O

COMPARATOR

V

OUT

UGATE

Q1

Q2

L

O

V

OUT

PHASE

-

PHASE

+

C

∆V

O

OSC

C

IN

C

ESR

(PARASITIC)

LGATE

PGND

O

D2

Z

FB

V

E/A

-

Z

IN

+

REFERENCE

RETURN

ERROR

AMP

FIGURE 6. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

DETAILED COMPENSATION COMPONENTS

Z

FB

V

OUT

C2

Figure 6 shows the critical power components of the

converter. To minimize the voltage overshoot the

interconnecting wires indicated by heavy lines should be

part of ground or power plane in a printed circuit board. The

components shown in Figure 6 should be located as close

Z

IN

C1

C3

R3

R2

R1

COMP

together as possible. Please note that the capacitors C

FB

IN

-

+

and C each represent numerous physical capacitors.

O

Locate the HIP6004 within 3 inches of the MOSFETs, Q1

and Q2. The circuit traces for the MOSFETs’ gate and

source connections from the HIP6004 must be sized to

handle up to 1A peak current.

HIP6004

DACOUT

FIGURE 8. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

7

HIP6004

The modulator transfer function is the small-signal transfer

function of V /V . This function is dominated by a DC

100

80

60

40

20

0

OUT E/A

Gain and the output ﬁlter (L and C ), with a double pole

F

P1

F

Z2

Z1

P2

O

break frequency at F and a zero at F

. The DC Gain of

LC

ESR

OPEN LOOP

ERROR AMP GAIN

the modulator is simply the input voltage (V ) divided by the

IN

peak-to-peak oscillator voltage ∆V

.

OSC

20LOG

(R /R )

Modulator Break Frequency Equations

2

1

20LOG

(V /∆V

)

IN OSC

1

MODULATOR

GAIN

F

= --------------------------------------

F

= ---------------------------------------

COMPENSATION

GAIN

LC

ESR

2π • ESR • C

2π •

L • C

O O

O

-20

-40

-60

CLOSED LOOP

GAIN

The compensation network consists of the error ampliﬁer

(internal to the HIP6004) and the impedance networks Z

F

LC

F

IN

ESR

100K

FREQUENCY (Hz)

and Z . The goal of the compensation network is to provide

FB

10

100

1K

10K

1M

10M

a closed loop transfer function with the highest 0dB crossing

frequency (f

) and adequate phase margin. Phase margin

and

0dB

FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

is the difference between the closed loop phase at f

0dB

180 degrees. The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 8. Use these guidelines for

locating the poles and zeros of the compensation network:

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to ﬁlter the output and supply

the load transient current. The ﬁltering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

1. Pick Gain (R2/R1) for desired converter bandwidth

ST

2. Place 1 Zero Below Filter’s Double Pole (~75% F

ND

)

LC

3. Place 2

Zero at Filter’s Double Pole

ST

4. Place 1 Pole at the ESR Zero

ND

5. Place 2

Pole at Half the Switching Frequency

6. Check Gain against Error Ampliﬁer’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Modern microprocessors produce transient load rates above

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

Compensation Break Frequency Equations

1

F

= ----------------------------------

2π • R2 • C1

F

= -----------------------------------------------------

Z1

P1

C1 • C2

----------------------

•

2π • R

2

C1 + C2

1

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

speciﬁc decoupling requirements. For example, Intel

recommends that the high frequency decoupling for the

Pentium Pro be composed of at least forty (40) 1µF ceramic

capacitors in the 1206 surface-mount package.

= 2π • (R1 + R3) • C3

= ----------------------------------

Z2

P2

2π • R3 • C3

Figure 9 shows an asymptotic plot of the DC-DC converter’s

gain vs. frequency. The actual Modulator Gain has a high gain

peak due to the high Q factor of the output filter and is not

shown in Figure 9. Using the above guidelines should give a

Compensation Gain similar to the curve plotted. The open

loop error amplifier gain bounds the compensation gain.

Check the compensation gain at F with the capabilities of

P2

the error amplifier. The Closed Loop Gain is constructed on

the log-log graph of Figure 9 by adding the Modulator Gain (in

dB) to the Compensation Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient. An

aluminum electrolytic capacitor’s ESR value is related to the

case size with lower ESR available in larger case sizes.

However, the equivalent series inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient loading.

Unfortunately, ESL is not a specified parameter. Work with

your capacitor supplier and measure the capacitor’s

compensation transfer function and plotting the gain.

The compensation gain uses external impedance networks

Z

and Z to provide a stable, high bandwidth (BW) overall

FB

IN

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

impedance with frequency to select a suitable component. In

8

HIP6004

most cases, multiple electrolytic capacitors of small case size

perform better than a single large case capacitor.

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximately

1/2 the DC load current.

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by the following equations:

For a through hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo

MV-GX or equivalent) may be needed. For surface mount

designs, solid tantalum capacitors can be used, but caution

must be exercised with regard to the capacitor surge current

rating. These capacitors must be capable of handling the

surge-current at power-up. The TPS series available from

AVX, and the 593D series from Sprague are both surge

current tested.

V

- V

OUT

V

OUT

•

IN

Fs x L

∆V

OUT

= ∆I x ESR

∆I =

V

IN

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

MOSFET Selection/Considerations

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

HIP6004 will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

The HIP6004 requires 2 N-Channel power MOSFETs.

These should be selected based upon r

, gate supply

DS(ON)

requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss components;

conduction loss and switching loss. The conduction losses are

the largest component of power dissipation for both the upper

and the lower MOSFETs. These losses are distributed

between the two MOSFETs according to duty factor (see the

equations below). Only the upper MOSFET has switching

losses, since the Schottky rectifier clamps the switching node

before the synchronous rectifier turns on. These equations

assume linear voltage-current transitions and do not

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

adequately model power loss due the reverse-recovery of the

lower MOSFETs body diode. The gate-charge losses are

dissipated by the HIP6004 and don't heat the MOSFETs.

However, large gate-charge increases the switching interval,

L x I

TRAN

OUT

t

=

t

=

FALL

RISE

V

- V

V

OUT

IN

where: I

is the transient load current step, t

is the

TRAN

RISE

t

which increases the upper MOSFET switching losses.

response time to the application of load, and t

SW

FALL

Ensure that both MOSFETs are within their maximum junction

temperature at high ambient temperature by calculating the

temperature rise according to package thermal-resistance

specifications. A separate heatsink may be necessary

depending upon MOSFET power, package type, ambient

temperature and air flow.

response time to the removal of load. With a +5V input

source, the worst case response time can be either at the

application or removal of load and dependent upon the

DACOUT setting. Be sure to check both of these equations

at the minimum and maximum output levels for the worst

case response time. With a +12V input, and output voltage

level equal to DACOUT, t

FALL

is the longest response time.

1

2

P

= Io x r

x D +

Io x V x t x F

IN SW S

UPPER

DS(ON)

Input Capacitor Selection

2

P

= Io x r

x (1 - D)

LOWER

DS(ON)

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time Q1 turns on. Place the

small ceramic capacitors physically close to the MOSFETs

and between the drain of Q1 and the source of Q2.

Where: D is the duty cycle = V

OUT

/ V ,

IN

t

is the switching interval, and

SW

F

is the switching frequency.

S

Standard-gate MOSFETs are normally recommended for

use with the HIP6004. However, logic-level gate MOSFETs

can be used under special circumstances. The input voltage,

upper gate drive level, and the MOSFETs absolute gate-to-

source voltage rating determine whether logic-level

MOSFETs are appropriate.

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

9

HIP6004

+12V

D

BOOT

+5V OR LESS

V

CC

+5V or +12V

+ V

-

D

VCC

BOOT

HIP6004

C

BOOT

Q1

UGATE

PHASE

UGATE

PHASE

NOTE:

_G-S≈ V -5V

NOTE:

_G-S≈ V -V

V

CC

V

CC

D

D2

Q2

D2

Q2

-

LGATE

PGND

LGATE

PGND

-

+

NOTE:

V

_G-S≈ V

CC

V_G-S≈ V

CC

GND

IGURE 11. UPPER GATE DRIVE - DIRECT V

CC

DRIVE OPTION

FIGURE 10. UPPER GATE DRIVE - BOOTSTRAP OPTION

Figure 10 shows the upper gate drive (BOOT pin) supplied

Schottky Selection

by a bootstrap circuit from V . The boot capacitor, C

CC BOOT

Rectifier D2 is a clamp that catches the negative inductor

swing during the dead time between turning off the lower

MOSFET and turning on the upper MOSFET. The diode must

be a Schottky type to prevent the lossy parasitic MOSFET

body diode from conducting. It is acceptable to omit the diode

and let the body diode of the lower MOSFET clamp the

negative inductor swing, but efficiency will drop one or two

percent as a result. The diode's rated reverse breakdown

voltage must be greater than the maximum input voltage.

develops a ﬂoating supply voltage referenced to the PHASE

pin. This supply is refreshed each cycle to a voltage of VCC

less the boot diode drop (V ) when the lower MOSFET, Q2

D

turns on. Logic-level MOSFETs can only be used if the

MOSFETs absolute gate-to-source voltage rating exceeds

the maximum voltage applied to V

CC

.

Figure 11 shows the upper gate drive supplied by a direct

connection to V . This option should only be used in

CC

converter systems where the main input voltage is +5V

or

DC

less. The peak upper gate-to-source voltage is approximately

less the input supply. For +5V main power and +12VDC

V

CC

for the bias, the gate-to-source voltage of Q1 is 7V. A logic-

level MOSFET is a good choice for Q1 and a logic-level

MOSFET can be used for Q2 if its absolute gate-to-source

voltage rating exceeds the maximum voltage applied to V

.

CC

10

HIP6004

HIP6004 DC-DC Converter Application Circuit

Figure 12 shows an application circuit of a DC-DC Converter

for an Intel Pentium Pro microprocessor. Detailed

information on the circuit, including a complete Bill-of-

Materials and circuit board description, can be found in

Application Note AN9672. Intersil AnswerFAX (321-724-

7800) doc. #99672.

L1 - 1µH

F1

+5V

V

=

OR

IN

+12V

C1

5x 1000µF

2x 1µF

2N6394

+12V

2K

D1

0.1µF

1000pF

VCC

OVP

19

18

1K

2

12

15

OCSET

PGOOD

BOOT

MONITOR

AND

PROTECTION

SS

3

1

VSEN

0.1µF

RT 20

0.1µF

OSC

14

13

UGATE

PHASE

Q1

Q2

L2

3µH

4

VID0

5

6

7

8

HIP6004

+V

VID1

VID2

VID3

VID4

O

D/A

D2

17

16

C

LGATE

PGND

-

O

+

-

9x 1000µF

FB

10

9

11

COMP

GND

2.2nF

8.2nF

20K

0.1µF

15

1.33K

Component Selection Notes;

C

- 9 Each 1000µF 6.3W VDC, Sanyo MV-GX or Equivalent

0

C1 - 5 Each 330µF 25W VDC, Sanyo MV-GX or Equivalent

L2 - Core: Micrometals T50-52B; Each Winding: 10 Turns of 16AWG

L1 - Core: Micrometals T50-52; Winding: 5 Turns of 18AWG

D1 - 1N4148 or Equivalent

D2 - 3A, 40V Schottky, Motorola MBR340 or Equivalent

Q1, Q2 - Intersil MOSFET; RFP70N03

FIGURE 12. PENTIUM PRO DC-DC CONVERTER

11

HIP6004

Small Outline Plastic Packages (SOIC)

M20.3 (JEDEC MS-013-AC ISSUE C)

N

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

0.25(0.010)

M

B M

H

AREA

INCHES

MIN MAX

MILLIMETERS

E

SYMBOL

MIN

2.35

0.10

0.33

0.23

12.60

7.40

MAX

2.65

0.30

0.51

0.32

13.00

7.60

NOTES

-B-

A

A1

B

C

D

E

e

0.0926 0.1043

0.0040 0.0118

-

1

2

3

L

0.013

0.0200

9

SEATING PLANE

A

0.0091 0.0125

0.4961 0.5118

0.2914 0.2992

0.050 BSC

-

-A-

o

3

h x 45

D

4

-C-

1.27 BSC

-

α

H

h

0.394

0.010

0.016

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

20

7

o

0

8

0

8

-

NOTES:

Rev. 0 12/93

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Ofﬁce Headquarters

NORTH AMERICA

EUROPE

ASIA

Intersil Corporation

Intersil SA

Mercure Center

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

Intersil (Taiwan) Ltd.

7F-6, No. 101 Fu Hsing North Road

Taipei, Taiwan

Republic of China

TEL: (886) 2 2716 9310

FAX: (886) 2 2715 3029

P. O. Box 883, Mail Stop 53-204

Melbourne, FL 32902

TEL: (321) 724-7000

FAX: (321) 724-7240

12


型号：	HIP6004
厂家：	Intersil
描述：	Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor 降压和同步整流器（ PWM）控制器和输出电压监视器监视器控制器
文件：	总12页 (文件大小：213K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HIP6004 [INTERSIL]

相关型号：

HIP6004A

HIP6004ACB

HIP6004ACB-T

HIP6004A_02

HIP6004B

HIP6004B

HIP6004BCB

HIP6004BCB

HIP6004BCB-T

HIP6004BCBZ

HIP6004BCR

HIP6004BCR