HIP6003 [INTERSIL]
Buck Pulse-Width Modulator (PWM) Controller and Output Voltage Monitor; 降压脉宽调制( PWM)控制器和输出电压监视器型号: | HIP6003 |
厂家: | Intersil |
描述: | Buck Pulse-Width Modulator (PWM) Controller and Output Voltage Monitor |
文件: | 总12页 (文件大小:211K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HIP6003
Data Sheet
March 2000
File Number 4274.2
Buck Pulse-Width Modulator (PWM)
Controller and Output Voltage Monitor
Features
• Drives N-Channel MOSFET
The HIP6003 provides complete control and protection for a
DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive an
N-Channel MOSFET in a standard buck topology. The
HIP6003 integrates all of the control, output adjustment,
monitoring and protection functions into a single package.
• Operates From +5V or +12V Input
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
The output voltage of the converter is easily adjusted and
precisely regulated. The HIP6003 includes a 4-Input
Digital-to-Analog Converter (DAC) that adjusts the output
voltage from 2.0VDC to 3.5VDC in 0.1V increments. The
precision reference and voltage-mode regulator hold the
selected output voltage to within ±1% over temperature and
line voltage variations.
• Excellent Output Voltage Regulation
- ±1% Over Line Voltage and Temperature
• 4-Bit Digital-to-Analog Output Voltage Selection
- Wide Range . . . . . . . . . . . . . . . . . . .2.0VDC to 3.5VDC
- 0.1V Binary Steps
The HIP6003 provides simple, single feedback loop, voltage-
mode control with fast transient response. It includes a
200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/ms slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.
• Power-Good Output Voltage Monitor
• Over-Voltage and Over-Current Fault Monitors
- Does Not Require Extra Current Sensing Element
- Uses MOSFETs r
DS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator Programmable from
50kHz to over 1MHz
The HIP6003 monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within ±10%. The HIP6003
protects against over-current conditions by inhibiting PWM
operation. Built-in over-voltage protection triggers an
external SCR to crowbar the input supply. The HIP6003
Applications
•
Power Supply for Pentium®, Pentium Pro, PowerPC™ and
Alpha™ Microprocessors
•
•
High-Power 5V to 3.xV DC-DC Regulators
Low-Voltage Distributed Power Supplies
monitors the current by using the r
of the upper
DS(ON)
MOSFET which eliminates the need for a current sensing
resistor.
Pinout
Ordering Information
HIP6003
(SOIC)
TOP VIEW
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
16 Ld SOIC
HIP6003CB 0 to 70
M16.15
OCSET
SS
1
2
3
4
5
6
7
8
16 VSEN
15 RT/OVP
14 VCC
VID0
VID1
VID2
VID3
COMP
FB
13 BOOT
12 UGATE
11 PHASE
10 PGOOD
9
GND
Alpha Micro™ is a trademark of Digital Computer Equipment Corporation.
Pentium® is a registered trademark of Intel Corporation.
PowerPC™ is a registered trademark of IBM.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000
1
HIP6003
Typical Application
+12V
V
= +5V OR +12V
IN
VCC
PGOOD
OCSET
BOOT
MONITOR AND
PROTECTION
SS
RT/OVP
OSC
UGATE
PHASE
VID0
HIP6003
VID1
VID2
VID3
+V
OUT
D/A
-
+
+
-
FB
COMP
GND
VSEN
Block Diagram
VCC
VSEN
POWER-ON
RESET (POR)
110%
90%
+
-
PGOOD
+
-
OVER-
VOLTAGE
10µA
115%
+
-
SOFT-
START
SS
+
-
OCSET
OVER-
BOOT
CURRENT
UGATE
200µA
4V
REFERENCE
PHASE
PWM
COMPARATOR
VID0
VID1
VID2
VID3
D/A
CONVERTER
(DAC)
DACOUT
GATE
CONTROL
LOGIC
INHIBIT
PWM
+
-
+
-
ERROR
AMP
FB
GND
COMP
OSCILLATOR
RT/OVP
2
HIP6003
Absolute Maximum Ratings
Thermal Information
o
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Thermal Resistance (Typical, Note 1)
θJA ( C/W)
CC
Boot Voltage, V
- V
. . . . . . . . . . . . . . . . . . . . . . . +15.0V
BOOT
PHASE
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
107
o
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2
o
o
o
(SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage, V
CC
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0 C to 125 C
. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details.
JA
Electrical Specifications Recommended Operating Conditions, unless otherwise noted.
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
UGATE Open
-
5
-
mA
CC
POWER-ON RESET
Rising VCC Threshold
Falling VCC Threshold
V
V
= 4.5V
= 4.5V
-
8.2
-
-
-
10.4
V
V
V
OCSET
-
-
OCSET
Rising V
OCSET
Threshold
1.26
OSCILLATOR
Free Running Frequency
Total Variation
RT = OPEN
185
-15
-
200
-
215
+15
-
kHz
%
6kΩ < RT to GND < 200kΩ
RT = OPEN
Ramp Amplitude
∆V
OSC
1.9
V
P-P
REFERENCE AND DAC
DACOUT Voltage Accuracy
ERROR AMPLIFIER
DC Gain
-1.0
-
+1.0
%
-
-
-
88
15
6
-
-
-
dB
Gain-Bandwidth Product
Slew Rate
GBW
SR
MHz
V/µs
COMP = 10pF
GATE DRIVER
Upper Gate Source
Upper Gate Sink
I
V
- V
= 12V, V = 6V
UGATE
350
-
500
5.5
-
mA
UGATE
BOOT
PHASE
R
10
Ω
UGATE
PROTECTION
Over-Voltage Trip (V
/DACOUT)
-
170
60
-
115
200
-
120
%
µA
mA
µA
SEN
OCSET Current Source
OVP Sourcing Current
Soft Start Current
I
V
V
= 4.5VDC
OVP
230
OCSET
OCSET
I
= 5.5V; V
= 0V
-
-
OVP
SEN
I
10
SS
POWER GOOD
Upper Threshold (V
Lower Threshold (V
/DACOUT)
/DACOUT)
V
V
Rising
106
-
-
111
%
%
%
V
SEN
SEN
Falling
89
-
94
-
SEN
SEN
Hysteresis (V
/DACOUT)
SEN
Upper and Lower Threshold
= -5mA
2
PGOOD Voltage Low
V
I
-
0.5
-
PGOOD
PGOOD
3
HIP6003
Typical Performance Curves
40
35
30
25
20
15
10
5
C
= 3300pF
1000
UGATE
R
PULLUP
T
R
TO V
PULLDOWN
SS
T
TO +12V
100
10
C
= 1000pF
UGATE
C
= 10pF
UGATE
0
100
10
100
SWITCHING FREQUENCY (kHz)
1000
200
300
400
500
600
700
800
900 1000
SWITCHING FREQUENCY (kHz)
FIGURE 1. R RESISTANCE vs FREQUENCY
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
T
Functional Pin Description
COMP (Pin 7) and FB (Pin 8)
OCSET
SS
1
2
3
4
5
6
7
8
16 VSEN
15 RT/OVP
14 VCC
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
VID0
VID1
VID2
VID3
COMP
FB
13 BOOT
12 UGATE
11 PHASE
10 PGOOD
GND (Pin 9)
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
9
GND
PGOOD (Pin 10)
OCSET (Pin 1)
PGOOD is an open collector output used to indicate the
status of the converter output voltage. This pin is pulled low
when the converter output is not within ±10% of the
DACOUT reference voltage.
Connect a resistor (R
) from this pin to the drain of the
, an internal 200µA current source
OCSET
upper MOSFET. R
OCSET
(I
), and the upper MOSFET on-resistance. (r
OCS
) set
DS(ON)
the converter over-current (OC) trip point according to the
PHASE (Pin 11)
following equation:
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for over-current protection. This pin also provides the return
path for the upper gate drive.
I
• R
OCSET
OCS
-------------------------------------------
I
=
PEAK
r
DS(ON)
An over-current trip cycles the soft-start function.
UGATE (Pin 12)
SS (Pin 2)
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10µA current source, sets the soft-
start interval of the converter.
BOOT (Pin 13)
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
VID0-3 (Pins 3-6)
VID0-3 are the input pins to the 4-bit DAC. The states of
these four pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the converter output
voltage. It also sets the PGOOD and OVP thresholds. Table
1 specifies DACOUT for the 16 combinations of DAC inputs.
VCC (Pin 14)
Provide a 12V bias supply for the chip to this pin.
4
HIP6003
SS voltage exceeds the DACOUT voltage and the output
RT/OVP (Pin 15)
voltage is in regulation. This method provides a rapid and
controlled output voltage rise. The PGOOD signal toggles
‘high’ when the output voltage (VSEN pin) is within ±5% of
DACOUT. The 2% hysteresis built into the power good
comparators prevents PGOOD oscillation due to nominal
output voltage ripple.
This pin is multiplexed, providing two functions. The first
function is oscillator switching frequency adjustment. By
placing a resistor (R ) from this pin to GND, the nominal
T
200KHz switching frequency is increased according to the
following equation:
6
5 • 10
(R to GND)
T
--------------------
F
≈ 200kHz +
S
R (kΩ)
T
Conversely, connecting a pull-up resistor (R ) from this pin
PGOOD
(2V/DIV)
T
to V
reduces the switching frequency according to the
CC
0V
following equation:
7
4 • 10
(R to 12V)
SOFT-START
(1V/DIV)
T
--------------------
F
≈ 200kHz +
S
R (kΩ)
T
OUTPUT
VOLTAGE
(1V/DIV)
The second function for this pin is to drive an external SCR
in the event of an overvoltage condition.
0V
VSEN (Pin 16)
0V
t
t
t
3
This pin is connected to the converters output voltage. The
PGOOD and OVP comparator circuits use this signal to
report output voltage status and for overvoltage protection.
1
2
TIME (5ms/DIV)
FIGURE 3. SOFT START INTERVAL
Functional Description
Over-Current Protection
Initialization
The over-current function protects the converter from a
shorted output by using the upper MOSFETs on-resistance,
The HIP6003 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the input supply voltages. The POR monitors the bias
r
to monitor the current. This method enhances the
DS(ON)
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
voltage at the VCC pin and the input voltage (V ) on the
OCSET pin. The level on OCSET is equal to V less a fixed
IN
voltage drop (see over-current protection). The POR function
initiates soft start operation after both input supply voltages
exceed their POR thresholds. For operation with a single
IN
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
)
OCSET
programs the over-current trip level. An internal 200µA current
sink develops a voltage across R that is referenced to
OCSET
V . When the voltage across the upper MOSFET (also
IN
+12V power source, V and V
are equivalent and the
IN
CC
referenced to V ) exceeds the voltage across R
, the
IN OCSET
+12V power source must exceed the rising V
before POR initiates operation.
threshold
CC
over-current function initiates a soft-start sequence. The soft-
start function discharges C with a 10µA current sink and
SS
inhibits PWM operation. The soft-start function recharges
Soft Start
C
, and PWM operation resumes with the error amplifier
SS
The POR function initiates the soft start sequence. An
clamped to the SS voltage. Should an overload occur while
recharging C , the soft start function inhibits PWM operation
internal 10µA current source charges an external capacitor
SS
(C ) on the SS pin to 4V. Soft start clamps the error
SS
while fully charging C to 4V to complete its cycle. Figure 4
SS
amplifier output (COMP pin) and reference input (+ terminal
of error amp) to the SS pin voltage. Figure 3 shows the soft
shows this operation with an overload condition. Note that the
inductor current increases to over 15A during the C
SS
start interval with C = 0.1µF. Initially the clamp on the error
SS
charging interval and causes an over-current trip. The
amplifier (COMP pin) controls the converter’s output voltage.
At t1 in Figure 3, the SS voltage reaches the valley of the
oscillator’s triangle wave. The oscillator’s triangular
waveform is compared to the ramping error amplifier voltage.
This generates PHASE pulses of increasing width that
charge the output capacitor(s). This interval of increasing
pulse width continues to t2. With sufficient output voltage,
the clamp on the reference input controls the output voltage.
This is the interval between t2 and t3 in Figure 3. At t3 the
5
HIP6003
converter dissipates very little power with this method. The
measured input power for the conditions of Figure 4 is 2.5W.
TABLE 1. OUTPUT VOLTAGE PROGRAM
PIN NAME NOMINAL
DACOUT
VOLTAGE
4V
2V
VID3
1
VID2
VID1
1
VID0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
1
1
0
0V
1
0
1
15A
10A
5A
1
0
0
1
1
1
1
1
0
0A
1
0
1
1
0
0
TIME (20ms/DIV)
0
1
1
FIGURE 4. OVER-CURRENT OPERATION
0
1
0
The over-current function will trip at a peak inductor current
0
0
1
(I
determined by:
PEAK)
0
0
0
I
• R
OCSET
OCSET
0
1
1
---------------------------------------------------
I
=
PEAK
r
DS(ON)
0
1
0
where I
is the internal OCSET current source (200µA
0
0
1
OCSET
typical). The OC trip point varies mainly due to the MOSFETs
variations. To avoid over-current tripping in the
0
0
0
r
DS(ON)
NOTE: 0 = Connected to GND or V , 1 = OPEN
SS
normal operating load range, find the R
the equation above with:
resistor from
OCSET
The DAC function is a precision non-inverting summation
amplifier shown in Figure 5. The resistor values shown are
only approximations of the actual precision values used.
Grounding any combination of the VID pins increases the
DACOUT voltage. The ‘open’ circuit voltage on the VID pins
is the band gap reference voltage, 1.26V.
1. The maximum r
at the highest junction temperature.
from the specification table.
DS(ON)
2. The minimum I
OCSET
3. Determine I > I
is the output inductor ripple current.
for I + (∆I)/2, where ∆I
PEAK
PEAK OUT(MAX)
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
BAND GAP
REFERENCE
A small ceramic capacitor should be placed in parallel with
R
to smooth the voltage across R in the
OCSET
OCSET
ERROR
1.26V
presence of switching noise on the input voltage.
DACOUT
AMPLIFIER
+
21.5kΩ
10.7kΩ
5.4kΩ
+
-
-
COMP
VID0
VID1
VID2
VID3
Output Voltage Program
The output voltage of a HIP6003 converter is programmed to
discrete levels between 2.0VDC and 3.5VDC. The voltage
identification (VID) pins program an internal voltage
reference (DACOUT) with a 4-bit digital-to-analog converter
(DAC). The level of DACOUT also sets the PGOOD and
OVP thresholds. Table 1 specifies the DACOUT voltage for
the 16 combinations of open or short connections on the VID
pins. The output voltage should not be adjusted while the
converter is delivering power. Remove input power before
changing the output voltage. Adjusting the output voltage
during operation could toggle the PGOOD signal and
exercise the overvoltage protection.
1.7kΩ
2.7kΩ
DAC
FB
2.9kΩ
FIGURE 5. DAC FUNCTION SCHEMATIC
6
HIP6003
Application Guidelines
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
Layout Considerations
SS
close to the SS pin because the internal current source is
only 10µA. Provide local V decoupling between VCC and
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
CC
GND pins. Locate the capacitor, C
as close as practical
BOOT
to the BOOT and PHASE pins.
Feedback Compensation
V
IN
OSC
DRIVER
PWM
COMPARATOR
LO
V
IN
V
OUT
-
+
PHASE
HIP6003
∆V
OSC
CO
ESR
(PARASITIC)
UGATE
PHASE
Q1
L
O
Z
-
V
FB
OUT
V
E/A
Z
IN
C
IN
+
CO
D2
REFERENCE
ERROR
AMP
RETURN
DETAILED COMPENSATION COMPONENTS
FIGURE 6. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Z
FB
V
OUT
C2
R2
Z
IN
Figure 6 shows the critical power components of the
converter. To minimize the voltage overshoot the
C1
C3
R3
R1
interconnecting wires indicated by heavy lines should be
part of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
COMP
FB
-
+
together as possible. Please note that the capacitors C
IN
HIP6003
and C each represent numerous physical capacitors.
O
DACOUT
Locate the HIP6003 within 3 inches of the MOSFET, Q1.
The circuit traces for the MOSFETs gate and source
connections from the HIP6003 must be sized to handle up to
1A peak current.
FIGURE 8. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Figure 8 highlights the voltage-mode control loop for a buck
converter. The output voltage (V ) is regulated to the
+V
IN
Q1
BOOT
OUT
Reference voltage level. The error amplifier (Error Amp)
D1
L
C
O
BOOT
V
OUT
output (V ) is compared with the oscillator (OSC)
E/A
PHASE
HIP6003
triangular wave to provide a pulse-width modulated (PWM)
V
CC
wave with an amplitude of V at the PHASE node. The
+12V
IN
SS
CO
D2
PWM wave is smoothed by the output filter (L and C ).
O
O
C
VCC
The modulator transfer function is the small-signal transfer
function of V /V . This function is dominated by a DC
C
SS
OUT E/A
Gain and the output filter (L and C ), with a double pole
GND
O
O
break frequency at F and a zero at F
. The DC Gain of
LC
ESR
the modulator is simply the input voltage (V ) divided by the
IN
FIGURE 7. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
peak-to-peak oscillator voltage ∆V
OSC.
Figure 7 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
7
HIP6003
Modulator Break Frequency Equations
100
80
60
40
20
0
F
F
P1
F
F
1
1
Z2
Z1
P2
--------------------------------------
-------------------------------------------
=
ESR
F
F
LC =
2π • (ESR • C
)
2π •
L • C
O O
O
OPEN LOOP
ERROR AMP GAIN
The compensation network consists of the error amplifier
(internal to the HIP6003) and the impedance networks Z
and Z . The goal of the compensation network is to provide
IN
20LOG
(R2/R1)
FB
20LOG
a closed loop transfer function with the highest 0dB crossing
(V /∆V
)
IN OSC
frequency (f
) and adequate phase margin. Phase margin
0dB
COMPENSATION
GAIN
is the difference between the closed loop phase at f
o
and
0dB
MODULATOR
-20
-40
-60
180 . The equations below relate the compensation
GAIN
CLOSED LOOP
GAIN
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
F
LC
F
ESR
100K
FREQUENCY (Hz)
10
100
1K
10K
1M
10M
1. Pick Gain (R2/R1) for desired converter bandwidth
ST
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
2. Place 1 Zero Below Filter’s Double Pole (~75% F
ND
)
LC
3. Place 2
Zero at Filter’s Double Pole
Component Selection Guidelines
ST
4. Place 1 Pole at the ESR Zero
ND
5. Place 2
Pole at Half the Switching Frequency
Output Capacitor Selection
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Compensation Break Frequency Equations
1
1
---------------------------------
2π • R2 • C1
-----------------------------------------------------
F
=
F
=
Z1
P1
C1 • C2
---------------------
2π • R2 •
C1 + C2
1
1
----------------------------------------------------
2π • (R1 + R3) • C3
---------------------------------
F
=
F
=
Z2
P2
2π • R3 • C3
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (Effective Series Resistance) and
voltage rating requirements rather than actual capacitance
requirements.
Figure 9 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 9. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F with the capabilities of
P2
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1µF ceramic
capacitors in the 1206 surface-mount package.
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 9 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
and Z to provide a stable, high bandwidth (BW) overall
FB
IN
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor's ESR value is related to
the case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter.
Work with your capacitor supplier and measure the
8
HIP6003
capacitor’s impedance with frequency to select a suitable
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-
GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
V
- V
V
OUT
V
IN
IN
OUT
∆V
= ∆I x ESR
OUT
------------------------------- ---------------
∆I =
FS x L
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6003 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
MOSFET Selection/Considerations
The HIP6003 requires an N-channel power MOSFET. It
should be selected based upon r
, gate supply
DS(ON)
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for the MOSFET.
Switching losses also contribute to the overall MOSFET power
loss (see the equations below). These equations assume linear
voltage-current transitions and are approximations. The gate-
charge losses are dissipated by the HIP6003 and don't heat the
MOSFET. However, large gate-charge increases the switching
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
interval, t , which increases the upper MOSFET switching
L
x I
L
x I
O TRAN
SW
O
TRAN
-------------------------------
-------------------------------
t
=
t
=
FALL
RISE
losses. Ensure that the MOSFET is within its maximum junction
temperature at high ambient temperature by calculating the
temperature rise according to package thermal-resistance
specifications. A separate heatsink may be necessary
depending upon MOSFET power, package type, ambient
temperature and air flow.
V
- V
V
IN
OUT
OUT
where: I
is the transient load current step, t
is the
is the
TRAN
RISE
response time to the application of load, and t
FALL
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
DACOUT setting. Be sure to check both of these equations
at the minimum and maximum output levels for the worst
case response time. With a +12V input, and output voltage
2
P
P
= I
x r
x D
DS(ON)
COND
O
1
--
=
I
x V x t
x Fs
SW
SW
O
IN
2
level equal to DACOUT, t
FALL
is the longest response time.
Where: D is the duty cycle + V
/V
,
OUT IN
Input Capacitor Selection
t
is the switching interval, and
SW
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place
the small ceramic capacitors physically close to the
MOSFETs and between the drain of Q1 and the anode of
Schottky diode D2.
Fs is the switching frequency
Standard-gate MOSFETs are normally recommended for
use with the HIP6003. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-to-
9
HIP6003
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Schottky Selection
Rectifier D2 conducts when the upper MOSFET Q1 is off.
The diode should be a Schottky type for low power losses.
The power dissipation in the Schottky rectifier is
approximated by:
Figure 10 shows the upper gate drive (BOOT pin) supplied
by a bootstrap circuit from V . The boot capacitor, C
,
CC
BOOT
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
P
= I x V x (1 - D)
O f
CC
COND
less the boot diode drop (V ) when the Schottky diode, D2,
conducts. Logic-level MOSFETs can only be used if the
MOSFETs absolute gate-to-source voltage rating exceeds
D
Where: D is the duty cycle = V /V , and
O
IN
V is the Schottky forward voltage drop
f
the maximum voltage applied to V
.
CC
In addition to power dissipation, package selection and
heatsink requirements are the main design trade-offs in
choosing the Schottky rectifier. Since the three factors are
interrelated, the selection process is an iterative procedure.
The maximum junction temperature of the rectifier must
remain below the manufacturer’s specified value, typically
+12V
D
BOOT
+
-
V
D
+5V OR +12V
VCC
BOOT
o
HIP6003
125 C. By using the package thermal resistance
C
BOOT
Q1
specification and the Schottky power dissipation equation
(shown above), the junction temperature of the rectifier can
be estimated. Be sure to use the available airflow and
ambient temperature to determine the junction temperature
rise. HIP6003 DC-DC Converter Application Circuit.
UGATE
PHASE
NOTE:
≈ V
V
-V
D
G-S
CC
D2
-
+
GND
FIGURE 10. UPPER GATE DRIVE - BOOTSTRAP OPTION
Figure 11 shows the upper gate drive supplied by a direct
connection to V . This option should only be used in
CC
converter systems where the main input voltage is + 5VDC or
less. The peak upper gate-to-source voltage is approximately
V
less the input supply. For +5V main power and + 12VDC
CC
for the bias, the gate-to-source voltage of Q1 is 7V. A logic-
level MOSFET is a good choice for Q1 under these
conditions.
+12V
+5V OR LESS
VCC
BOOT
HIP6003
Q1
UGATE
PHASE
NOTE:
V
≈ V
-5V
CC
G-S
D2
-
+
GND
IGURE 11. UPPER GATE DRIVE - DIRECT V
DRIVE OPTION
CC
10
HIP6003
HIP6003 DC-DC Converter Application Circuit
The figure below shows an application circuit of a DC-DC
Converter for an Intel Pentium Pro microprocessor. Detailed
information on the circuit, including a complete Bill-of-
Materials and circuit board description, can be found in
Application Note AN9664. See Intersil’s home page on the
web: www.intersil.com or Intersil AnswerFAX (321-724-
7800) document # 99664.
L1
F1
+5V
OR
+12V
V
=
IN
1.5µH
C1-C4
4x 330µF
15A
C19-C20
2x 1µF
Q2
2N6394
+12V
R6
10
CR1
V
SS
4148
C14
0.1µF
C18
C21
1µF
VR1
5.1V
R9
10K
V
CC
1000pF
R7
R1
SPARE
14
OCSET
PGOOD
1
MONITOR AND
PROTECTION
2
10
1.1K
SS
PWRGD
13 BOOT
RT/OVP
C13
0.1µF
15
Q1
C22
UGATE
12
OSC
U1
0.1µF
L2
11 PHASE
3
4
VID0
VID1
VID2
VID3
VID0
VID1
VID2
VID3
VSEN
16
V
OUT
7µH
D/A
-
CR2
5
6
+
HIP6003
+
-
FB
8
C5-C12
7
9
8x 1000µF
R2
750K
V
SS
COMP
GND
C15
R8
20K
33pF
C16
R5
90.9K
1000pF
C17
R10
R4
SPARE
15K
C24
R3
3.01K
SPARE
0.1µF
Component Selection Notes:
C5-C12 - 8 each 1000µF 6.3W VDC, Sanyo MV-GX or Equivalent
C1-C4 - 4 each 330µF 25W VDC, Sanyo MV-GX or Equivalent
L1 - Core: Micrometals T60-52; Each Winding: 14 Turns of 17AWG
L2 - Core: Micrometals T44-52; Winding: 7 Turns of 18AWG
CR1 - 1N4148 or Equivalent
CR2 - 25A, 35V Schottky, Motorola MBR2535CTL or Equivalent
Q1 - Intersil MOSFET; RFP70N03
FIGURE 12. PENTIUM PRO DC-DC CONVERTER
11
HIP6003
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
0.25(0.010)
M
B M
H
AREA
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
0.0688
0.0098
0.020
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
1.75
0.25
0.51
0.25
10.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
-
1
2
3
L
-
SEATING PLANE
A
9
-A-
0.0075
0.3859
0.1497
0.0098
0.3937
0.1574
-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
16
16
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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Mercure Center
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Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
12
相关型号:
HIP6004BCB-T
SWITCHING CONTROLLER, 215kHz SWITCHING FREQ-MAX, PDSO20, PLASTIC, MS-013AC, SOIC-20
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