HI1-0518-8 [INTERSIL]
8-Channel/Differential 4-Channel, CMOS High Speed Analog Multiplexer; 8通道/差分4通道， CMOS高速模拟多路复用器
| 型号： | HI1-0518-8 |
| 厂家： | 
Intersil |
| 描述： | 8-Channel/Differential 4-Channel, CMOS High Speed Analog Multiplexer |
| 文件： | 总8页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-518
Data Sheet
June 1999
File Number 3147.2
8-Channel/Differential 4-Channel, CMOS
High Speed Analog Multiplexer
Features
• Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . 130ns
• Settling Time . . . . . . . . . . . . . . . . . . . . . . . . 250ns (0.1%)
• Low Leakage (Typical)
The Hl-518 is a monolithic, dielectrically isolated, high
speed, high performance CMOS analog multiplexer. It offers
unique built-in channel selection decoding plus an inhibit
input for disabling all channels. The dual function of address
- I
- I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10pA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15pA
S(OFF)
D(OFF)
input A enables the Hl-518 to be user programmed either
2
as a single ended 8-Channel multiplexer by connecting ‘Out
• Low Capacitance (Max)
A’ to ‘Out B’ and using A as a digital address input, or as a
2
- C
- C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5pF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10pF
S(OFF)
D(OFF)
4-Channel differential multiplexer by connecting A to the V-
2
supply. The substrate leakages and parasitic capacitances
are reduced substantially by using the Intersil Dielectric
Isolation process to achieve optimum performance in both
• Off Isolation at 500kHz . . . . . . . . . . . . . . . . . 45dB (Min)
• Low Charge Injection Error . . . . . . . . . . . . . . . . . . . 25mV
• Single Ended to Differential Selectable (SDS)
• Logic Level Selectable (LLS)
high and low level signal applications. The low output
o
leakage current (l
< 100pA at 25 C) and fast settling
D(OFF)
(t
= 800ns to 0.01%) characteristics of the device
SETTLE
make it an ideal choice for high speed data acquisition
systems, precision instrumentation, and industrial process
control.
Applications
• Data Acquisition Systems
• Precision Instrumentation
• Industrial Control
Ordering Information
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
18 Ld PDIP
18 Ld CERDIP
Pinout
HI3-0518-5
HI1-0518-5
HI1-0518-8
0 to 75
0 to 75
E18.3
HI-518 (CERDIP, PDIP)
F18.3
F18.3
TOP VIEW
-55 to 125 18 Ld CERDIP
1
2
3
4
5
6
7
8
9
18
17
V+
OUT B
IN8/4B
IN7/3B
IN6/2B
IN5/1B
GND
OUT A
V-
16 IN4/4A
15 IN3/3A
14 IN2/2A
13 IN1/1A
12
11
10
ENABLE
V
/LLS
A
0
DD
A /SDS
A
1
2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HI-518
Truth Tables
TABLE 2. HI-518 USED AS A DIFFERENTIAL 4-CHANNEL
MULTIPLEXER
TABLE 1. HI-518 USED AS AN 8-CHANNEL MULTIPLEXER
OR DUAL 4-CHANNEL MULTIPLEXER (NOTE 1)
USE A AS DIGITAL ADDRESS INPUT
ON CHANNEL TO
A
CONNECTED TO V- SUPPLY
ON CHANNEL TO
2
2
ENABLE
A
A
A
0
OUT A
None
1A
OUT B
None
None
None
None
None
1B
2
1
ENABLE
A
A
OUT A
None
1A
OUT B
None
1B
1
0
L
X
X
X
L
X
X
H
H
H
H
H
H
H
H
L
L
L
L
L
H
L
H
H
H
H
L
L
L
H
L
2A
2A
2B
L
H
H
L
3A
L
H
L
4A
H
H
3A
3B
H
H
H
H
None
None
None
None
H
4A
4B
L
H
L
2B
H
H
3B
H
4B
NOTE:
1. For 8-Channel single ended function, tie “Out A” to “Out B”; for
dual 4-Channel function, use the A address pin to select
2
between Mux A and Mux B, where Mux A is selected with A low.
2
Functional Block Diagram
V
/LLS
DD
IN 1A
N
P
EN
OUT A
IN 4A
A
0
1
DECODER
A
N
N
P
P
A
2
Q
A
2
DECODER
IN 1B
Q
OUT B
IN 4B
DECODER
N
P
INPUT BUFFER AND DECODERS
MULTIPLEXER
SWITCHES
A
DECODE
2
A
Q
H
L
Q
2
H
L
H
L
L
V-
L
2
HI-518
Absolute Maximum Ratings
Thermal Information
o
o
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33V
Thermal Resistance (Typical, Note 2). . . .θ ( C/W)
JA
θ
( C/W)
JC
Analog (V , V
Digital Input Voltage:
) . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V
PDIP Package . . . . . . . . . . . . . . . . . . .
CERDIP Package. . . . . . . . . . . . . . . . .
Maximum Junction Temperature
Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C
90
70
N/A
18
IN OUT
TTL Levels Selected (V /LLS Pin = GND or Open)
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +6V
o
V
A0-1
o
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V
A2/SDS
o
o
CMOS Levels Selected (V /LLS Pin = V
)
DD
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to (V+) +2V
o
V
A0-2
Operating Conditions
Temperature Ranges
HI-518-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
HI-518-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications Supplies = +15V, -15V; V (Logic Level High) = 2.4V, V (Logic Level Low) = 0.8V; V /LLS = GND
AH
AL
DD
(Note 3), Unless Otherwise Specified
-8
-5
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
Access Time, t
25
Full
25
25
25
25
25
25
25
25
25
25
25
-
-
130
175
225
-
-
-
130
175
225
-
ns
ns
ns
ns
ns
ns
ns
mV
dB
pF
pF
pF
pF
A
-
20
120
140
250
800
-
-
20
120
140
250
800
-
Break-Before-Make Delay, t
10
-
10
OPEN
Enable Delay (ON), t
175
175
-
175
175
-
ON(EN)
Enable Delay (OFF), t
Settling Time
-
OFF(EN)
To 0.1%
To 0.01%
Note 6
-
-
-
-
-
-
Charge Injection Error
Off Isolation
-
25
-
-
25
-
Note 7
45
-
-
45
-
-
Channel Input Capacitance, C
S(OFF)
-
5
-
5
Channel Output Capacitance, C
-
-
10
5
-
-
10
5
D(OFF)
Digital Input Capacitance, C
-
-
-
-
A
Input to Output Capacitance, C
-
0.02
-
-
0.02
-
DS(OFF)
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, V (TTL)
Note 3
Note 3
Note 3
Note 3
Full
Full
Full
Full
Full
Full
-
2.4
-
-
-
-
-
-
-
0.8
-
-
2.4
-
-
-
-
-
-
-
0.8
-
V
V
AL
Input High Threshold, V (TTL)
AH
Input Low Threshold, V (CMOS)
0.3V
DD
0.3V
V
AL
DD
Input High Threshold, V (CMOS)
0.7V
DD
-
0.7V
-
V
AH
Input Leakage Current, I
DD
(High)
-
-
1
-
-
1
µA
µA
AH
Input Leakage Current, I (Low)
AL
20
20
ANALOG CHANNEL CHARACTERISTICS
Analog Signal Range, V
Note 4
Note 5
Full
25
-14
-
+14
750
1,000
-
-15
-
+15
750
1,000
-
V
IN
On Resistance, r
-
-
-
-
-
-
-
-
480
-
-
-
-
-
-
-
-
480
Ω
ON
Full
25
-
-
Ω
Off Input Leakage Current, l
S(OFF)
0.01
0.01
nA
nA
nA
nA
nA
nA
Full
25
-
50
-
-
50
-
Off Output Leakage Current, I
D(OFF)
0.015
0.015
Full
25
-
0.015
-
50
-
-
0.015
-
50
-
On Channel Leakage Current, I
D(ON)
Full
50
50
POWER SUPPLY CHARACTERISTICS
Power Dissipation, P
Full
-
-
450
-
-
540
mW
D
3
HI-518
Electrical Specifications Supplies = +15V, -15V; V (Logic Level High) = 2.4V, V (Logic Level Low) = 0.8V; V /LLS = GND
AH
AL
DD
(Note 3), Unless Otherwise Specified (Continued)
-8
-5
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
MIN
TYP
MAX
15
MIN
TYP
MAX
18
UNITS
mA
I+, Current
I-, Current
NOTES:
V
= 2.4V
Full
Full
-
-
-
-
-
-
-
-
EN
15
18
mA
3. V /LLS pin = open or grounded for TTL compatibility. V /LLS pin = V
DD DD DD
for CMOS compatibility.
o
4. At temperatures above 90 C, care must be taken to assure V remains at least 1.0V below the V
IN SUPPLY
for proper operation.
5. V = ±10V, I
IN
= -100µA.
OUT
6. V = 0V, C = 100pF, enable input pulse = 3V, f = 500kHz.
IN
L
7. C = 40pF, R = 1K, V
EN
= 0.8V, V = 3V
IN
, f = 500kHz. Due to the pin to pin capacitance between IN 8/4B and OUT B, channel 8/4B
RMS
L
L
exhibits 60dB of OFF isolation under the above test conditions.
Test Circuits and Waveforms V /LLS = GND, Unless Otherwise Specified
DD
I
100µA
OUT
0.8V
EN
V
2
OUT
IN
A
I
D(OFF)
OUT
V
2
±
±10V
10V
r
=
±10V
ON
V
IN
100µA
FIGURE 1. ON RESISTANCE TEST CIRCUIT
FIGURE 2. I
TEST CIRCUIT (NOTE 8)
D(OFF)
OUT
OUT
I
EN
S(OFF)
A
A
I
D(ON)
EN
0.8V
A
A
0
2
±
±
±10V
10V
10V
±10V
2.4V
FIGURE 3. I
S(OFF)
TEST CIRCUIT (NOTE 8)
FIGURE 4. I
TEST CIRCUIT (NOTE 8)
D(ON)
+15V
V+
3.5V
ADDRESS
DRIVE (V )
A
±10V
IN 1
50%
A /SDS
2
IN 2-7
0V
V
50Ω
A
1
A
±
10V
IN 8
A
0
OUTA
+10V
EN
2.4V
OUTB
V-
OUTPUT
10%
V
/LLS
50
10
DD
pF
kΩ
-10V
GND
t
A
-15V
FIGURE 5A. MEASUREMENT POINTS
FIGURE 5B. TEST CIRCUIT
FIGURE 5. ACCESS TIME
NOTE:
8. Two measurements per channel: ±10V and 10V. (Two measurements per device for I
±10V and 10V.)
D(OFF)
4
HI-518
Test Circuits and Waveforms V /LLS = GND, Unless Otherwise Specified (Continued)
DD
+15V
V+
3.5V
+5V
IN 1
A /SDS
2
ADDRESS
DRIVE (V )
IN 2-7
A
0V
V
A
A
A
50Ω
1
IN 8
OUTPUT
OUTA
0
V
OUT
S
ON 50%
50% S ON
OUTB
V-
1
8
EN
V
2.4V
800
Ω
/LLS
12.5pF
DD
t
GND
OPEN
-15V
FIGURE 6A. MEASUREMENT POINTS
FIGURE 6. BREAK-BEFORE-MAKE DELAY
FIGURE 6B. TEST CIRCUIT
+15V
V+
3.5V
ENABLE
DRIVE (V )
50%
50%
+10V
IN 1
A
0V
A /SDS
2
OUTPUT
10%
IN 2-8
90%
A
A
1
0
0V
EN
V
OUTA
V-
t
50
Ω
/LLS
800
Ω
ON(EN)
DD
12.5pF
V
A
t
OFF(EN)
GND
-15V
FIGURE 7A. MEASUREMENT POINTS
FIGURE 7B. TEST CIRCUIT
FIGURE 7. ENABLE DELAY
+15V
V+
2.4V
A , A ,
0
1
3V
A /SDS
2
0V
V
A
OUT
V
OUT
∆V
O
IN
A OR B
V
OUT
C
= 100pF
L
EN
GND
V
/LLS V-
-15V
DD
V
A
FIGURE 8A. MEASUREMENT POINTS
∆V is the measured voltage error due to charge injection. The error
FIGURE 8B. TEST CIRCUIT
O
in coulombs is Q = C x ∆V .
L
O
FIGURE 8. CHARGE INJECTION
5
HI-518
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
89 mils x 93 mils
Type: Nitride Over Silox
Nitride Thickness: 3.5kÅ ±1.0kÅ
Silox Thickness: 12kÅ ±2.0kÅ
METALLIZATION:
Type: AlCu
Thickness: 16kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
5
2
1.43 x 10 A/cm
SUBSTRATE POTENTIAL (NOTE):
TRANSISTOR COUNT:
-V
SUPPLY
356
PROCESS:
CMOS-DI
NOTE: The substrate appears resistive to the -V
SUPPLY
terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a
conductor at -V
potential.
SUPPLY
Metallization Mask Layout
HI-518
A
A
A /SDS
V
/LLS GND
DD
EN
0
1
2
IN 1/1A
IN 2/2A
IN 5/1B
IN 6/2B
IN 7/3B
IN 8/4B
IN 3/3A
IN 4/4A
V-
OUT A
OUT B
V+
6
HI-518
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F18.3 MIL-STD-1835 GDIP1-T18 (D-6, CONFIGURATION A)
18 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.960
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
24.38
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.070
-
3.18
5.08
1.78
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
aaa
bbb
ccc
M
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
18
18
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
7
HI-518
Dual-In-Line Plastic Packages (PDIP)
E18.3 (JEDEC MS-001-BC ISSUE D)
N
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.845
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
21.47
0.13
7.62
6.10
4
D
E
BASE
PLANE
0.195
0.022
0.070
0.014
0.880
-
4.95
0.558
1.77
0.355
22.35
-
-
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
-
eA
A1
A
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
e
-
0.430
0.150
-
10.92
3.81
7
B
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
18
18
JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
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HI1-0546-2
Single 16 and 8, Differential 8-Channel and 4-Channel CMOS Analog MUXs with Active Overvoltage Protection
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HI1-0546-5
Single 16 and 8, Differential 8-Channel and 4-Channel CMOS Analog MUXs with Active Overvoltage Protection
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