HI1-0524-5 [INTERSIL]
4-Channel Wideband and Video Multiplexer; 4通道宽带和视频多路复用器
| 型号： | HI1-0524-5 |
| 厂家： | 
Intersil |
| 描述： | 4-Channel Wideband and Video Multiplexer |
| 文件： | 总6页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-524
Data Sheet
July 1999
File Number 3148.2
4-Channel Wideband and Video
Features
Multiplexer
• Crosstalk (10MHz) . . . . . . . . . . . . . . . . . . . . . . . . <-60dB
• Fast Access Time . . . . . . . . . . . . . . . . . . . . . . . . . 150ns
• Fast Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . 200ns
• TTL Compatible
The HI-524 is a 4-Channel CMOS analog multiplexer designed
to process single-ended signals with bandwidths up to 10MHz.
The chip includes a 1 of 4 decoder for channel selection and an
enable input to inhibit all channels (chip select).
Three CMOS transmission gates are used in each channel,
as compared to the single gate in more conventional CMOS
multiplexers. This provides a double barrier to the unwanted
coupling of signals from each input to the output. In addition,
Dielectric Isolation (DI) processing helps to insure the
Crosstalk is less than -60dB at 10MHz.
Applications
• Wideband Switching
• Radar
• TV Video
The HI-524 is designed to operate into a wideband buffer
amplifier such as the Intersil HA-2541. The multiplexer chip
includes two “ON” switches in series, for use as a feedback
element with the amplifier. This feedback resistance
• ECM
Functional Diagram
IN1
matches and tracks the channel ON resistance, to minimize
FB (IN)
the amplifier V
OS
and its variation with temperature.
The HI-524 is well suited to the rapid switching of video and
other wideband signals in telemetry, instrumentation, radar
and video systems.
SIG GND
IN2
FB (OUT)
Ordering Information
SIG GND
OUTPUT
IN3
PART
NUMBER
TEMP. RANGE
o
( C)
PACKAGE
18 Ld CERDIP F18.3
18 Ld PDIP E18.3
PKG. NO.
HI1-0524-5
HI3-0524-5
0 to 75
0 to 75
SIG GND
IN4
1 OF 4
DECODER
Pinout
SIG GND
SIG GND
HI-524 (CERDIP, PDIP)
TOP VIEW
1
-15V SUP +15V EN
GND
A
A
1
0
1
2
3
4
5
6
7
8
9
18
17
+V
OUT
FB (IN)
-V
TRUTH TABLE
SIG GND
SIG GND
IN4
16 FB (OUT)
15 SIG GND
14 IN2
A
A
EN
L
ON CHANNEL
1
0
X
X
None
SIG GND
IN3
13 SIG GND
L
L
L
H
L
H
1 (Note)
12
11
10
IN1
EN
H
2
3
4
SUPPLY GND
H
H
H
A
1
A
0
H
H
NOTE: Channel 1 is shown selected in the Functional Diagram.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
HI-524
Absolute Maximum Ratings
Thermal Information
o
o
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
Digital Input Voltage (V , V ) . . . . . . . . . . . . . . . . . . . . -6V to +6V
EN
A
CERDIP Package. . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
75
80
20
N/A
Analog Signal (V , V
). . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V
IN OUT
Either Supply to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V
o
Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
o
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
Operating Conditions
o
o
Maximum Storage Temperature. . . . . . . . . . . . . . . . -65 C to 150 C
Temperature Range
HI-524-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
o
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . 300 C
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications Supplies = +15V, -15V; V (Logic Level High) = 2.4V, V (Logic Level Low) = 0.5V; V = 2.4V,
AH
AL
EN
Unless Otherwise Specified
-5
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
Access Time, t
Note 5
Note 5
25
25
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
150
20
300
ns
ns
ns
ns
ns
ns
dB
pF
pF
pF
A
Break-Before-Make Delay, t
OPEN
-
-
-
-
-
-
-
-
-
Enable Delay (ON), t
R
R
= 500Ω
= 500Ω
180
180
200
600
-65
4
ON (EN)
L
L
Enable Delay (OFF), t
OFF (EN)
Settling Time (Note 5)
To 0.1%
To 0.01%
Note 6
Crosstalk
Channel Input Capacitance, C
S(OFF)
Channel Output Capacitance, C
D(OFF)
10
Digital Input Capacitance, C
5
A
DIGITAL INPUT SPECIFICATIONS
Input Low Threshold (TTL), V
Full
Full
Full
Full
-
2.4
-
-
0.8
-
V
V
AL
Input High Threshold (TTL), V
-
0.05
-
AH
Input Leakage Current (High), I
1
µA
µA
AH
AL
Input Leakage Current (Low), I
-
25
ANALOG CHANNEL SPECIFICATIONS
Analog Signal Range, V
Full
25
-10
-
700
-
+10
-
V
Ω
lN
On Resistance, r
ON
Note 2
Note 3
Note 3
Note 3
Note 4
-
-
-
-
-
-
-
-
-
Full
25
1.5
-
kΩ
nA
nA
nA
nA
nA
nA
MHz
Off Input Leakage Current, I
0.2
-
S (OFF)
Full
25
50
-
Off Output Leakage Current, I
D (OFF)
0.2
-
Full
25
50
-
On Channel Leakage Current, I
-3dB Bandwidth
0.7
-
D (ON)
Full
25
50
-
8
2
HI-524
Electrical Specifications Supplies = +15V, -15V; V (Logic Level High) = 2.4V, V (Logic Level Low) = 0.5V; V = 2.4V,
AH
AL
EN
Unless Otherwise Specified (Continued)
-5
TEST
CONDITIONS
TEMP
( C)
o
PARAMETER
POWER SUPPLY CHARACTERISTICS
MIN
TYP
MAX
UNITS
Power Dissipation, P
Current, I+
Full
Full
Full
-
-
-
-
-
-
750
25
mW
mA
mA
D
Note 7
Note 7
Current, I-
25
NOTES:
2. V = 0V; l
lN
= 100µA (See Test Circuit section).
OUT
3. V = ±10V; V = ±10V. (See Test Circuit section).
IN
O
4. MUX output is buffered with HA-5033 amplifier.
±
5. 6V Step, ±3V to 3V, See Test Circuit section.
6. V = 10MHz, 3V
IN
on one channel, with any other channel selected. (Worst case is channel 3 selected with input on channel 4.) MUX output
P-P
is buffered with HA-2541 as shown in Applications section. Terminate all channels with 75Ω.
7. Supply currents vary less than 0.5mA for switching rates from DC to 2MHz.
o
Test Circuits and Waveforms T = 25 C, V
= ±15V, V = 2.4V, V = 0.8V, Unless Otherwise Specified
SUPPLY AH AL
A
I
100µA
OUT
V
2
IN
OUT
r
V
2
V
=
IN
ON
100µA
FIGURE 1A. TEST CIRCUIT
1,000
1,000
900
800
700
600
500
400
V
= 0V
IN
o
125 C
900
800
700
o
25 C
o
-55 C
9
10
11
12
13
14
15
-10
-8
-6
-4
-2
0
(V)
2
4
6
8
10
SUPPLY VOLTAGE (±V)
V
IN
FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE
FIGURE 1C. ON RESISTANCE vs SUPPLY VOLTAGE
FIGURE 1. ON RESISTANCE
3
HI-524
o
Test Circuits and Waveforms T = 25 C, V
= ±15V, V = 2.4V, V = 0.8V, Unless Otherwise Specified (Continued)
A
SUPPLY
AH
AL
I
D(ON)
1.0
0.8V
EN
OUT
I
S(OFF)
I
D(OFF)
A
I
D(OFF)
±
±10V
10V
0.1
0
25
50
75
100
125
150
o
TEMPERATURE ( C)
FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE
FIGURE 2B. I
TEST CIRCUIT (NOTE 8)
D(OFF)
OUT
0.8V
OUT
I
A
S(OFF)
I
EN
A
D(ON)
EN
A
1
A
0
±
10V
±
±10V
±10V
10V
+2.4V
FIGURE 2C. I
TEST CIRCUIT (NOTE 8)
FIGURE 2D. I
TEST CIRCUIT (NOTE 8)
S(OFF)
D(ON)
FIGURE 2. LEAKAGE CURRENTS
HA-524
IN1
IN2
±3V
V
= 2.4V
= 0.8V
AH
ADDRESS DRIVE (V )
A
HA-2541
1.6V
2
18
OUTPUT
+
-
V
AL
75Ω
20pF
(NOTE 10)
+3V
IN3
IN4
16
ACCESS TIME, t
A
SETTLING TIME, t
S
±
3V
A
A
EN
0
1
HA-2541
OUTPUT
10%
-3V
5V
±0.1% OF FULL SCALE
(OR ±0.01%)
V
50Ω
A
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. SETTLING TIME, ACCESS TIME, BREAK-BEFORE-MAKE DELAY (NOTE 9)
NOTES:
8. Two measurements per channel: ±10V and 10V. (Two measurements per device for I
9. The Break-Before-Make test requires inputs 1 and 4 at the same voltage.
10. Capacitor value may be selected to optimize AC performance.
±10V and 10V.)
D(OFF)
4
HI-524
o
Test Circuits and Waveforms T = 25 C, V
= ±15V, V = 2.4V, V = 0.8V, Unless Otherwise Specified (Continued)
A
SUPPLY
AH
AL
5V/DIV.
V
INPUT
A
1V/DIV.
S
ON
S ON
4
1
OUTPUT
50ns/DIV.
FIGURE 4. ACCESS TIME WAVEFORMS
Application Information
Often it is desirable to buffer the Hl-524 output, to avoid
loading errors due to the channel “ON” resistance:
Note that the on-chip feedback element between pins 16 and
18 includes two switches in series, to simulate a channel
resistance. These switches open for V
= Low. This allows
EN
HA-524
two or more Hl-524s to operate into one HA-2541, with their
feedback elements connected in parallel. Thus, only the
selected multiplexer provides feedback, and the amplifier
remains stable.
12
CH1
75Ω
HA-2541
All Hl-524 pins labeled ‘SlG GND’ (pins 3, 4, 6, 13, 15)
should be externally connected to signal ground for best
crosstalk performance.
14
7
2
18
CH2
75Ω
+
-
BUFFERED
OUTPUT
20pF
(NOTE)
Bypass capacitors (0.1µF to 1µF) are recommended from
each HI-524 supply pin to power ground (pins 1 and 17 to
pin 8). Locate the buffer amplifier near the Hl-524 so the two
capacitors may bypass both devices.
16
CH3
75Ω
If an analog input 1V or greater is present when supplies are
off, a low resistance is seen from that input to a supply line.
(For example, the resistance is approximately 160Ω for an
input of -3V.) Current flow may be blocked by a diode in each
supply line, or limited by a resistor in series with each
channel. The best solution, of course, is to arrange that no
digital or analog inputs are present when the power supplies
are off.
5
CH4
75Ω
NOTE: Capacitor value may be selected to optimize AC performance.
FIGURE 5.
The buffer amplifier should offer sufficient bandwidth and
slew rate to avoid degradation of the anticipated signals. For
video switching, the HA-5033 and HA-2542 offer good
performance plus ±100mA output current for driving coaxial
cables. For general wideband applications, the HA-2541
offers the convenience of unity gain stability plus 90ns
settling (to ±0.1%) and ±10V output swing. Also, the Hl-524
includes a feedback resistance for use with the HA-2541.
This resistance matches and tracks the channel “ON”
resistance, to minimize offset voltage due to the buffer's bias
currents.
5
HI-524
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
2250µm x 3720µm x 485µm
Type: Nitride Over Silox
Nitride Thickness: 3.5kÅ ±1kÅ
Silox Thickness: 12kÅ ±2kÅ
METALLIZATION:
Type: CuAl
Thickness: 16kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
5
2
1.58 x 10 A/cm
Metallization Mask Layout
HI-524
EN AO
SUPPLY
GND
A1
IN1
IN3
SIG
GND
SIG
GND
IN2
IN4
SIG
GND
SIG
GND
FB (OUT)
SIG
GND
-V FB (IN)
+V OUT
6
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